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Multidisciplinary Heat Generating Logic Block Placement Optimization Using Genetic Algorithm

[+] Author Affiliations
Tohru Suwa, Hamid Hadim

Stevens Institute of Technology, Hoboken, NJ

Paper No. IPACK2007-33443, pp. 773-779; 7 pages
  • ASME 2007 InterPACK Conference collocated with the ASME/JSME 2007 Thermal Engineering Heat Transfer Summer Conference
  • ASME 2007 InterPACK Conference, Volume 1
  • Vancouver, British Columbia, Canada, July 8–12, 2007
  • Conference Sponsors: Electronic and Photonic Packaging Division
  • ISBN: 0-7918-4277-0 | eISBN: 0-7918-3801-3
  • Copyright © 2007 by ASME


A multidisciplinary optimization methodology for placement of heat generating logic blocks on integrated circuit chips is presented. The methodology includes thermal and wiring length criteria, which are optimized simultaneously using the genetic algorithm. An effective thermal performance prediction methodology based on a superposition method is used to calculate the temperature distribution on a silicon chip due to multiple heat generating logic blocks. Using the superposition method, the predicted temperature distribution in the silicon chip is obtained in a much shorter time than with a detailed finite element model and with comparable accuracy. The main advantage of the present multi-disciplinary design and optimization methodology is its ability to handle multiple design objectives simultaneously for optimized placement of heat generating logic blocks. To demonstrate its capabilities, the present methodology is applied to benchmark cases involving placement optimization of multiple heat generating logic blocks on a silicon chip. The results indicate that the maximum temperature on a silicon chip can be reduced by up to 7.5 °C, compared with the case in which only the wiring length is minimized.

Copyright © 2007 by ASME



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