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High Resolution Die Stress Mapping Using Arrays of CMOS Sensors

[+] Author Affiliations
Yonggang Chen, Richard C. Jaeger, Jeffrey C. Suhling

Auburn University, Auburn, AL

Paper No. IPACK2007-33569, pp. 285-295; 11 pages
  • ASME 2007 InterPACK Conference collocated with the ASME/JSME 2007 Thermal Engineering Heat Transfer Summer Conference
  • ASME 2007 InterPACK Conference, Volume 1
  • Vancouver, British Columbia, Canada, July 8–12, 2007
  • Conference Sponsors: Electronic and Photonic Packaging Division
  • ISBN: 0-7918-4277-0 | eISBN: 0-7918-3801-3
  • Copyright © 2007 by ASME


This paper reports high resolution die stress measurements using a multiplexed array of 512 current mirror type CMOS piezoresistive FET stress sensor cells fabricated on an MOSIS tiny chip. Using 1.5 μm CMOS technology, a stress mapping resolution of 256 points/mm2 has been obtained, providing high spatial resolution mapping of the stress on the surface of the integrated circuit die. Driven by an on-chip counter, the sequentially scanned array efficiently maps the two-dimensional stress field. The sensor array is calibrated using a chip-on-beam calibration technique. These CMOS sensor arrays have been used to map stress on the die in the chip-on-beam configuration under four-point-bending load, in encapsulated chip-on-beam samples, and in DIP40 packages with cavities filled with underfill. The measured stress distribution agrees well with finite element simulation results, and permit smooth measurement of stress gradients on the surface of the integrated circuit die. The results give clear verification that the NMOS PiFET sensors are indeed responding to shear stresses.

Copyright © 2007 by ASME



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