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ASME Conference Presenter Attendance Policy and Archival Proceedings

2017;():V001T00A001. doi:10.1115/IPACK2017-NS.
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This online compilation of papers from the ASME 2017 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems (InterPACK2017) represents the archival version of the Conference Proceedings. According to ASME’s conference presenter attendance policy, if a paper is not presented at the Conference by an author of the paper, the paper will not be published in the official archival Proceedings, which are registered with the Library of Congress and are submitted for abstracting and indexing. The paper also will not be published in The ASME Digital Collection and may not be cited as a published paper.

Commentary by Dr. Valentin Fuster

Heterogeneous Integration: Micro-Systems With Diverse Functionality: 2.5D/3D Integration

2017;():V001T01A001. doi:10.1115/IPACK2017-74173.

The ability to create 3D ICs can significantly increase transistor packing density, reduce chip area and power dissipation leading to possibilities of large-scale on-chip integration of different systems. A promising process for this application is the microscale additive manufacturing (AM) of 3D interconnect structures and capability of writing 3D metal structures with feature sizes of approximately 1 μm on a variety of substrates. Current microscale AM techniques are limited in their capabilities to produce 3D conductive interconnect structures. This paper presents the design and development of a new micro AM technique — microscale selective laser sintering (μ-SLS) — which overcomes many of the limitations of other micro AM processes to achieve true micron sized, electrically conductive features on a variety of substrates.

This paper will present preliminary results from set of sintering experiments on copper (Cu) nanoparticle (NP) ink using the continuous wave (CW) laser to be employed in the μ-SLS system which will be compared to Cu NP sintering results produced with other laser sources such as nanosecond (ns) & femtosecond (fs) lasers. This study is important to estimate the optimum working range of fluence/irradiance to be used in the μ-SLS setup depending upon the laser employed. In general, it provides an experimental estimate of the sintering fluence/irradiance range of Cu NPs depending upon the type of laser used and compares their sintering quality based on morphology of sintered spots.

Commentary by Dr. Valentin Fuster
2017;():V001T01A002. doi:10.1115/IPACK2017-74222.

During the last few decades, the microelectronics packaging industry has moved into the 2.5D to 3D space for increased density, functionality, and speed. Similar concepts and ideas for developing 2.5D to 3D power electronics packaging are desired to achieve even greater efficiency and power density over conventional power electronics packaging methods. Wide-band gap (WBG) semiconductors, such as SiC and GaN, have accelerated the ability to shrink the volumetric size and weight of these power conversion systems, and thus improve overall power density metrics, due to their inherent high frequency, high temperature, and high voltage capabilities. WBG power semiconductor devices, with these attributes, thus make themselves excellent candidates for more aggressive packaging, compared to Si-derived packaging, in order to not only take full advantage of the WBG device ratings, but also to achieve high power densities of the overall power conversion systems. Already different/multiple power semiconductor devices are being combined by processing them together on the same die to boost electrical performance and increase power density. It can be assumed that further levels of integration will be sought after for the next levels of packaging to enable similar gains, especially with the advent of double side solderable die. The 3D stacking of die, components, and substrates creates the question of how well will each of these perform in close proximity to each other. This work focuses on the numerical simulation and experimental measurements to predict the temperature distribution of power converters built in a stacked fashion. Thermal models of a stacked power electronic switching unit — a silicon controlled rectifier and anti-parallel diode — are modeled under the assumption of equally sized die. Temperature field maps are generated for 20W to 250W of power dissipations across the power semiconductor die. Thermal models are then compared with matching experimental setups to observe the effect of switching unit placement attached to a given substrate on the die junction temperatures for various scenarios of thermal crosstalk. Results from this work are expected to aid in the development 2.5D to 3D power electronic packaging by predicting thermal performance of stacked, ultra-dense, WBG device -based packages.

Commentary by Dr. Valentin Fuster

Heterogeneous Integration: Micro-Systems With Diverse Functionality: Additive and Advanced Manufacturing

2017;():V001T01A003. doi:10.1115/IPACK2017-74059.

Metal lines used in integrated circuits (ICs) become narrow for raising the device performance. Due to scaling down of the ICs, current density and Joule heating are increased, which induces electromigration (EM) damage. EM is transportation phenomena of metallic atoms caused by electron wind under high current density. EM leads to hillock and void formation in the metal line, thus EM should be considered to evaluate the performances of the device safe. It is known that a value of threshold current density which is critical current density of the EM damage exists in via-connected and passivated lines. In this study, the effect of line geometry on the threshold current density is discussed in the case of taper-shaped line. The evaluation method of threshold current density is conducted based on numerical simulation technique with building-up processes of atomic density distribution in the metal line by using a governing parameter of EM damage. As the simulation results, threshold current density increased in the cases of shorter line length, lower temperature, and wider width in cathode side. Furthermore, a new parameter was proposed for simplified evaluation of the threshold current density in taper-shaped lines. The evaluation method is able to apply various line shapes and conditions and it is expected to use for confirmation of the reliability of the lines in circuit design processes.

Commentary by Dr. Valentin Fuster
2017;():V001T01A004. doi:10.1115/IPACK2017-74092.

Reservoir structures are often constructed in the interconnection to prevent the electromigration damages. In this study, a numerical simulation technique for analyzing the atomic density distributions in the line under high current density was used to evaluate the effects of reservoir length and location on the threshold current density considering void and hillock generations.

The threshold current density is determined when the local atomic density in the line reaches the upper critical value for hillock creation or the lower critical value for void generation. Atomic density distributions in the line were simulated when cathode and anode reservoir lengths were changed.

The threshold current density considering void formation became higher with longer cathode reservoir and shorter anode reservoir. However, opposite results obtained in the case of hillock formation. It was found that there was an optimum value of reservoir length, corresponding to both critical values of hillock and void initiation.

Commentary by Dr. Valentin Fuster
2017;():V001T01A005. doi:10.1115/IPACK2017-74306.

With recent advancements in additive manufacturing (AM) technology, it is possible to deposit copper conductive paths and insulation layers of an electric machine in a selective controlled manner. AM of copper enables higher fill factors that improves the internal thermal conduction in the stator core of the electric machine (induction motor), which will enhance its efficiency and power density. This will reduce the motor size and weight and make it more suitable for aerospace and electric vehicle applications, while reducing / eliminating the rare-earth dependency. The objective of this paper is to present the challenges associated with AM of copper coils having 1×1mm cross section and complex features that are used in producing ultra-high efficiency induction motor for traction applications. The paper also proposes different approaches that were used by the authors in attempts to overcome those challenges.

Commentary by Dr. Valentin Fuster

Heterogeneous Integration: Micro-Systems With Diverse Functionality: Advanced Materials and Interfaces for Emerging Electronic Packaging Paradigms

2017;():V001T01A006. doi:10.1115/IPACK2017-74090.

Enhanced boiling is one of the popular cooling schemes in thermal management due to its superior heat transfer characteristics. This study demonstrates the ability of copper inverse opal (CIO) porous structures to enhance pool boiling performance using a thin CIO film with a thickness of ∼ 10 μm and pore diameter of 5 μm. The microfabricated CIO film increases microscale surface roughness that in turn leads to more active nucleation sites thus improved boiling performance parameters such as heat transfer coefficient and critical heat flux compared to those of smooth Si surfaces. The experimental results for CIO film show a maximum critical heat flux of 225 W/cm2 (at 16.2°C superheat) or about 3 times higher than that of smooth Si surface (80 W/cm2 at 21.6°C superheat). Optical images showing bubble formation on the microporous copper surface are captured to provide detailed information of bubble departure diameter and frequency.

Commentary by Dr. Valentin Fuster

Heterogeneous Integration: Micro-Systems With Diverse Functionality: Advanced Packaging, Interconnects and Substrate Technologies

2017;():V001T01A007. doi:10.1115/IPACK2017-74010.

In this study, the peeling process of UV-curable pressure sensitive adhesive tape from bump wafer is investigated through the use of finite element analysis, observation of high speed video, and actual wafer back-grinding process testing. In our experiment, a large deformation of adhesive is observed at the edge of bottom of bump, appearing on the side of the bump opposite tape-peeling direction when observed with high speed microscope video. The largely deformed adhesive creates a string shaped elongation. The adhesive residue is caused by the fracture of the adhesive string. We investigated how to generate the adhesive string in the tape-peeling process through the use of finite element analysis. In this analysis, a cohesive element is introduced into the adhesive layer. The analytical result shows the adhesive string at the same position of experiment and the stress distribution is different between the string part and the other area of adhesive. The influence of peeling angle and bump size is also investigated by the same finite element model. As a result, higher peeling angle and smaller bump sizes shows a shorter adhesive string, which lowers the risk of adhesive residue.

Commentary by Dr. Valentin Fuster
2017;():V001T01A008. doi:10.1115/IPACK2017-74026.

Next generation high speed network/communication packages require much larger die sizes and increased ball counts (>3000) to meet high speed, high input/output (I/O) functionality and improved reliability performance. Demand for such high speed large flip chip packages create an opportunity for highly integrated multi-chip modules (MCM’s) and 2.5D/3D silicon (Si) interposer packages which are gradually emerging to meet these requirements. Achieving both increased margins in the power delivery network and increased functionality in next generation high speed network/communication applications requires extremely efficient, low loss package designs with body sizes 50×50mm or larger. One of the biggest challenges for such large die, large body packages is how effectively the assembly risk can be mitigated while fulfilling long term package reliability and functionality. The work presented in this paper describes key factors for mitigating several assembly related issues in the industry, including package warpage/co planarity, and the identification of the optimum processes and materials for successfully manufacturing large body flip chip packages with high assembly yields.

As the body sizes and die sizes increase, the chip-to-package interaction failure risk increases significantly due to a larger distance to neutral point (DNP). Typical assembly risks are extreme low-k (ELK) delamination (white bumps) during the chip joining process, bump tearing or cracking, underfill delamination, and warpage issues. A comprehensive experiment was carried out to achieve the objective of the work. A test vehicle was developed using a 21×22mm2, flip chip copper (Cu) column bumped die placed onto a 50×50mm body size, using a multi-layer substrate with full array BGA footprint and ample passive components in the package. Processes were developed to optimize assembly yield and package reliability, including an extensive board level reliability test. Assembly materials were selected to achieve excellent assembly yield, high thermo-mechanical reliability, and increased package functionality.

Commentary by Dr. Valentin Fuster
2017;():V001T01A009. doi:10.1115/IPACK2017-74133.

The coarse heterogeneous microstructure of SAC alloys makes the behavior of interconnections highly sensitive to its geometric length-scale. Heterogeneous integration and the resulting increase in package complexity and miniaturization are making this scale-effect ever more important. This scale effect derives from the anisotropy of tin and the coarse multi-tiered microstructural heterogeneities in SAC solders. As a result, no two joints behave the same and every joint is unique depending on its specific microstructure. Product teams responsible for reliable heterogeneous integration have to ensure that they have adequate methods to deal with this variability.

This paper highlights the multi-tiered microstructural morphology in SAC solders due to the solidification and crystallization process. At the highest tier in the joint microstructure are individual (highly anisotropic) grains that can be 100s of microns in size. At the next lower tier the primary heterogeneity is due to individual dendrites of pro-eutectic β tin, that can have lobes as large as 10–20 microns. At the next lower tier the characteristic heterogeneity is a eutectic mix of nanoscale Ag3Sn IMC particles dispersed in a Sn matrix.

Researchers have long recognized that the grain morphology is extremely important to mechanical behavior of BGA solder joints because they are coarse-grained (i.e. there may be only a few anisotropic grains in each BGA solder joint). However, heterogeneous integration has now led to joints that are much smaller (less than 100 microns tall), thus making them of the same length-scale as individual tin dendrites within each grain. In other words, there may be just a few dendrites through the thickness of the joint. Unfortunately, very little attention has focused on SAC behavior at such a small length-scale. This study focuses on the effect of the tin-dendrite morphology on the effective behavior of SAC solder joints, using a combination of experiments and multi-tiered anisotropic models that combine dislocation nano-mechanics with composite micromechanics. The volume fraction of β-Sn dendrite within one crystal could vary from 20% to 80%, depending on the time and temperature above the liquidus temperature and the cooling rates. The effects of volume fraction and aspect ratio of Sn dendrites on the anisotropic steady-state creep rate of single crystal SAC specimen are examined. The objective of the study is to provide insights into the role that solder microstructural heterogeneity will play on package reliability in heterogeneous integration.

Topics: Solders
Commentary by Dr. Valentin Fuster
2017;():V001T01A010. doi:10.1115/IPACK2017-74266.

The most well-known and widely observed microstructural changes during aging are the coarsening of Ag3Sn and Cu6Sn5 intermetallic compounds (IMCs) present in the eutectic regions between β-Sn dendrites. In this investigation, Scanning Electron Microscopy (SEM) has been utilized to examine aging induced coarsening of IMCs occurring within lead free solders. Unlike many prior studies, fixed regions in the solder joint cross-sections were monitored throughout the aging process, rather than examining different samples and/or different regions after the various aging exposures. Sn-3.0Ag-0.5Cu (SAC305) lead free solder samples were formed with reflowed (RF) and water quenched (WQ) cooling profiles and resulting initial microstructures, and then polished microscopy cross-sections were prepared. Nanoindentation marks were added to the cross-sections at certain locations to facilitate locating the fixed regions of interest in subsequent microscopy observations. After preparation, the samples were then aged at T = 125 °C, and the microstructures were observed and recorded in the selected regions after various aging exposures using SEM. In addition, the coarsening of IMCs during aging has been quantitatively analyzed. Particularly, the aging induced changes in number of IMCs, total area of all IMCs, average particle area, and average particle diameter have been quantified for fixed regions in the samples.

Commentary by Dr. Valentin Fuster

Heterogeneous Integration: Micro-Systems With Diverse Functionality: Fracture, Fatigue, and Thermomechanical Reliability of Devices and Packages

2017;():V001T01A011. doi:10.1115/IPACK2017-74017.

In this study, the moisture induced delamination behavior of a plastic ball grid array package under the solder reflow process was investigated by the finite element analysis. The entire moisture history of the PBGA package was simulated for preconditioning at moisture sensitivity level 1 and the subsequent exposure to a soldering reflow. A fracture mechanics based analysis was used to investigate the combined effects of temperature, moisture and vapor pressure on the delamination behavior at the die/molding compound and die/die attach interfaces during solder reflow. For determining the total strain energy release rate and total stress intensity factor under a multiphysics environment like reflow, researchers commonly used the principle of superposition to combine the results from individual thermal stress, hygroscopic stress and vapor pressure induced stress analyses. In this study, a new method was proposed to obtain the total strain energy release rate and total stress intensity factor under the multi-physics environment in a single fracture analysis instead of three. Two different methods-virtual crack closure technique (VCCT) and crack tip opening displacement method (CTOD) were employed and compared in studying the variation of strain energy release rates during lead-free solder reflow. The relationship between the strain energy release rate and crack length was also obtained. The developments of the stress intensity factors due to individual effect of thermal mismatch, hygroscopic swelling and vapor pressure were calculated. The mode mixity was also determined under different temperatures and crack length.

Commentary by Dr. Valentin Fuster
2017;():V001T01A012. doi:10.1115/IPACK2017-74082.

This paper provides details of Knowledge Based Qualification (KBQ) methodology to calculate BGA component shock qualification requirements. The methodology is based on experimental, theoretical and computational approach used to generate a detailed knowledge of the use conditions and failure physics. Discussed are the steps taken to understand the end-user behavior and system design impact on dynamic load experienced by the component in the field. A special focus is placed on the understanding of the board deformation modes, their impact on BGA failures, and the physics-of-failure (PoF) metric that is not only accurate enough but also practical for everyday applications. Theoretical and computational modeling was used to perform the necessary “translations” from use condition to test conditions and from system level drop to test board component shock. These “translations” enabled by the PoF metric, directly lead to the determination of BGA shock qualification requirements.

Commentary by Dr. Valentin Fuster
2017;():V001T01A013. doi:10.1115/IPACK2017-74097.

To solve the low-k delamination in chip assembly for high-end servers, our hypothesis is proposed that the low-k stress is determined by the bending moment and the stress relaxation of a joint. In our hypothesis, the low-k stress decreases as the joint height (SnAg bump height) becomes shorter, such as below 80μm, in 150μm-pitch joints. Our hypothesis is supported by simulation, in which the low-k stress is investigated as a function of the joint height, the joint material and also the joint width (the joint pitch). Finally, experiments are performed to evaluate the low-k delamination as a function of the joint height and our hypothesis is also supported by experiments.

Commentary by Dr. Valentin Fuster
2017;():V001T01A014. doi:10.1115/IPACK2017-74099.

In this study, dynamic three points bending test by split Hopkinson pressure bar method and numerical simulations which was based on finite element method (FEM) were performed to estimate stress-based design standard for 3216 type of multilayer ceramic capacitors (MLCCs). Tool for creating the standard was suggested and linear dependence with loading rate was shown in the standard.

Commentary by Dr. Valentin Fuster
2017;():V001T01A015. doi:10.1115/IPACK2017-74177.

Recently, due to the increasing heat density of printed circuit boards (PCBs), thermal fatigue damage in the joints has exerted a more significant influence on the reliability of electronic components. Accordingly, the development of a new nondestructive inspection technology is strongly desired by related industries. The authors have applied a synchrotron radiation X-ray micro-tomography system to the nondestructive observation of micro-cracks. However, the reconstruction of CT images is difficult for planar objects such as PCB substrates, due to insufficient X-ray transmission in the direction parallel to the substrates. In order to solve this problem, a synchrotron radiation laminography system was developed to relax size restrictions on the observation samples, and was applied to the three-dimensional nondestructive evaluation of several kinds of solder joints, which were loaded under accelerated thermal cyclic conditions via thermal shock tests. Moreover, the thermal fatigue crack propagation process that occurs under actual PCB energization loading conditions will differ from that under the usual acceleration test conditions. In this work, the possibility of in-situ monitoring of the thermal fatigue crack propagation process using the laminography system was investigated at die-attached joints subjected to cyclic energization loading, which is close to the actual usage conditions of PCBs. The optical system developed for use in the laminography system was constructed to provide a rotation stage with a tilt from the horizontally incident X-ray beam, and to obtain X-ray projection images via a beam monitor. In this manner, the X-ray beam is sufficiently transmitted through the planar specimen in all projections. The observed specimens included several die-attached joints, in which 3 mm square ceramic dies had been mounted on a 40 mm square FR-4 substrate using Sn-3.0wt%Ag-0.5wt%Cu solder. Consequently, the laminography system was successfully applied to the in-situ monitoring of thermal fatigue cracks that appeared in the solder layer under cyclic energization. This was possible because the laminography images obtained in the energization state have a quality that is equivalent to those obtained in a non-energized state, provided that the temperature distribution of the specimen is stable. In addition, the fatigue crack propagation process can be quantitatively evaluated by measuring the crack surface area and calculating the average crack propagation rate. However, in some cases, the appearance of thermal fatigue cracks was not observed in a solder layer that had been loaded by the accelerated thermal cycle test. This result strongly suggests that delamination occurred at the interface, which indicates that the corresponding fracture mode was significantly influenced by the type of thermal loading.

Commentary by Dr. Valentin Fuster
2017;():V001T01A016. doi:10.1115/IPACK2017-74201.

In this paper, the effect of pretest isothermal aging and in-test aging on the fatigue behavior of Sn3.0Ag0.5Cu alloy are examined using the microstructurally adaptive creep model (MACM) and the maximum entropy fracture model (MEFM). Compared to traditional constitutive models, the MACM considers the effect of thermal history. Two microstructural parameters, the average Ag3Sn particle size and the average primary-Sn cell size, are identified as critical to capturing the aging behavior of SnAgCu alloys and are incorporated into a modified Dorn creep form. The MEFM is next utilized to characterize the damage accumulation rate in the Sn3.0Ag0.5Cu solder alloy. The MEFM uses a single damage accumulation parameter, which connects the accumulated damage to the accumulated in-elastic dissipation. This parameter is independent of sample geometry, test temperature and strain rate. The concepts of static aging and dynamic aging are utilized to describe pretest aging and in-test aging. In 25° C tests, with longer static aging, a faster fatigue damage accumulation results. Through the relationship between the damage accumulation rate and the average primary-Sn cell size, the influence of microstructural evolution introduced by static aging on fatigue behavior is confirmed. In 100° C tests, the dynamic aging causes further rapid damage accumulation relative to the 25° C tests.

Topics: Fatigue , Alloys , Solders
Commentary by Dr. Valentin Fuster
2017;():V001T01A017. doi:10.1115/IPACK2017-74233.

Current trends in the automotive industry point to increasing role of electronics for vehicle control, safety, efficiency and entertainment. Examples include lane-departure warning systems, collision avoidance systems, vehicle stability systems, and drive assist systems. Many of the automotive electronics systems are located under the hood of the vehicle mounted directly on engine or on transmission with sustained exposure to temperatures greater than 150°C in conjunction with vibration. Solder joint fatigue is a dominant failure modes under high-temperature vibration. Industry migration to lead-free solders has resulted in a proliferation of a wide variety of solder alloy compositions many of which are based on formulation of Sn, Ag and Cu. While it is well known that solder interconnects, accrue damage much faster when vibrated at elevated temperatures, the models for assessment of life under simultaneous temperature and vibration are scarce. State-of-art reliability models for solder joints focus on single stresses of vibration or thermal cycling. There is need for models for evaluating the survivability of leadfree solder assemblies to ensure 10-years, 100,000 miles life in automotive environments. In this paper, a new model has been proposed for life prediction of electronics under simultaneous temperature-vibration.

Commentary by Dr. Valentin Fuster
2017;():V001T01A018. doi:10.1115/IPACK2017-74249.

Solder interconnects in electronic assemblies are susceptible to failures due to environmental high strain rate impact and cyclic stresses. To mitigate the failures, adhesive bonds can be added after the solder assembly process to provide additional mechanical support. For ball grid array (BGA) packages, the adhesive is normally applied to the corners of the package and referred to as corner staking. In addition to corner staking, underfill is also a strategy used to mitigate the stresses on the solder joints. While components with underfill has been widely studied, the study of the impact of corner staking on the reliability of packages remains limited. This paper presents a study of corner-staked BGA packages with tin-3.0 silver-0.5 copper (SAC305) solder subjected to temperature cycling. Experimental temperature cycling is conducted to examine impact of the selected corner staking material on the fatigue life of BGAs. Further, finite element analysis is conducted to understand the influence of material properties of staking material on the fatigue life of BGAs. The result of the study indicates that the presence of corner staking, with selected material properties, reduces the damage on the solder joints under thermal cycling, and thus increases its fatigue life by about 80%. This paper may serve as a guidance for staking material selection to improve the fatigue life of solder joints of BGAs under thermal cycling.

Commentary by Dr. Valentin Fuster
2017;():V001T01A019. doi:10.1115/IPACK2017-74278.

Most of the electronic devices manufactured are used in daily life and with the miniaturization process of these devices, in the day to day life there is a risk of drop impact failure. It has been important to analyze and ensure the reliability of any electronic devices under every type of loading. Drop impact is not only loading that can affect reliability, but the simultaneous thermal load, moisture, convection is also acting. Smaller devices like cell phones, laptops, tablets are more prone to accidental impact loads which create board interconnects failure by frequent drop occurrence. Therefore, a multi-dimensional approach is taking place in research to study product reliability. In this paper, comprehensive study of drop and shock test is done on Quad Flat No-lead (QFN) package board of two different thickness. The computation setup is done with thermal analysis by providing power to die of the package which creates non-uniform temperature distribution during the drop testing analysis. This way drop test is coupled with a thermal load which is more realistic analysis. Our study depends on young’s modulus, density, CTE, thermal conductivity, specific heat and Poisson’s ratio of the material. Therefore, Experimental work includes material properties characterization of two boards to get temperature dependent Coefficient of thermal expansion, poison’s ratio and young’s modulus values using Thermal mechanical analyzer (TMA), the Dynamic mechanical analyzer (DMA) and Universal testing machine. Finite element analysis (FEA) method is used for computational analysis. Effect of impact loading for two boards has been done to investigate board and solder joint reliability due thickness and layer stack-ups in PCBs in environmental condition and at elevated temperature. For computational analysis, the assembly is subjected to the drop test per JEDEC standards. [12] The main purpose of this work is to study the impact of drop test with the powered package and how the reliability of any assembly changes with changing the stiffness of printed circuit board. The comparison of the boards has been made to understand the effect of PCB layer stack-ups, thickness, and temperature effect on the reliability of solder interconnects by considering the stress-strain generation that is induced in the PCBs during the drop test.

Commentary by Dr. Valentin Fuster
2017;():V001T01A020. doi:10.1115/IPACK2017-74279.

The reliability assessment of package assembly is important to predict the performance of any microelectronic devices. Formation of fatigue cracks at the interface between the solder joint and component is the common failure occur in widely used microelectronic devices. Lead-free solders and advanced silicon process nodes with ultra-low-k (ULK) dielectrics flip chip package are used and are facing significant reliability challenges. The ultra-low-k materials improve performance by reducing parasitic capacitance and crosstalk between adjacent metal lines. [2] With low modulus, lower fracture toughness, higher coefficient of thermal expansion (CTE) and poorer adhesion of ultra-low-k material, when it is compared to the common dielectric materials, it becomes a major concern to analyze thermomechanical failures. From our past study, it has been concluded that solder joint reliability (SJR) of the small package depends on the copper content in the printed circuit boards (PCB). Also, the wire bond large PBGA packages are a cost-effective package with a substantial number of solder balls. The substrate and PCB have its impact on the solder ball, the mismatch in CTE of different components cause solder failure. In this paper, critical attention has been given to the copper content present in the PCB of different thicknesses and how PCB thickness is related to SJR. The structure of package plays a vital role in deciding reliability of package, as the different structure can shift stress point or distribute stresses to one or more components. The substrate or PCB stack-up or composition can strongly affect the package life. Many parameters need to be studied and package to substrate ratio is one of its which is discussed in this work. Material characterization of PCB with different thickness has been done. Thermal Mechanical Analyzer (TMA) is leveraged to measure temperature-dependent CTE, Dynamic Mechanical Analyzer (DMA) and Universal testing machine are used for measuring Elastic modulus and Poisson’s ratio. Further, a package assembly for the PCB of different thickness has been a model using ANSYS Workbench 18.0.

Commentary by Dr. Valentin Fuster

Heterogeneous Integration: Micro-Systems With Diverse Functionality: Microelectronics and Optoelectronic Systems Integration

2017;():V001T01A021. doi:10.1115/IPACK2017-74195.

In this study, we proposed a bell shape phosphor layer geometry and the corresponding dual-step phosphor coating method for enhancing the angular color uniformity (ACU) of phosphor-converted white light-emitting diodes (pcLEDs). Numerical simulation based on Volume of Fluid (VOF) model was applied to predict phosphor geometries. Based on the simulated results, experiments were conducted to realize the phosphor geometries. The simulated results show that the VOF model can predict the phosphor geometries with an acceptable geometric deviation within 5%. The experimental results show that compared with the spherical cap phosphor layer geometry, the bell shape geometry can achieve better ACU performance, an optimal bell phosphor layer geometry with equal coating volume above and around the LED chip was achieved, for the corrected color temperature (CCT) of 4000 K, the angular CCT deviation of the optimal geometry is 62 K, while it is 382 K for the spherical cap geometry.

Commentary by Dr. Valentin Fuster
2017;():V001T01A022. doi:10.1115/IPACK2017-74252.

MEMS microphones are extensively used in many applications that require reliability, small size, and high sound quality. For harsh environment reliability data MEMS microphones need to be monitored under conditions mimicking their areas of applications. MEMS microphones have an opening/sound port in order to interact with the environment, therefore cannot be sealed completely since the sensing mechanism requires interaction between sound waves and the sensing element. Little to no information exists on reliability data for MEMS microphones under low/high temperature operating life and temperature humidity bias condition. Our work is primarily focused on providing harsh environmental reliability data which can be useful to MEMS designers and engineers. In this paper the test vehicles with MEMS Microphones have been tested under three different harsh environmental conditions: high temperature operating life (HTOL) at 125°C at 3.3V, low temperature storage (LTS) at −35°C and temperature humidity 85°C/85%RH at 3.3V. The main motive of this study is to document the incremental shift and degradation in output parameters namely distortion, frequency response, power supply rejection capability of IC, frequency vs pressure characteristics and analog output voltage of the MEMS microphone. The survivability of MEMS microphone, ADMP401, has been demonstrated as a function of change in the output parameters. Failure analysis has been conducted on the microphone samples to study failure modes and sites using analytical methods such as SEM, EDS and X-ray.

Commentary by Dr. Valentin Fuster

Heterogeneous Integration: Micro-Systems With Diverse Functionality: Thermal Management for Heterogeneous Integration

2017;():V001T01A023. doi:10.1115/IPACK2017-74080.

High heat flux from electronic devices remains a continuing challenge for cooling of electronics hardware in radar antenna applications pertaining to the defense industry. Cooling methods for such applications have varied from conduction cooling approaches for the cooling of circuit card assemblies, to advanced convection cooling using two phase flow (with pumped refrigerant) for the high heat flux devices used in transmit / receive modules. It is found that the limiting parameter in such applications is usually the heat flux from the electronic device. This paper provides an overview of the cooling techniques used for defense electronics, as well as current modeling tools and analytical methods used for thermal design during the product development phase. The role of thermal interface materials used in the material stack up for the thermal design solutions will also be touched upon. Additionally, the importance of using experimental techniques to characterize the heat transfer coefficient for the pumped refrigerant two phase flow will be discussed.

Commentary by Dr. Valentin Fuster
2017;():V001T01A024. doi:10.1115/IPACK2017-74107.

As technological advances lead to miniaturization of high power electronics, the concentration of heat generating components per area increases to the point of requiring innovative, integrated cooling solutions to maintain operational temperatures. Traditional coolant pumps have many moving parts, making them susceptible to mechanical failure and requiring periodic maintenance. Such devices are too complex to be miniaturized and embedded in small scale systems. Electrohydrodynamic (EHD) conduction pumps offer an alternative way of generating fluid flow in small scales for use in modern thermal control systems for high power electronics, both for terrestrial and aerospace applications. In EHD conduction, the interaction between an applied electrical field and the dissociation of electrolyte species in a dielectric fluid generates an accumulation of space charge near the electrodes, known as heterocharge layers. These layers apply electric body forces in the fluid, resulting in a flow in the desired direction based on the pump characteristics. EHD conduction pumps work with dielectric fluids and have simple, flexible designs with no moving parts. These pumps have very low power consumption, operate reliably for longer periods than mechanical pumps, and have the ability to operate in microgravity. EHD conduction pumps have been previously proven effective for heat transfer enhancement in multiple size scales, but were only studied in a flush ring or flush flat electrode configurations at the micro-scale. This study provides the pressure and flow rate generation performance characterization for a micro-scale pump with perforated electrodes, designed to be manufactured and assembled using innovative techniques, and incorporated into an evaporator embedded in an electronic cooling system. The performance of the pump is numerically simulated based on the fully coupled equations of the EHD conduction model, showcasing the distinctive heterocharge layer structure and subsequent force generation unique to this innovative design.

Commentary by Dr. Valentin Fuster
2017;():V001T01A025. doi:10.1115/IPACK2017-74137.

Thermal-aware techniques for 3D ICs have shown that high temperatures dramatically reduce the lifetime and the reliability of the 3D ICs with utilizing the third dimension. Hence, thermal management has been very crucial for the further improvement of the 3D IC architecture. There has been some thermal management strategies suggested at the micro/nano scale to alleviate the nonlocal heat dissipation; however, many solution methods such as liquid cooling have challenges and create many problems. In this paper, we propose nanoparticle based interfacial cooling to improve the thermal transport due to surface phonon polariton coupling and to reduce the thermal resistance between the interfaces. We demonstrate the efficiency of the heat dissipation from the proposed structure for 3D ICs.

Commentary by Dr. Valentin Fuster
2017;():V001T01A026. doi:10.1115/IPACK2017-74179.

The study investigated how the material roughness of a tablet computer surface can affect thermal sensation and comfort of users fingers and palms at different surface temperatures. Three levels of pattern spacing were tested, and it was shown that rough material surface provided higher thermal comfort comparing to a smooth surface. In addition, the surface temperature of the material also moderates participants′ physical sensation of the roughness of the materials. The results of the study have shown evidences of the potentials to use materials with spatial patterns to improve thermal comfort while dissipating heat from electronic devices.

Commentary by Dr. Valentin Fuster
2017;():V001T01A027. doi:10.1115/IPACK2017-74196.

Phase Change Materials (PCMs) have been widely investigated as a cooling solution due to their significant latent heat capacity. However, the current PCMs generally suffer a low thermal conductivity, thus hindering the application of PCMs. Composite Phase Change Materials (CPCMs) filling with high thermal conductivity materials have been proposed to solve this issue. Nevertheless, the latent heat of the CPCMs decreases with the mass fraction of fillings, thus leading to a lower allowable working time under safe operating temperature. Therefore, an optimal filling mass fraction of CPCMs is in urgent needed to improve the application of CPCMs. In this study, we developed a one-dimensional conduction heat transfer model of CPCMs to predict the optimal filling mass fraction of CPCMs to realize the maximum allowable working time. The filling mass fraction was introduced into the model and the relationship between the thermal conductivity and latent heat was built. We adopted paraffin as the matrix material and Expanded Graphite (EG) as the thermal conductivity enhancer. The allowable working time of the CPCMs as the function of filling mass fraction was obtained. Based on the principle of the maximum allowable working time, the optimal filling mass fraction was calculated. Comparative experiments were also conducted to validate the accuracy of the prediction model. The parameters which affect the maximum allowable working temperature were also investigated, including input heat flux, safe temperature, and height of CPCMs. The results show that a higher heat flux and height requires a larger filling mass fraction, and it’s opposite for the safe temperature.

Commentary by Dr. Valentin Fuster
2017;():V001T01A028. doi:10.1115/IPACK2017-74224.

Significant thermal gradients and hotspots is a major safety and operational issue in microprocessors, hence accurate real-time monitoring hot spots is a critical need. This thermal monitoring is typically performed using temperature sensors embedded in the chip or processor board. The location of the temperature sensors is primarily determined by the sensor space claim rather than the ideal location for thermal management. This manuscript presents an optimization methodology to determine the most beneficial locations for the temperature sensors inside of the microprocessors, based input from high resolution surface infrared thermography combined with inverse heat transfer solvers to predict hot spot locations. Specifically, the infrared image is used to obtain the temperature map over the processor surface, and subsequently delivers the input to a 3D inverse heat conduction methodology, used to determine the temperature field within the processor. In this paper, simulated thermal maps are utilized to assess the accuracy of the method. The inverse methodology is based in a function specification method combined with a sequential regularization in order to increase accuracy in the results. Together with a number of sensors, the temperature field within the processor is then used to determine the optimal location of the temperature sensors using a genetic algorithm optimization combined with a Kriging interpolation. This combination of methodologies was validated against the Finite Element Analysis of a chip incorporating heaters and temperature sensors. An uncertainty analysis of the inverse methodology and the Kriging interpolation was performed separately to assess the reliability of the procedure.

Commentary by Dr. Valentin Fuster

Servers of the Future: Data Centers and Energy Efficient HPC Concepts

2017;():V001T02A001. doi:10.1115/IPACK2017-74020.

Gravity-driven two-phase liquid cooling systems using flow boiling within micro-scale evaporators are becoming a game-changing solution for electronics cooling. The optimization of the system’s filling ratio can however become a challenging problem for a system operating over a wide range of cooling capacities and temperature ranges. The benefits of a liquid accumulator to overcome this difficulty are evaluated in the present paper.

An experimental thermosyphon cooling system was built to cool multiple electronic components up to a power dissipation of 1800 W. A double-ended cylinder with a volume of 150 cm3 is evaluated as the liquid accumulator for two different system volumes (associated to two different condensers).

Results demonstrated that the liquid accumulator provided robust thermal performance as a function of filling ratio for the entire range of heat loads tested. In addition, the present liquid accumulator was more effective for a small volume system, 599 cm3, than for a large volume system, 1169 cm3, in which the relative size of the liquid accumulator increased from 12.8 % to 25% of the total system’s volume.

Commentary by Dr. Valentin Fuster
2017;():V001T02A002. doi:10.1115/IPACK2017-74028.

Modern day data centers are operated at high power for increased power density, maintenance, and cooling which covers almost 2 percent (70 billion kilowatt-hours) of the total energy consumption in the US. IT components and cooling system occupy the major portion of this energy consumption. Although data centers are designed to perform efficiently, cooling the high-density components is still a challenge. So, alternative methods to improve the cooling efficiency has become the drive to reduce the cooling cost. As liquid cooling is more efficient for high specific heat capacity, density, and thermal conductivity, hybrid cooling can offer the advantage of liquid cooling of high heat generating components in the traditional air-cooled servers. In this experiment, a 1U server is equipped with cold plate to cool the CPUs while the rest of the components are cooled by fans. In this study, predictive fan and pump failure analysis are performed which also helps to explore the options for redundancy and to reduce the cooling cost by improving cooling efficiency. Redundancy requires the knowledge of planned and unplanned system failures. As the main heat generating components are cooled by liquid, warm water cooling can be employed to observe the effects of raised inlet conditions in a hybrid cooled server with failure scenarios. The ASHRAE guidance class W4 for liquid cooling is chosen for our experiment to operate in a range from 25°C – 45°C. The experiments are conducted separately for the pump and fan failure scenarios. Computational load of idle, 10%, 30%, 50%, 70% and 98% are applied while powering only one pump and the miniature dry cooler fans are controlled externally to maintain constant inlet temperature of the coolant. As the rest of components such as DIMMs & PCH are cooled by air, maximum utilization for memory is applied while reducing the number fans in each case for fan failure scenario. The components temperatures and power consumption are recorded in each case for performance analysis.

Topics: Cooling , Failure , Water
Commentary by Dr. Valentin Fuster
2017;():V001T02A003. doi:10.1115/IPACK2017-74030.

Nowadays, datacenters heat density dissipation follows an exponential increasing trend that is reaching the heat removal limits of the traditional air-cooling technology. Two-phase cooling implemented within a gravity-driven system represents a scalable and viable long-term solution for datacenter cooling in order to increase the heat density dissipation with larger energy efficiency and lower acoustic noise. The present article builds upon the 4-part set of papers presented at ITHERM 2016 for a 15-cm height thermosyphon to cool a contemporary datacenter cabinet, providing new test data over a wider range of heat fluxes and new validations of the thermal-hydrodynamics of our thermosyphon simulation code.

The thermosyphon consists of a microchannel evaporator connected via a riser and a downcomer to a liquid-cooled condenser for the cooling of a pseudo-chip to emulate an actual server. Test results demonstrated good thermal performance coupled with uniform flow distribution for the new larger range of operating test conditions. At the maximum imposed heat load of 158 W (corresponding to a heat flux of 70 W cm−2) with a water inlet coolant at 20 °C, water mass flow rate of 12 kg h−1 and thermosyphon filling ratio of 78%, the pseudo mean chip temperature was found to be 58 °C and is well below the normal thermal limits in datacenter cooling.

Finally, the in-house LTCM’s thermosyphon simulation code was validated against an expanded experimental database of about 262 data points, demonstrating very good agreement; in fact, the pseudo mean chip temperature was predicted with an error band of about 1 K.

Commentary by Dr. Valentin Fuster
2017;():V001T02A004. doi:10.1115/IPACK2017-74033.

Data centers concern not just energy usage, but also other important overall considerations such as the actual computational work, the energy efficiency and the performance of servers. The server, as one of the key ingredients of a data center, plays an increasingly crucial role in contributing to the overall energy use, especially in cases where the efficiency of the infrastructure has been optimized. Baidu has been exploring the sweet zone between power and performance in efficient rack server design and deployment for their self-built data center energy efficiency optimization from all the aspects. Recent deployment of rack server with distributed backup battery (Li-ion) subsystem (BBS) is one typical example to demonstrate their advanced rack server design for energy efficiency. Compared with lead acid battery based traditional UPS in data center, distributed BBS design in Baidu rack server has an advantage in lower power loss, data center power delivery and topology simplification, data center real estate saving, scalable deployment on demand without overprovision and so on, which overall contributes to a total cost ownership (TCO) reduction on both cap-ex (i.e., power infrastructure investment) and op-ex (i.e., electricity bill).

This paper introduces overall architecture and design of Baidu rack server with distributed BBS. Furthermore details energy efficiency design methodology of power peak draw trimming based on workload power characterization; Also the related lab data collection, experiments result, ongoing work and future plan are summarized in the end. This paper also recaps TCO saving points benefiting from distributed BBS design into rack server system.

Topics: Design , Batteries
Commentary by Dr. Valentin Fuster
2017;():V001T02A005. doi:10.1115/IPACK2017-74055.

Continuously increasing demand for higher compute performance is pushing for improved advanced thermal solutions. In high performance computing (HPC) area, most of the end users deploy some sort of direct or indirect liquid cooling thermal solutions. But for the users who have air cooled data centers and air cooled thermal solutions are challenged to cool next generation higher Thermal Design Power (TDP) processors in the same platform form factor without changing environmental boundary conditions. This paper presents several different advanced air cooled technologies developed to cool high TDP processors in the same form factor and within the same boundary conditions of current generation processor. Comparison of thermal performance using different cooling technologies such as Liquid Assist Air Cooling (LAAC) and Loop Heat Pipe (LHP) are presented in this paper. A case study of Intel’s Knights Landing (KNL) processor is presented to show case the increase in compute performance due to different advanced air cooling technologies.

Commentary by Dr. Valentin Fuster
2017;():V001T02A006. doi:10.1115/IPACK2017-74108.

This paper presents an experimentally validated room-level computational fluid dynamics (CFD) model for raised-floor data center configurations employing active tiles. Active tiles are perforated floor tiles with integrated fans, which increase the local volume flowrate by redistributing the cold air supplied by the computer room air conditioning (CRAC) unit to the under-floor plenum. In a previous study [1], experiments were conducted to explore the potential of active tiles for economically and efficiently eliminating hot spots in data center. Our results indicated that active tiles, as the actuators closest to the racks, can significantly and quickly impact the local distribution of cooling resources. They could therefore be used in an appropriate control framework to rapidly mitigate hot spots, and maintain local conditions in an energy-efficient manner.

The numerical model of the data center room operates in an under-floor supply and ceiling return cooling configuration and consists of one cold aisle with 12 racks arranged on both sides and three CRAC units sited around the periphery of the room. The commercial computational fluid dynamics (CFD) software package Future Facilities 6SigmaDCX [2], which is specifically designed for data center simulation, is used to develop the model. First, a baseline model using only passive tiles was developed and experimental data were used to verify and calibrate plenum leakage for the room. Then a CFD model incorporating active tiles was developed for two configurations: (a) a single active tile and 9 passive tiles in the cold aisle; and (b) an aisle populated with 10 (i.e., all) active tiles. The active tiles are modeled as a combination of a grill, fan elements and flow blockages to closely mimic the actual active tile used in the experimental studies. The fan curve for the active tile fans is included in the model to account for changes in flow rate through the tiles in response to changes in plenum pressure.

The model with active tiles is validated by comparing the flow rate through the floor tiles, relative plenum pressure and rack inlet temperatures for selected racks with the experimental measurements. The predictions from the CFD model are found to be in good agreement with the experimental data, with an average discrepancy between the measured and computed values for total flow rate and rack inlet temperature less than 4% and 1.7 °C, respectively. These validated models were then used to simulate steady state and transient scenarios following cooling failure.

This physics-based and experimentally validated room-level model can be used to predict temperature and flow distributions in a data center using active tiles. These predictions can then be used to identify the optimal number and locations of active tiles to mitigate hot spots, without adversely affecting other parts of the data center.

Commentary by Dr. Valentin Fuster
2017;():V001T02A007. doi:10.1115/IPACK2017-74148.

The constant increase in data center computational and processing requirements has led to increases in the IT equipment power demand and cooling challenges of high-density (HD) data centers. As a solution to this, the hybrid and liquid systems are widely used as part of HD data centers thermal management solutions.

This study presents an experimental based investigation and analysis of the transient thermal performance of a stand-alone server cabinet. The total heat load of the cabinet is controllable remotely and a rear door heat exchanger is attached with controllable water flow rate. The cooling performances of two different failure scenarios are investigated. One is in the water chiller and another is in the water pump for the Rear Door Heat eXchanger (RDHX). In addition, the study reports the impact of each scenario on the IT equipment thermal response and on the cabinet outlet temperature using a mobile temperature and velocity mesh (MTVM) experimental tool. Furthermore, this study also addresses and characterizes the heat exchanger cooling performance during both scenarios.

Commentary by Dr. Valentin Fuster
2017;():V001T02A008. doi:10.1115/IPACK2017-74174.

In this paper, the impact of direct liquid cooling (DLC) system failure on the IT equipment is studied experimentally. The main factors that are anticipated to affect the IT equipment response during failure are the CPU utilization, coolant set point temperature (SPT) and the server type. These factors are varied experimentally and the IT equipment response is studied in terms of chip temperature and power, CPU utilization and total server power. It was found that failure of the cooling system is hazardous and can lead to data center shutdown in less than a minute. Additionally, the CPU frequency throttling mechanism was found to be vital to understand the change in chip temperature, power, and utilization. Other mechanisms associated with high temperatures were also observed such as the leakage power and the fans speed change. Finally, possible remedies are proposed to reduce the probability and the consequences of the cooling system failure.

Commentary by Dr. Valentin Fuster
2017;():V001T02A009. doi:10.1115/IPACK2017-74181.

Silicon photonics has emerged as a scalable technology platform for future optotelectronic communication systems. However, the current use of SiO2-based silicon-on-insulator (SOI) substrates presents a thermal challenge to integrated active photonic components such as lasers and semiconductor optical amplifiers due to the poor thermal properties of the buried SiO2 optical cladding layer beneath these devices. To improve the thermal performance of these devices, it has been suggested that SiO2 be replaced with aluminum nitride (AlN); a dielectric with suitable optical properties to function as an effective optical cladding that, in its crystalline state, demonstrates a high thermal conductivity (∼100× larger than SiO2 in current SOI substrates).

On the other hand, the tuning efficiencies of thermally-controlled optical resonators and phase adjusters, crucial components for widely tunable lasers and modulators, are directly proportional to the thermal resistance of these devices. Therefore, the low thermal conductivity buried SiO2 layer in the SOI substrate is beneficial. Moreover, to further improve the thermal performance of these devices air trenches have been used to further thermally isolate these devices, resulting in up to ∼10× increase in tuning efficiency.

Here, we model the impact of changing the buried insulator on a SOI substrate from SiO2 to high quality AlN on the thermal performance of a MRR. We map out the thermal performance of the MRR over a wide range of under-etch levels using a thermo-electrical model that incorporates a pseudo-etching approach. The pseudo-etching model is based on the diffusion equation and distinguishes the regions where substrate material is removed during device fabrication. The simulations reveal the extent to which air trenches defined by a simple etch pattern around the MRR device can increase the thermal resistance of the device.

We find a critical under-etch below which no benefit is found in terms of the MRR tuning efficiency. Above this critical under-etch, the tuning efficiency increases exponentially. For the SiO2-based MRR, the thermal resistance increases by ∼7.7× between the un-etched state up to the most extreme etch state. In the unetched state, the thermal resistance of the AlN-based MRR is only ∼4% of the SiO2-based MRR. At the extreme level of under-etch, the thermal resistance of the AlN-based MRR is still only ∼60% of the un-etched SiO2-based MRR. Our results suggest the need for a more complex MRR thermal isolation strategy to significantly improve tuning efficiencies if an AlN-based SOI substrate is used.

Commentary by Dr. Valentin Fuster
2017;():V001T02A010. doi:10.1115/IPACK2017-74184.

Ridge-type hybrid III-V active waveguides on silicon-on-insulator (SOI) substrates demonstrate poor thermal performance due to several factors. One aspect of their typical design that leads to large thermal resistance is the use of polymer-based optical cladding around the waveguide. To address this issue, we have been exploring the use of deposited aluminium nitride (AlN) as an alternative optical cladding material. AlN is an excellent dielectric with optical properties making it suitable as a cladding around III-V waveguides. Crucially, this material can demonstrate thermal conductivities ∼100 times larger than current polymer cladding materials such as benzocyclobutene (BCB). Electro-thermo simulation results suggest that replacing BCB with AlN could reduce device thermal resistance by ∼2 times. However, our previous linear elastic mechanical modelling indicates that mismatched thermal expansion has the potential to cause mechanical tensile failure in the III-V waveguide when cooled from the processing temperature to room temperature if AlN is deposited in a neutral residual stress state.

Here, to facilitate the design of encapsulated reliable hybrid semiconductor lasers, we extend our finite element, electro-thermo-mechanical model to include a residual stress in the deposited AlN. Using the Christensen criterion to define the maximum allowable stress in the device, our simulations indicate that there is a window of residual compressive stress in the AlN where mechanical failure may be avoided. To assess the feasibility of accessing this region of compressive residual stress while maintaining suitable thermal properties in the deposited AlN, we measure the thermal conductivity of AlN thin films (∼1.6 μm thick) deposited on silicon using a time-domain thermo reflectance (TDTR) setup. Stress measurements demonstrate compressive residual stresses ranging from ∼0 to −0.5 GPa. The TDTR measurement results reveal a similar thermal conductivity of ∼155 Wm−1K−1 over the entire range of compressive residual stress. These results strengthen the promise of encapsulating III-V active waveguides with AlN that simultaneously satisfy both thermal and mechanical requirements.

Commentary by Dr. Valentin Fuster
2017;():V001T02A011. doi:10.1115/IPACK2017-74254.

Over the past few years, there has been an ever increasing rise in energy consumption by IT equipment in Data Centers. Thus, the need to minimize the environmental impact of Data Centers by optimizing energy consumption and material use is increasing. In 2011, the Open Compute Project was started which was aimed at sharing specifications and best practices with the community for highly energy efficient and economical data centers. The first Open Compute Server was the ‘ Freedom’ Server. It was a vanity free design and was completely custom designed using minimum number of components and was deployed in a data center in Prineville, Oregon. Within the first few months of operation, considerable amount of energy and cost savings were observed. Since then, progressive generations of Open Compute servers have been introduced. Initially, the servers used for compute purposes mainly had a 2 socket architecture. In 2015, the Yosemite Open Compute Server was introduced which was suited for higher compute capacity. Yosemite has a system on a chip architecture having four CPUs per sled providing a significant improvement in performance per watt over the previous generations. This study mainly focuses on air flow optimization in Yosemite platform to improve its overall cooling performance. Commercially available CFD tools have made it possible to do the thermal modeling of these servers and predict their efficiency. A detailed server model is generated using a CFD tool and its optimization has been done to improve the air flow characteristics in the server. Thermal model of the improved design is compared to the existing design to show the impact of air flow optimization on flow rates and flow speeds which in turn affects CPU die temperatures and cooling power consumption and thus, impacting the overall cooling performance of the Yosemite platform. Emphasis is given on effective utilization of fans in the server as compared to the original design and improving air flow characteristics inside the server via improved ducting.

Commentary by Dr. Valentin Fuster
2017;():V001T02A012. doi:10.1115/IPACK2017-74295.

With the rapid growth of data centers worldwide and the global shift towards energy sustainability, deploying new cooling technologies has an utmost importance. Conventional cooling systems such as chilled water system, usually have high capital costs and relatively low energy efficiency, leading to a high PUE and TCO values. Indirect evaporative cooling is a promising technology, which offers air cooling with high efficiency, hygiene air quality, and lower total cost. This paper details the design of a proof-of-concept data center with indirect evaporative cooling, which will be eventually deployed at megawatt-scale Baidu datacenters. BIN data analysis and CFD simulation are performed to optimize the physical design and operating conditions. CFD analysis of the data center room is established to optimize rack placement, air flow management, and cold aisle hot aisle configuration. A comprehensive TCO analysis is established, which shows a total savings of 9% using IDEC technology compared to chilled water system for cooling. In addition, TCO analysis indicates small to negligible effect of air supply temperature. Hence, air supply to the cold aisle is set to 27 °C to improve cooling performance. Finally, ROI sensitivity analysis is performed to measure the sensitivity of ROI on power usage effectiveness of the IDEC unit.

Commentary by Dr. Valentin Fuster
2017;():V001T02A013. doi:10.1115/IPACK2017-74337.

This paper presents experimental data of concurrent modulation of a multi-channel transmitter that uses carrier-injection ring modulators at 10Gb/s/channel that is optically driven by a quantum-dot comb laser with 50GHz channel spacing.

Topics: Lasers
Commentary by Dr. Valentin Fuster
2017;():V001T02A014. doi:10.1115/IPACK2017-74341.

With the growth of Internet-based services, data centers must deal with increasing data traffic. Load-balancing technologies can help data centers process data effectively and stably; however, the current load-balancing methods do not take into account the heat generated by servers. Excessive heat can increase the failure rate of IT devices and the energy consumption of air conditioning systems, both of which lead to higher data center maintenance costs. This paper aims to simultaneously increase the coefficient of performance (COP) of the data center’s air-conditioning equipment and decrease the semiconductor-based equipment failure rate. To do so — and, consequently, reduce the operation and maintenance costs — we propose a novel request distribution system based on server-temperature and evaluate the proposed system by creating a thermal model of a data center. As a result, it is suggested that using the proposed load-balancing method the semiconductor failure rate can be reduced by 32 % when compared with the common round-robin distribution method, and by 19 % when compared with a load-balancing method based on CPU utilization. Moreover, the COP of the air-conditioning equipment obtained with the proposed method is recognized to be higher than those obtained with either the round-robin or the CPU-utilization-based methods.

Topics: Temperature , Cycles
Commentary by Dr. Valentin Fuster

Servers of the Future: Modeling and Simulation

2017;():V001T02A015. doi:10.1115/IPACK2017-74016.

Data centers house a variety of compute, storage, network IT hardware where equipment reliability is of utmost importance. Heat generated by the IT equipment can substantially reduce its service life if Tjmax, maximum temperature that the microelectronic device tolerates to guarantee reliable operation, is exceeded. Hence, data center rooms are bound to maintain continuous conditioning of the cooling medium becoming large energy consumers.

The objective of this work is to introduce and evaluate a new end-of-aisle cooling design which consists of three cooling configurations. The key objectives of close-coupled cooling are to enable a controlled cooling of the IT equipment, flexible as well as modular design, and containment of hot air exhaust from the cold air. The thermal performance of the proposed solution is evaluated using CFD modeling. A computational model of a small size data center room has been developed. Larger axial fans are selected and placed at rack-level which constitute the rack-fan wall design. The model consists of 10 electronic racks each dissipating a heat load of 8kw. The room is modeled to be hot aisle containment i.e. the hot air exhaust exiting for each row is contained and directed within a specific volume. Each rack has passive IT with no server fans and the servers are cooled by means of rack fan wall. The cold aisle is separated with hot aisle by means of banks of heat exchangers placed on the either sides of the aisle containment. Based on the placement of rack fans, the design is divided to three sub designs — case 1: passive heat exchangers with rack fan walls; case 2: active heat exchangers (HXs coupled with fans) with rack fan walls; case 3: active heat exchangers (hxs coupled with fans) with no rack fans. The cooling performance is calculated based on the thermal and flow parameters obtained for all three configurations. The computational data obtained has shown that the case 1 is used only for lower system resistance IT. However, case 2 and Case 3 can handle denser IT systems. Case 3 is the design that can consume lower fan energy as well as handle denser IT systems. The paper also discusses the cooling behavior of each type of design.

Commentary by Dr. Valentin Fuster
2017;():V001T02A016. doi:10.1115/IPACK2017-74021.

The miniaturization of Control Units (CUs), consequently increasing power and reduced component size justifies a growing need for significantly improved Thermal Interface Material (TIM) which is a pivotal material for transferring heat from a die to a heat-spreader. However, it also has a crucial effect on the thermomechanical and dynamic behavior of the attached components. In this paper, the effect of frequency dependency of TIM on dynamic behavior of the attached capacitor is investigated analytically, numerically and experimentally. The results show that it is crucial to consider the frequency dependent material properties of TIM, for reliability assessment of the attached components under dynamic loading conditions.

Commentary by Dr. Valentin Fuster
2017;():V001T02A017. doi:10.1115/IPACK2017-74081.

In this work we present a knowledge-based qualification approach for solder joint reliability of Ball Grid Array (BGA) component used in server systems. Servers experience very few on-off power cycles during their lifetime. The primary source of BGA thermo-mechanical damage in these systems is, therefore, the temperature fluctuations during use. We employ measured server CPU die temperature during field usage and a novel physics-of-failure metric to define the requirements for qualification in temperature cycling accelerated tests. The result of this computational/empirical approach is compared against the result of the industry-standard based empirical acceleration model. The key conclusion of this work is that standard empirical acceleration models have difficulty accounting for small temperature fluctuations and lead to significant overestimation of the risks. On the other hand, the proposed computational/empirical approach provides a physically meaningful estimation of risk.

Topics: Temperature
Commentary by Dr. Valentin Fuster
2017;():V001T02A018. doi:10.1115/IPACK2017-74098.

In large-die (20mm and above) flip-chip packaging applications such as high-end processors, the organic substrates have been widely used. In most cases, they are double-sided multi-layer printed wiring boards. The substrates mainly consist of glass-reinforced rigid core, build-up film resin layers and copper trace patterns. During chip attaching process, the substrates are warped due mainly to the unbalance in copper loading ratio of the build-up layers between the front and the back of the core layer. A common practice for minimizing the warpage of a substrate is to balance its copper loading as much as possible at its design stage. However, the thickness of each build-up layer and trace pattern can shift from its designed value due to fluctuation in process conditions during manufacturing. Consequently, the substrate warpage becomes larger than the minimized value, since the copper loading is no longer balanced. One of the possible solutions for this challenge is to minimize the errors in manufacturing process. Another solution is to make the substrates more resilient to the manufacturing variations. The latter can be performed at the design stage. The substrates can be made resilient by minimizing the warpage deviation when the thickness of the build-up layer and trace pattern are varied.

In this paper, we have found that the warpage dispersion can be reduced by the build-up material properties which are the key components in balancing the front and back build-up layers. To study the effect of the build-up material properties, we performed dispersion analyses using the multilayered beam model. The analyses results showed a minimum in warpage dispersion when the coefficient of thermal expansion (CTE) of build-up materials is varied at a fixed Young’s modulus. They also show that the warpage dispersion decreases with decreasing Young’s modulus of build-up materials.

The analyses are also done by Monte Carlo simulation with finite element analyses (FEA) so that the analyses can be applied to more complex substrates made for actual packages. The results of Monte Carlo simulations were consistent with those of obtained by the multilayered beam model. The values in build-up material for minimizing the warpage dispersion are in realistic range. In summary, we showed that the organic substrates can be made resilient to manufacturing variations by choosing build-up materials with appropriate material properties which minimize the warpage dispersion.

Commentary by Dr. Valentin Fuster
2017;():V001T02A019. doi:10.1115/IPACK2017-74105.

The operation of today’s data centers increasingly relies on environmental data collection and analysis to operate the cooling infrastructure as efficiently as possible and to maintain the reliability of IT equipment. This in turn emphasizes the importance of the quality of the data collected and their relevance to the overall operation of the data center. This study presents an experimentally based analysis and comparison between two different approaches for environmental data collection; one using a discrete sensor network, and another using available data from installed IT equipment through their Intelligent Platform Management Interface (IPMI). The comparison considers the quality and relevance of the data collected and investigates their effect on key performance and operational metrics. The results have shown the large variation of server inlet temperatures provided by the IPMI interface. On the other hand, the discrete sensor measurements showed much more reliable results where the server inlet temperatures had minimal variation inside the cold aisle. These results highlight the potential difficulty in using IPMI inlet temperature data to evaluate the thermal environment inside the contained cold aisle.

The study also focuses on how industry common methods for cooling efficiency management and control can be affected by the data collection approach. Results have shown that using preheated IPMI inlet temperature data can lead to unnecessarily lower cooling set points, which in turn minimizes the potential cooling energy savings. It was shown in one case that using discrete sensor data for control provides 20% more energy savings than using IPMI inlet temperature data.

Topics: Data centers
Commentary by Dr. Valentin Fuster
2017;():V001T02A020. doi:10.1115/IPACK2017-74129.

Particulate thermal interface materials (TIMs) are commonly used to transport heat from chip to heat sink. While high thermal conductance is achieved by large volume loadings of highly conducting particles in a compliant matrix, small volume loadings of stiff particles will ensure reduced thermal stresses in the brittle silicon device. Developing numerical models to estimate effective thermal and mechanical properties of TIM systems would help optimize TIM performance with respect to these conflicting requirements. Classical models, often based on single particle solutions or regular arrangement of particles, are insufficient as real-life TIM systems contain a distriubtion of particles at high volume fractions, where classical models are invalid. In our earlier work, a computationally efficient random network model was developed to estimate the effective thermal conductivity of TIM systems [1,2]. This model is extended in this paper to estimate the effective elastic modulus of TIMs. Realistic microstructures are simulated and analyzed using the proposed method. Factors affecting the modulus (volume fraction and particle size distribution) are also studied.

Commentary by Dr. Valentin Fuster
2017;():V001T02A021. doi:10.1115/IPACK2017-74339.

In raised floor data centers, tiles with high open area ratio or complex understructure are used to fulfill the demand of today’s high-density computing. Using more open tiles reduces pressure drop across the raised floor with the potential advantages of increased airflow and lower noise. However, it introduces the disadvantage of increased non-uniformity of airflow distribution. In addition, there are various tile designs available on the market with different opening shapes or understructures. Furthermore, a physical separation of cold and hot aisles (containment) has been introduced to minimize the mixing of cold and hot air. In this study, three types of floor tiles with different open area, opening geometry, and understructure are considered. Experimentally validated detail models of tiles were implemented in CFD simulations to address the impact of tile design on the cooling of IT equipment in both open and enclosed aisle configurations. Also, impacts of under-cabinet leakage on the IT equipment inlet temperature in the provisioned and under-provisioned scenarios are studied. Finally, a predictive equation for the critical under-provisioning point that can lead to a no-flow condition in IT equipment with weaker airflow systems is presented.

Topics: Design , Tiles
Commentary by Dr. Valentin Fuster

Servers of the Future: Thermal Management and Advanced Heat Spreading Concepts for 2D, 2.5D, and 3D Architectures

2017;():V001T02A022. doi:10.1115/IPACK2017-74025.

The rapid growth of the global network infrastructure has resulted in a sharp increase in the number and size of data center facilities. Total data center power consumption now represents a significant fraction of global electricity production. To conserve natural resources, and to satisfy the cooling demands of compact, powerful electronics, thermal management strategies with high heat transfer coefficients must be employed. Two-phase liquid immersion cooling is one such strategy that has been gaining momentum in commercial cooling applications over recent years. The work discussed in this paper provides information on two different flow boiling investigations performed on vertically oriented surfaces in a small form factor server model. Two different types of surfaces — bare silicon, and silicon surfaces attached with microfinned heat sinks were tested in this study. Novec 649 dielectric fluid was used as the primary working fluid. The first investigation compares the thermal performance of parallel and impinging flow distribution systems, for different subcooling and flow rate conditions. The second investigation is on nucleation suppression in flow boiling for the parallel and impinging flow distribution systems. In this study, flow rates ranging from 0 ml/min to 1650 ml/min were tested and high-speed imaging was performed to capture the change in bubble characteristics. The resulting observations, including highest heat flux values supported without nucleation activity, are reported and discussed.

Commentary by Dr. Valentin Fuster
2017;():V001T02A023. doi:10.1115/IPACK2017-74119.

Pulsating heat pipe (PHP) is a two phase highly efficient heat transfer device, due to its simple and flexible construction; it can be manufactured for a variety of applications. PHP works on thermally induced self-sustaining oscillation of liquid plugs and vapor slugs, so it does not have any moving parts either. Ease of manufacturing, potential for high efficiency at different scales and the ability to handle large heat fluxes has the PHP a suitable candidate for microscale electronics cooling or power electronics cooling. However, this technology is still in developing phase and there is at present no comprehensive model which can be used to design a PHP for a specific application. There are many parameters which affect PHP operation and a thorough understanding of the relation between all the variables is first required. The present study is an attempt to investigate experimentally the effects of various parameters on PHP startup, based on startup temperature measurements under varying heat input and carefully controlled conditions. It has been observed that the oscillations in PHP start (startup) as soon as it reaches a minimum temperature corresponding to the minimum Etvos number required for vapor bubble rise.

Topics: Heat pipes
Commentary by Dr. Valentin Fuster
2017;():V001T02A024. doi:10.1115/IPACK2017-74158.

This work presents the design and characterization of a two-phase, embedded manifold-microchannel (MMC) system for cooling of high heat flux electronics. The study uses a thin-Film Evaporation and Enhanced fluid Delivery System (FEEDS) MMC cooler for high heat flux cooling of electronics. The work builds upon our group’s earlier work in this area with a particular focus on the use of an improved bonding structure and implementation of uniform heat flux heaters that collectively contribute to enhanced performance of the system. In many MMC systems targeted for high heat flux applications microchannels and manifolds are fabricated separately due to different dimensions and tolerances required for each. However, assembly of the system often leaves a gap between the channels and the manifold, thus causing the working fluid to leak through the top of the microfins leading to decreased cooler performance. The effect of this gap is parametrized and analyzed with ANSYS Fluent CFD simulations and discussed in this paper. The findings show that even a few microns wide gap can cause a noticeable degradation of the MMC system performance. Imperfect assembly and the deformation of a microchannel chip due to working fluid pressure can cause gaps, indicating the necessity of uniform and hermetic bonding between the manifold and the tips of the microfins. Furthermore, this work presents the need for better heater designs to enable uniform and high heat flux to the heat transfer surface. Serpentine heaters are often used to mimic electronics in a laboratory environment, but there is a lack of study on the performance characterization of the heaters themselves. In the current work, the performance of a conventional serpentine heater is characterized using ANSYS thermo-electric modeling software. The results show that conventional serpentine heaters are insufficient at providing uniform heat flux in applications where there is a lack of heat spreading-such as in the current embedded cooler — showing deviations ranging over 200 % of the nominal value. The deviations are caused by the many bends present in a serpentine pattern where current density concentrations vary significantly. Two alternate designs are proposed, and numerical simulations show that these new heater designs are capable of providing uniform heat flux, not deviating more than 20% from the nominal heat flux value. The conventional and newly proposed heaters are fabricated, tested, and analyzed with a working FEEDS system.

Commentary by Dr. Valentin Fuster
2017;():V001T02A025. doi:10.1115/IPACK2017-74287.

Two-phase cooling has become an increasingly attractive option for thermal management of high-heat flux electronics. Cooling channels embedded directly on the back of the heat source (chip) facilitate two-phase boiling/evaporation effectiveness, eliminating many thermal resistances generated by more traditional, remote chip-cooling approaches. Accordingly, manifold-microchannel flow paths in embedded cooling systems can allow very high heat fluxes with low junction temperatures. But, the effect of the feeding manifold design, channel geometry, and the associated shear, stagnation zones, and centripetal accelerations with varying heat flux and mass flux are not well understood. This study builds upon our previous work and elucidates effects of channel geometry, mass flux, and outlet quality on the boiling/evaporation flow regimes in a manifolded microgap channel.

Commentary by Dr. Valentin Fuster

Structural and Physical Health Monitoring: Mechanical Reliability Issues in Flexible and Printed Electronics

2017;():V001T03A001. doi:10.1115/IPACK2017-74178.

This paper describes a method for the synthesis of silica nanoparticles that can be later used for coating of quantum dots inside a microfluidic reactor. Here, a droplet-based system is used where two reagents were mixed inside the droplets to obtain silica. Particles in the size range of 25±2.7 nm were obtained with comparable size distribution to controlled batch-wise synthesis methods. This method is suitable to be used later to coat CdSe nanoparticles inside the microreactor.

Topics: Drops , Nanoparticles
Commentary by Dr. Valentin Fuster
2017;():V001T03A002. doi:10.1115/IPACK2017-74232.

Flexible electronics have a myriad of potential applications in fields such as healthcare, soldier situational awareness, soldier rehabilitation, sports performance, and textile manufacturing among other areas. The primary benefits that flexible electronics provide to both the producers and consumers are their light weight, low power consumption, efficiency, low cost of production, flexibility, and scalability. In comparison to rigid electronics, these systems would be subjected to a greater amount of mechanical and thermal stress in real-time due to their ability to be flexed, rolled, folded, and stretched. Environmental conditions such as bending, mechanical shock, water immersion, sweat, UV radiation, and temperature exposure could degrade the performance of these embedded electronic systems. At this time, there is a lack of suitable test standards and reliability data about flexible electronics manufacturing, assembly, and real-time use. In this paper, a fully flexible medical electronics system was built in full dimension to study the assembly and operation-related failure mechanisms of flexible and wearable electronics. The fabricated flexible electronics system measures pulse and muscle activity, and then transmits this data to a paired mobile device. The pulse rate was measured using an LED and a photo diode, while an electromyography (EMG) sensor was used to measure muscle activity. After collecting the data, the microcontroller sends it to a Bluetooth module, which can in turn transmit this information to a paired mobile device. Through experimentation with the fabricated flexible electronics device, unexpected degradation and quality issues were observed. In flexible PCBs, the space between the IC lead could not be isolated by the solder mask because of its large feature size and as a result, increases the risk of shortage between IC leads when subjected to mechanical stress. In addition, during the assembly process, high reflow temperature was found to subject a huge thermal stress on the connections between the solder pad and copper trace. Proper support of the solder pad should be designed to compensate the thermal stress during the reflow process, and prevent the copper joint on top of the board from being damaged. A set of guidelines for flexible medical electronics and an implementable reliability test standard can, therefore, be established for medical device manufacturers based on these reliability assessments.

Commentary by Dr. Valentin Fuster
2017;():V001T03A003. doi:10.1115/IPACK2017-74264.

Flexible electronics provide new design options not afforded by rigid electronics in a variety of applications including wearable electronics, robotics and automotive systems. However, the processes for the manufacturing of complex electronic assemblies using fine-pitch components are not as well developed as those for rigid electronics. The lack of structural rigidity of flexible printed circuit cards requires attention to assembly configuration for double-sided flexible assemblies. In addition, mechanisms are needed to compensate for the deformation and warpage of the flexible substrate and components during assembly. In this paper, the stresses in solder joints of double-sided flexible assemblies have been measured during thermal excursions using x-ray micro-computed tomography in conjunction with digital volume correlation. The method allows for non-invasive measurement and does not require cross-sectioning of the part for the purpose of deformation and strain measurement. In addition, the measurements are not limited to the joints in the line of sight. The three-dimensional measurements of deformation and strain have been visualized on the geometry of the solder joints in the package. Digital volume correlation (DVC) method has been used to find the displacements and strains in interconnects of operational electronics. The x-ray microscopic computed tomography (μCT) system has been used to generate the 16 bit digital volume data. The x-ray detector has ability to image the x-ray attenuation of x-rays through the object. Reliability testing of SAC 305 solder interconnects has been performed on double-sided flexible circuit board using x-ray μCT by heating the package to 100°C. The flexible circuit board used in this experiment is of BGA 256-144 combination, two packages, A-PBGA256-1.0mm-17mm and A-CABGA144-1.0mm-13mm.

A 3D printed fixture has also been used to support the flexible board and keep it flat while in the CT scan machine. The reference and deformed scans are then re-constructed 3D using Volume Graphics, and Digital Volume Correlation performed using MATLAB modules. Reliability of double-sided flexible printed circuit boards will be discussed and any crack, defects, or deformation in the solder interconnectivity which might occur while heating the package on flexible board is presented. The solder joint strains during thermal excursions are also compared between the flexible and rigid printed circuit assemblies.

Commentary by Dr. Valentin Fuster

Structural and Physical Health Monitoring: Novel Sensors and Packaging for Structural and Health Monitoring

2017;():V001T03A004. doi:10.1115/IPACK2017-74058.

This paper presents a failure mode detection methodology using a piezoresistive silicon based stress sensor. Data from experiment is used to validate algorithms developed for detection. Dedicated test vehicles are designed and fabricated, where the process parameters and materials are carefully selected to produce delamination between molding compound and PCB after fabrication. The test vehicles are then subjected to thermal cycling of −40°C to 125°C to grow the delamination area. After every 150 cycles, the samples are examined using Scanning Acoustic Microscopy (SAM), and the results are correlated with stress sensor signal. It is demonstrated that the propagation of the delamination area can be detected using the stress sensor. Collected data is also used to examine the applicability of statistical pattern recognition algorithms for detecting the failure. The algorithms considered in the study include Mahalanobis Distance (MD) and Singular Value Decomposition (SVD), which do not require a prior knowledge about failures and are just searching for deviation from norm in the data. The results from the analysis indicate that both techniques are suitable to stress sensor measurements, and thus are capable of detecting failure during reliability testing.

Commentary by Dr. Valentin Fuster
2017;():V001T03A005. doi:10.1115/IPACK2017-74150.

PARC, a Xerox Company, is developing a low-cost system of peel-and-stick wireless sensors that will enable widespread building environment sensor deployment with the potential to deliver up to 30% energy savings. The system is embodied by a set of RF hubs that provide power to automatically located sensor nodes, and relay data wirelessly to the building management system (BMS). The sensor nodes are flexible electronic labels powered by rectified RF energy transmitted by an RF hub and can contain multiple printed and conventional sensors. The system design overcomes limitations in wireless sensors related to power delivery, lifetime, and cost by eliminating batteries and photovoltaic devices. Sensor localization is performed automatically by the inclusion of a programmable multidirectional antenna array in the RF hub. Comparison of signal strengths while the RF beam is swept allows for sensor localization, reducing installation effort and enabling automatic recommissioning of sensors that have been relocated, overcoming a significant challenge in building operations. PARC has already demonstrated wireless power and temperature data transmission up to a distance of 20m with less than one minute between measurements, using power levels well within the FCC regulation limits in the 902–928 MHz ISM band. The sensor’s RF energy harvesting antenna achieves high performance with dimensions below 5cm × 9cm.

Topics: Sensors
Commentary by Dr. Valentin Fuster
2017;():V001T03A006. doi:10.1115/IPACK2017-74191.

Identifying fugitive methane leaks can improve predictive maintenance of the extraction process, can extend gas extraction equipment lifetime, and eliminate hazardous work conditions. We demonstrate a wireless sensor network based on cost effective and robust chemi-resistive methane sensors combined with real time analytics to identify leaks from 2 scfh to 1000 scfh. The chemi-resistive sensors were validated to have a sensitivity better than 1 ppm in methane plume detection. The real time chemical sensor and wind data is integrated into an inversion models to identify the location and the magnitude of the methane leak. This integrated sensing and analytics solution can be deployed in outdoor environment for long term monitoring of accidental methane plume emissions, generate recommendations about fixing them, and ensure compliance with local government regulations.

Commentary by Dr. Valentin Fuster
2017;():V001T03A007. doi:10.1115/IPACK2017-74239.

This paper focusses on health monitoring of electronic assemblies under vibration load of 14 G until failure at an ambient temperature of 55 degree Celsius. Strain measurements of the electronic assemblies were measured using the voltage outputs from the strain gauges which are fixed at different locations on the Printed Circuit Board (PCB). Various analysis was conducted on the strain signals include Time-frequency analysis (TFA), Joint Time-Frequency analysis (JTFA) and Statistical techniques like Principal component analysis (PCA), Independent component analysis (ICA) to monitor the health of the packages during the experiment. Frequency analysis techniques were used to get a detailed understanding of the different frequency components before and after the failure of the electronic assemblies. Different filtering algorithms and frequency quantization techniques gave insight about the change in the frequency components with the time of vibration and the energy content of the strain signals was also studied using the joint time-frequency analysis. It is seen that as the vibration time increases the occurrence of new high-frequency components increases and further the amplitude of the high-frequency components also has increased compared to the before failure condition. Statistical techniques such as PCA and ICA were primarily used to reduce the dimensions of the larger data sets and provide a pattern without losing the different characteristics of the strain signals during the course of vibration of electronic assemblies till failure. This helps to represent the complete behavior of the electronic assemblies and to understand the change in the behavior of the strain components till failure. The principal components which were calculated using PCA discretely separated the before failure and after failure strain components and this behavior were also seen by the independent components which were calculated using the Independent Component Analysis (ICA). To quantify the prognostics and hence the health of the electronic assemblies, different statistical prediction algorithms were applied to the coefficients of principal and independent components calculated from PCA and ICA analysis. The instantaneous frequency of the strain signals was calculated and PCA and ICA analysis on the instantaneous frequency matrix was done. The variance of the principal components of instantaneous frequency showed an increasing trend during the initial hours of vibration and after attaining a maximum value it then has a decreasing trend till before failure. During the failure of components, the variance of the principal component decreased further and attained a lowest value. This behavior of the instantaneous frequency over the period of vibration is used as a health monitoring feature.

Commentary by Dr. Valentin Fuster
2017;():V001T03A008. doi:10.1115/IPACK2017-74269.

Field extracted electrical assemblies, subjected to harsh environments including storage, and transportation may have often sustained degradation in their material properties and physical structure, without exhibiting external signs of damage. The lack of macro-indicators of damage makes the quantification of sustained damage and the remaining useful life challenging for assessment of the reliability makes quantification of accrued damage and remaining useful life much difficult. The operation environment requires survivability under high-g loads often in excess of 10,000g-100,000g. The need of non-destructive test methods for determination of the internal damage and the assessment of expected operational reliability under the presence of accrued damage from prolonged storage is extremely desirable. While a number of non-destructive test methods such as x-ray, and acoustic imaging exist in the state-of-art — they are limited to the acquisition of imaging of the internal damage state without the ability of conducting measurement of deformation under the action of environment loads. There is scarcity of literature on studying progressive damage to the physical structure of fuze components when subjected to high g shocks. Previously, researchers have studied the reliability of fuze subjected to high-temperature and high-g mechanical shocks, measured redundancy and reliability of fuze electronics through prediction of failure rates and MTTF using MIL-HDBK-217F standard, and performed on fault diagnosis. In this paper, a full-field deformation measurement technique has been presented to monitor damage in key components of the fuze after exposure to multiple high G shocks. Fuze assembly has been subjected to 30,000g mechanical shock until failure. The fuze assembly is CT scanned at regular intervals and the scan data is compared to the pristine scan data to compute physical deformations and damage sustained during the mechanical shock event.

Commentary by Dr. Valentin Fuster
2017;():V001T03A009. doi:10.1115/IPACK2017-74304.

Interpreting sensor data requires knowledge of sensor placement and the contextual environment surrounding the sensor. For a single sensor measurement, it is easy to document the context usually by visual observation. However, for millions of sensors reporting data back to a server, the contextual information needs to be automatically extracted from either data analysis or leveraging complimentary data sources. Data layers that overlap spatially or temporally with sensor locations, can be used to extract the context and validate the measurement. The second challenge is to minimize the amount of sensor data transmitted through the internet while preserving signal information content. Here we demonstrate two methods for communication bandwidth reduction: computation at the edge and compressed sensing. We validate the above methods on wind and chemical sensor data to: (1) eliminate redundant measurement from wind sensors and (2) extract peak value of a chemical sensor measuring a methane plume. We present a general cloud based framework to validate sensor data based on statistical and physical modeling and contextual data extracted from geospatial data.

Topics: Sensors , Internet
Commentary by Dr. Valentin Fuster

Energy Conversion and Storage: Batteries and Storage Devices

2017;():V001T04A001. doi:10.1115/IPACK2017-74118.

Metallic phase change materials (PCMs) have been demonstrated as an excellent alternative to act as a passive cooling system for pulse power applications. The possibility of integrating metallic PCMs, directly on top of a heat source, reducing the thermal resistance between the device and the cooling solution, could result in a significant improvement in thermal management for transient applications. However, the effectiveness of this method of implementation will depend on the quality of the interface between the metallic PCM and the heat source.

For this work, a metallic PCM (49Bi/18Pb/12Sn/21In-Bi/Pb/Sn/In for simplicity) was placed directly on top of a device that has a layer of silicon nitride on the top. The device was pulsed with powers of 40W – 160W (84W/cm2 – 338W/cm2) with a 20 ms duration. After reaching the maximum power, the device was pulsed for a second cycle, and the temperature profiles were compared. Micrographical inspections, at the interlayer between the silicon nitride and metallic PCM, were performed before and after the pulses and compared.

A maximum temperature of ≈20–25% higher was observed in the performance (at 80W) after pulse cycling. A visual inspection at the mating surfaces, between the metallic PCM and device, showed a clear difference between the contact surfaces before and after pulses. Significant voiding at the PCM interfacial layer was observed after cyclic loading which is believed to be the cause of the recorded increment in maximum temperature.

Commentary by Dr. Valentin Fuster
2017;():V001T04A002. doi:10.1115/IPACK2017-74244.

The energy density and power density are critical properties of thermal energy storage systems. Use of a phase change material as the storage medium provides high energy density due to the ability to store energy as latent heat during the phase transition; however, the power density is limited by the low thermal conductivity. Insertion of a highly conductive graphite foam within the material can increase the rate of thermal response of the phase change material. As the graphite bulk density increases, the thermal conductivity increases, but the composite latent heat decreases due to displacement of the phase change material. This introduces a trade-off between energy density and power density of the composite.

In this work, a validated numerical model is used to study the trade-off between energy density and power density with respect to graphite bulk density under various imposed heat fluxes. Comparisons are made based on the melting time, junction temperature between the composite and the heat source, and the volumetric energy density. To simplify the complicated relationship between composite thermophysical properties and charging response, two non-dimensional numbers are used. The Fourier number provides a comparison between the heat storage and heat diffusion by considering the thermal conductivity, latent heat, sensible heat, density, melting time, and volume. A dimensionless temperature compares the junction temperature (temperature between the heat source and the composite) when the sample is fully melted to the melt onset temperature. These non-dimensional numbers can assist in the design of latent heat storage systems where some parameters are fixed (such as heat flux, junction temperature, mass, operating time, or required energy storage) and others must be determined by the design (such as required thermal conductivity or height).

Commentary by Dr. Valentin Fuster

Energy Conversion and Storage: Harsh Environment and High Temperature Electronics

2017;():V001T04A003. doi:10.1115/IPACK2017-74138.

Transient Liquid Phase Sintering (TLPS) is a novel high temperature attach technology. It is of particular interest for application as a die attach in power electronic systems because of its high melting temperature and high thermal conductivity. TLPS joints formed from sinter pastes are comprised of metallic particles embedded in matrices of Intermetallic Compounds (IMCs). Compared to conventional solder attach, TLPS joints contain a considerably higher percentage of brittle IMCs. This raises the concern that TLPS joints are susceptible to brittle failure. In this paper we describe and analyze the cooling-induced formation of vertical cracks as a newly detected failure mechanism unique to TLPS joints.

In a power module structure with a TLPS joint as interconnect between a power device and a Direct Bond Copper (DBC) substrate, cracks can form between the interface of the DBC and the TLPS joint when large voids are located in the proximity of the DBC. These cracks do not appear in regions with smaller voids. A method has been developed for the three-dimensional modeling of paste-based TLPS sinter joints that possess complex microstructures with heterogeneous distributions of metal particles and voids in IMC matrices. Thermo-mechanical simulations of the post-sintering cooling process have been performed and the influence of microstructure on the stress-response within the joint and at the joint interfaces have been characterized for three different material systems (Cu+Cu6Sn5, Cu+Cu3Sn, Ni+Ni3Sn4).

The maximum principal stress within the assembly was found to be a poor indicator for prediction of vertical crack formation. In contrast, stress levels at the interface between the TLPS joint and the power substrate metallization are good indicators for this failure mechanism. Small voids lead to higher joint maximum principal stresses, but large voids induce higher interfacial stresses, which explain why the vertical cracking failure was only observed in joints with large voids.

Commentary by Dr. Valentin Fuster
2017;():V001T04A004. doi:10.1115/IPACK2017-74169.

Predominant high melting point solders for high temperature and harsh environment electronics (operating temperatures from 200 to 250°C) are Pb-based systems, which are being subjected to RoHS regulations because of their toxic nature. In this study, high bismuth (Bi) alloy compositions with Bi-XSb-10Cu (X from 10 wt.% to 20 wt.%) were designed and developed to evaluate their potential as high-temperature, Pb-free replacements. Reflow processes were developed to make die-attach samples made out of the cast Bi alloys. In particular, die-attach joints made out of Bi-15Sb-10Cu alloy exhibited an average shear strength of 24 MPa, which is comparable to that of commercially available high Pb solders. These alloy compositions also retained original shear strength even after thermal shock between −55°C and +200°C and high temperature storage at 200°C. Brittle interfacial fracture sometimes occurred along the interfacial NiSb layer formed between Bi(Sb) matrix and Ni metallized surface. In addition, heat dissipation capabilities, using flash diffusivity, were measured on the die-attach assembly, compared to the corresponding bulk alloys. The thermal conductivity of all the Bi-Sb alloys was higher than that of pure Bi. By creating high volume fraction of precipitates in a die-attach joint microstructure, it was feasible to further increase thermal conductivity of this joint to 24 W/m·K, which is three times higher than that of pure Bi (8 W/m·K). Bi-15Sb-10Cu alloy has so far shown the most promising performance as a die-attach material for high temperature applications (operated over 200°C). Hence, this alloy was further studied to evaluate its potential for plastic deformation. Bi-15Sb-10Cu alloy has shown limited plastic deformation in room temperature tensile testing, in which premature fracture occurred via the cracks propagated on the (111) cleavage planes of rhombohedral crystal structure of the Bi(Sb) matrix. The same alloy has, however, shown up to 7% plastic strain under tension when tested at 175°C. The cleavage planes, which became oriented at smaller angles to the tensile stress, contributed to improved plasticity in the high temperature test.

Commentary by Dr. Valentin Fuster

Energy Conversion and Storage: Photovoltaics, Thermoelectrics, Energy Harvesting Devices

2017;():V001T04A005. doi:10.1115/IPACK2017-74015.

The transient and steady state response of a thermal system with thermoelectric coolers has been studied analytically. The system is comprised of a device with thermal mass inside an insulated enclosure, thermal resistance between the mass and the thermoelectric cooler, insulation thermal resistance, TIM between thermoelectric cooler layers, and a heatsink on the hot side of the thermoelectric cooler. It is assumed that the thermal mass of the thermoelectric cooler is negligible compared to other thermal masses. The analytical transient solution consists of two exponential eigen functions and hence two time scales (i.e. two eigen values). The analytical solution has been validated with a numerical Runge-Kutta solution. A simple method is explained to combine thermoelectric coolers in series and parallel. The time scales are studied for different parameters and the key parameters for time scale minimization are identified. It is found that the thermoelectric module thermal resistance limits the fastest transient response.

Commentary by Dr. Valentin Fuster
2017;():V001T04A006. doi:10.1115/IPACK2017-74112.

Rapid advancement of modern electronics has pushed the limits of traditional thermal management techniques. Novel approaches to the manipulation of the flow of heat in electronic systems have potential to open new design spaces. Here, the field of thermal metamaterials as it applies to electronics is briefly reviewed. Recent research and development of thermal meta-material systems with anisotropic thermal conductivity for the manipulation of heat flow in ultra-thin composites is explained. An explanation of fundamental experimental studies on heat flow control using standard printed circuit board technology follows. From this, basic building blocks for heat flux cloaking, focusing, and reversal are reviewed, and their extension to a variety of electronics applications is emphasized. While device temperature control, thermal energy harvesting, and electro-thermal circuit design are the primary focus, some discussion on the extension of thermal-guiding structures to device-scale applications is provided. In total, a holistic view is offered of the myriad of possible applications of thermal metamaterials to heat flow control in future electronics.

Commentary by Dr. Valentin Fuster
2017;():V001T04A007. doi:10.1115/IPACK2017-74147.

Creating a large surface area from a packed bed of particles is a necessary step for many packing, chemical, and heat transfer applications. However, the excessive pressure drop across the packed bed is not desirable in many of these applications. This problem can be addressed by using microchannels instead of the packed bed of particles, providing a high heat transfer rate at the acceptable pressure drop range. Microchannels offer a reduced amount of pressure drop due to their ability to introduce a low resistance flow passage while still providing the large surface area for heat and mass transfer. In this study, a magnetic stabilization process was developed to fabricate microchannels from the fine ferrite particles. The experimental hydrodynamic performance evaluation of such structures is described in this paper. This unique microchannel fabrication method can significantly improve thermal and hydrodynamic performance, while providing additional flexibility to control the porosity of the packed bed of particles.

Topics: Microchannels
Commentary by Dr. Valentin Fuster
2017;():V001T04A008. doi:10.1115/IPACK2017-74212.

The ability to manipulate heat flow can result in wonderful applications such as thermal logic and memory devices. Thermal logic and memory devices are similar to their electronic counterparts, however, they are powered solely by heat. In addition, thermal logic and memory devices can operate in harsh environments where electronics typically fail. Despite our understanding of various mechanisms of heat transfer, controlling heat (in a sense of switching heat flow on or off) is more challenging than controlling electricity due to the lack of perfect thermal insulators. One possible solution is to control the near-field thermal radiation heat transfer between hot and cold terminals by manipulating the size of the vacuum gap separating the two. Unlike far-field thermal radiation, near-field thermal radiation intensity increases exponentially with decreasing the gap size. There are however challenges in manipulating the nano/micro vacuum gaps to achieve enough contrast in heat transfer between the high and low heat transfer cases. In this paper, we present a prototype of a microdevice with a controllable micro gap of size 3 μm (initial gap size) between the hot and cold terminals; this configuration achieves a contrast in near-field radiative heat transfer at temperatures as high as 600 K. Furthermore, we present numerical analysis for meshed photonic crystals to achieve even higher contrast in radiative heat transfer with enhancement in heat transfer as high as 26 times in comparison to far-field.

Commentary by Dr. Valentin Fuster
2017;():V001T04A009. doi:10.1115/IPACK2017-74243.

This paper provides an overview of a thermoelectric heat pump clothes dryer which was developed with the aim of reducing the significant primary energy consumption attributed to residential electric clothes drying in the United States (623 TBtu/yr). The use of thermoelectric modules in place of the conventional electric resistance heater resulted in a 40% reduction in the energy consumption of the system, compared to the minimum energy efficiency standard. This was achieved for the first time for a standard test load of 8.45 lb, using a clothes dryer prototype with a thermoelectric heat pump module as the sole heating mechanism. The current experimental prototype was developed after extensive modeling, system design and control optimization, and experimental system-level evaluation of control parameters. The demonstration of improved energy consumption has laid the foundation for future development of this technology.

Commentary by Dr. Valentin Fuster

Energy Conversion and Storage: Power Electronics Wide Band Gap Semiconductors, Packaging, Module Assembly and Thermal Management

2017;():V001T04A010. doi:10.1115/IPACK2017-74095.

A series of experiments was conducted to investigate the performance characteristics of a heat pipe with a hybrid wick that combined grooves and a wire screen. The heat pipe in this study was designed primarily for the cooling of high-density power electronic elements such as IGBTs, and it had tiny triangular grooves along its entire length. The container was a copper tube which had an outer diameter of 19 mm and length of 0.8 m, and the working fluid was water. To lower the thermal resistance against increased thermal loads, a higher performance was desired for the heat pipe, without changing the external dimensions. A fine mesh wire screen was partially applied to the evaporator to enhance the heat transfer performance. The hybrid wick heat pipe was tested and analyzed from the viewpoints of thermal resistance, effective thermal conductance, and operating temperature. For a 1.6 kW effective thermal load, as a typical result, the heat pipe with the hybrid wick exhibited a 70 % decrease in thermal resistance compared to that with a groove wick only. The paper includes results for various thermal loads and fluid charges. The results herein can be utilized in applications that require an intensive enhancement in heat pipe performance.

Commentary by Dr. Valentin Fuster
2017;():V001T04A011. doi:10.1115/IPACK2017-74125.

AlGaN/GaN high electron mobility transistors (HEMTs) are widely used in high frequency and power applications of the space and military industries due to their high RF power densities. When operated in full capacity, reliability of GaN HEMTs drop significantly due to device degradation, electron collapse phenomena, and concentrated heating effects. Although significant research has been done to investigate the effects of passivation, field-plates on the device degradation and the electron collapse separately, combined electrothermal analysis of the field-plates and the SiO2 passivation on GaN HEMTs has not been performed from the perspective of device reliability. For this purpose, electrothermal simulations of the field-plated and non-field-plated devices with different SiO2 passivation thicknesses are performed using Sentaurus TCAD to obtain the electrical field distribution and Joule heating caused temperature distribution in operating devices. Using these results, electrical and thermal effects of the field-plates on the devices with different SiO2 passivation thicknesses are analyzed to obtain the most effective and reliable operating conditions.

Topics: Gallium nitride
Commentary by Dr. Valentin Fuster
2017;():V001T04A012. doi:10.1115/IPACK2017-74130.

This work presents an easy to use approach to quickly estimate the device temperatures and thermal stresses in a generic high power module. A low order model was developed in MATLAB using a combination of numerical-analytical approach and a 3D nodal resistor network to calculate device temperatures and thermal stresses. The model assumes a heat flux generated at the top of each device which is dissipated through the packaging structure and removed by convection. The temperature distribution is used to calculate thermal stresses throughout the package. This method eliminates computer aided drawings (CAD) in favor of numerical parameters that can be easily and quickly varied over a wide range. The resistor network solves quickly in MATLAB, enabling fast, iterative thermal analyses and design through parametric studies of the chip dimensions, number of chips, chip layout, material types, cooling solutions, etc. The model is adaptable to any number of devices and board layers. The MATLAB model reduced the computational time by 97% compared to an equivalent SOLIDWORKS finite element analysis (FEA) model and that does not include the time required to generate the CAD model and verify mesh convergence and mesh independence. Temperatures from the network model were within 5°C and stresses were within 30% of the values obtained from the FEA model. The ability to quickly assess the thermal and stress effects of a wide variety of power module design parameters during the initial design process, without the complexity of a full FEA analysis, with reasonable results can significantly improve the final module.

Topics: Stress , Packaging
Commentary by Dr. Valentin Fuster
2017;():V001T04A013. doi:10.1115/IPACK2017-74132.

This work presents a demonstration of a coefficient of thermal expansion (CTE) matched, high heat flux vapor chamber directly integrated onto the backside of a direct bond copper (DBC) substrate to improve heat spreading and reduce thermal resistance of power electronics modules. Typical vapor chambers are designed to operate at heat fluxes > 25 W/cm2 with overall thermal resistances < 0.20 °C/W. Due to the rising demands for increased thermal performance in high power electronics modules, this vapor chamber has been designed as a passive, drop-in replacement for a standard heat spreader. In order to operate with device heat fluxes >500 W/cm2 while maintaining low thermal resistance, a planar vapor chamber is positioned onto the backside of the power substrate, which incorporates a specially designed wick directly beneath the active heat dissipating components to balance liquid return and vapor mass flow. In addition to the high heat flux capability, the vapor chamber is designed to be CTE matched to reduce thermally induced stresses. Modeling results showed effective thermal conductivities of up to 950 W/m-K, which is 5 times better than standard copper-molybdenum (CuMo) heat spreaders. Experimental results show a 43°C reduction in device temperature compared to a standard solid CuMo heat spreader at a heat flux of 520 W/cm2.

Commentary by Dr. Valentin Fuster
2017;():V001T04A014. doi:10.1115/IPACK2017-74163.

From a materials perspective, diamond exhibits properties that are extremely well suited for use in the thermal management of high power and high heat flux electronic devices. While bulk diamond grown via chemical vapor deposition (CVD) has been demonstrated since the 1980s, and people have measured thermal conductivities ranging from 500–2000 W/m-K, these measurements have typically taken place over a large domain that encompasses numerous diamond grains. However, many of these techniques do not reveal the heterogenous nature of the diamond thermal conductivity which arises due to the local grain structure and orientation. The diamond sample investigated in this study contained a high level of boron doping on the order of 1021cm−3, giving rise to a reduced thermal conductivity measured as 714 W/m-K with a laser flash method. Similar bulk CVD diamond samples that are undoped show thermal conductivity values of greater than 1500 W/m-K with the same measurement technique.

Through the use of time-domain thermoreflectance (TDTR) we are able to measure the thermal conductivity of bulk CVD diamond at a spatial resolution smaller than the size of the columnar grains. This allows us to examine significant changes in thermal conductivity as a function of spatial location, which is of great significance when the thermal source from electronics is on the size scale of this variation. Using TDTR, we present an approach involving a variation in the laser spot size using multiple focusing objectives to yield the heterogeneous thermal conductivity in bulk CVD diamond. The data show variations in thermal conductivity near 40% over a diameter of 40 μm. Scanning Electron Microscopy (SEM) and electron backscatter diffraction (EBSD) data are presented which also show variation in microstructure over this length scale giving rise to the heterogeneity.

Commentary by Dr. Valentin Fuster
2017;():V001T04A015. doi:10.1115/IPACK2017-74213.

Wide bandgap (WBG) semiconductors are revolutionizing the world of power electronics. They have the potential to bring about an unprecedented increase in power density. The ability to switch at ultrafast rates, coupled with the promise of high temperature operation, make these devices extremely desirable. However, having superior semiconductor devices will not automatically translate to superior package characteristics. In real applications, the performance of a power device is only as good as the package allows. One of the major drawbacks plaguing contemporary power modules is the wire-bonded interconnection. Wire bonds offer a high parasitic inductance. This paper presents a novel wire bondless SiC power MOSFET packaging technique. A commercially available bare die was reconfigured into a chip-scale package. The new form factor enabled the MOSFET to be bonded to a patterned FR4 substrate using flip-chip bonding. The electrical interconnection between the package and the substrate was established using solder balls — thus eliminating the requirement for wire bonds. The motivation for using a wire bondless method was a reduction in stray parasitic inductances and an increase in the thermo-mechanical reliability. Lower parasitic inductances will facilitate high switching frequencies which will promote miniaturization, a reduction in electromagnetic interference (EMI), and lead to lower switching losses. The proposed approach was demonstrated to reduce the parasitic loop inductance by a fctor of > 3× as compared with wire bonded modules.

Topics: Wire , Silicon , Packaging
Commentary by Dr. Valentin Fuster

Transportation: Autonomous and Electric Vehicles: Device to System Level Reliability

2017;():V001T05A001. doi:10.1115/IPACK2017-74190.

Electronic products used in autonomous vehicles can be subjected to harsh road conditions. Transportation induced vibration is one such reliability risk to be addressed as part of qualification. Vibration use data and reliability models are very extensively studied for fully packaged systems exposed to vibration risks during shipping. MIL-STD-810G and ISTA4AB are some of the industry standards that address these risks. On the other hand, USCAR-2 and GMW-3172 are couple of standards that may be more relevant for electronics used in automotive applications, where electronic components are exposed to vibration risks during their entire lifetime. Even though the usage model and duration for fully packaged systems in shipping and automotive electronics are different, the source of energy (road conditions), driving the risks are similar. The industry standards based damage model appear to be generic, covering a wide variety of products. In this paper, a knowledge based qualification (KBQ) framework, is used to map use conditions to accelerated test requirements for two failure modes: solder joint fatigue and socket contact fretting. The mechanisms chosen are distinct with different damage metric and drivers. The KBQ obtained qualification requirements were discussed relative to standard requirement with the objective to verify how well industry standard models reflect field reliability risks. For the chosen failure mechanisms and use condition data, it was observed that the industry standards lead to erroneous conclusions about vibration risk in the field.

Commentary by Dr. Valentin Fuster
2017;():V001T05A002. doi:10.1115/IPACK2017-74245.

With the anticipated growth in the electric vehicle market, advances in power electronics used in electric drivetrain, battery charging systems, etc. are delivering higher power densities, and with them, associated thermal challenges for operation in relatively closed vehicular systems. As such, the framework of reliability qualifications of electronic devices need to be reconsidered as system needs have moved beyond typical consumer electronic device needs, such as laptops or entertainment devices, where safe operation and longevity is essential to electric vehicle market viability. This work provides an overview of the reliability challenges associated with the operating environments and characteristics of power inverters in electric vehicles, particularly with respect to thermomechanical stresses. When considering the acceleration models presumed by the AEC Q100 specification for automotive electronics qualification, it is shown that inconsistencies in acceleration model form result in lack of clarity of how grades are chosen for different vehicle applications. Furthermore, the differences in vehicle drive cycles among user types show that service vehicles may have the most challenge to reliable operation, particularly in cold weather climates.

As an alternative metric for determining reliability in cyclic stresses, a novel test methodology for correlating solder fatigue life (and other thermomechanical failure modes) is proposed. The mechanical test for electronic packages is capable to disentangle the effects of temperature and design from the thermal cycling reliability such that the fundamental physics of failure can be extracted in a systematic fashion, and thereby develop better physics-based reliability acceleration models. Moreover, this novel approach enables the determination of independent stress to failure metrics that can translate risk across design and operating conditions for different system layouts without the need for multiple qualification tests.

Commentary by Dr. Valentin Fuster
2017;():V001T05A003. doi:10.1115/IPACK2017-74273.

Polymer materials have been widely used in electronic packaging with many advantages such as: lower cost, light weight and good performance. They however suffer a major drawback that results in a number of challenges for reliability engineers and researchers, in which polymer materials are quite sensitive to moisture absorption when exposed to humid environment, causing many failure modes in electronic packages such as: popcorn cracking, delamination or corrosion. It is well-known that finite element simulation is a powerful tool to evaluate the effects of moisture on electronic package reliability. In this study, three moisture properties (diffusivity, saturated concentration, and coefficient of moisture expansion) were experimentally characterized. The obtained results were then used to perform moisture diffusion simulations on various types of electronic package. Finally, a numerical study was conducted on the dependence of the moisture effects (weight gains, die stresses) upon each moisture property of polymeric components of three kinds of electronic packages (Quad Flat Package, Plastic Ball Grid Array, and Flip Chip on Laminate). The results of the study provided valuable insights into how moisture induced die stresses vary with each moisture property of polymeric components in the packages.

Commentary by Dr. Valentin Fuster

Transportation: Autonomous and Electric Vehicles: High Temperature Electronics

2017;():V001T05A004. doi:10.1115/IPACK2017-74286.

Silver is a leading competitor to gold and copper in fine pitch wire bonding used in the interconnection of microelectronic devices. Primary material for wire bonding has been gold, which gave way to copper in order for original equipment manufacturers to realize cost benefits. However, copper wire bonding has exhibited several reliability issues, especially in industrial and high temperature applications. Corrosion is the major problem, which was mitigated by coating the wire with palladium, which increased overall cost of production. Other concerns include harder free air ball (FAB) leading to under pad metallization cracking, smaller process window, excessive aluminum splash especially in fine pitch bonding, and lower throughput and yield arising from the hardness and stiffness of copper. Due to the above concerns, automotive, military and aerospace industries are still reluctant to fully adopt copper wire bonding. Light emitting diodes (LEDs) are also not manufactured with copper wires due to its low reflectance. Some of these industries are still using gold wire bonds in most of their packages, but are continually looking for an alternative. Silver wire bonds have good electrical and thermal conductivity, are less prone to corrosion than copper, have low melting points and comparable hardness to gold. Also, cost of silver has been shown to be similar to that of palladium coated copper wire, hence making it a good alternative. Silver wire bonding, a relatively new area of research, has attracted a lot of research focused on wire dopant material, bonding process, quality and reliability. This paper is aimed to serve as a comprehensive review of research done in this area, by summarizing the literature on silver wire bonding, establishing benefits and drawbacks over other wire bond materials and indicating reliability concerns along with failure modes and mechanisms.

Topics: Silver , Wire bonding
Commentary by Dr. Valentin Fuster
2017;():V001T05A005. doi:10.1115/IPACK2017-74322.

Electronics components operating under extreme thermo-mechanical stresses are often protected with conformal coating and potting encapsulation to isolate the thermal and vibration shock loads. Development of predictive models for high-g shock survivability of electronics requires the measurement of the interface properties of the potting compounds with the printed circuit board materials. There is scarcity of interface fracture properties of porting compounds with printed circuit board materials. Potting and encapsulation resins are commonly two-part systems which when mixed together form a solid, fully cured material, with no by-products. The cured potting materials are prone to interfacial delamination under dynamic shock loading which in turn potentially cause failures in the package interconnects. The study of interfacial fracture resistance in PCB/epoxy potting systems under dynamic shock loading is important in mitigating the risk of system failure in mission critical applications. In this paper three types of epoxy potting compounds were used as an encapsulation on PCB samples. The potting compounds were selected on the basis of their ultimate elongation under quasi-static loading. Potting compound, A is stiffer material with 5% of ultimate elongation before failure. Potting compound, B is a moderately stiff material with 12% ultimate elongation. Finally potting compound C is a softer material with 90% ultimate elongation before failure. The fracture properties and interfacial crack delamination of the PCB/epoxy interface was determined using three-point bend loading with a pre-crack in the epoxy near the interface. The fracture toughness and crack initiation of the three epoxy systems was compared with the cure schedule and temperature. Fracture modeling was performed with crack tip elements in ABAQUS finite element models to determine the crack initiation and interfacial stresses. A comparison of the fracture properties and the performance of epoxy system resistance to delamination was shown through the three-point bend tests. The finite element model results were correlated with the experimental findings.

Commentary by Dr. Valentin Fuster
2017;():V001T05A006. doi:10.1115/IPACK2017-74325.

Transition of ground vehicles to HEV and FEV has necessitated the operation of electronics in automotive underhood at high voltage bias and high temperature for extended period-of-time. Examples include gate drivers and IGBT modules. A typical automotive benchmark is operation for 10 years and 100,000 miles. Simultaneously, the first-level interconnects are migrating to use copper-wire interconnects in place of the previously used gold wire. Copper wire has higher propensity for corrosion and a narrower process-bonding window in comparison with gold wire based systems. Exposure to high temperature, humidity and bias influences the mobility of ions in the EMC and thus the contaminant transport to the WB interfaces. Measurements of diffusion behavior of EMCs at high temperature and high voltage bias are not available for readily being used in models. Prior studies have focused on biased humidity tests on wire bonds with the amplitude of the bias being limited up to 3.5Volts. In this paper, a PWM-controlled-gate drive-based test setup is established to study the effect of high voltage (up to 20Volts) on Cu-Al wire bond interconnects. A migration-diffusion cell experiment is designed to quantify the effect of voltage bias on transport of chlorine in EMCs. Diffusion coefficient and ionic mobility of chlorine at different temperatures are obtained. Resistance spectroscopy measurements show the progression of corrosion induced by voltage bias. A corrosion simulation is used to quantify the effect of voltage bias on corrosion rate of Cu-Al wire bond.

Commentary by Dr. Valentin Fuster

Transportation: Autonomous and Electric Vehicles: Simulation and Test Methods

2017;():V001T05A007. doi:10.1115/IPACK2017-74073.

Fracture mechanics is an essential field of study towards the improvement and development of electronic packages. In combination with modern simulation method such as finite element analysis (FEA), fracture mechanics is widely used and appreciated in the industry. Many different approaches have been developed to calculate the fracture parameters for interfaces or bulk material under given loads in order to compare them against previously measured failure criteria. While many publications are available that have described the different simulation approaches in detail or compare the different fracture test methods, there have been few comparisons of these simulation approaches with respect to their use in research and development of electronic packages.

The objective of this work is to compare different delamination modeling methodologies and their applications for electronic packaging. The work highlights the differences in theory behind each approach as well as the differences in their practical use to predict delamination or asses a fracture risk in electronic packages. The intention was to use commercially available FE-codes in conjunction with a well-defined set of adhesion strength tests. During this work, energy based fracture criteria were applied by means of the virtual crack closure technique (VCCT), the J-integral and the cohesive zone material model (CZM) methods. These methodologies are most commonly used but can differ significantly from each other as will be shown in this comparison. To demonstrate the use of these techniques, copper lead frame to epoxy mold compound (EMC) delamination was assessed, representing a very common packaging failure mode. Critical energy release rates were measured on multiple Copper-EMC test specimens under varying load phase angles. ANSYS was used to build mechanical simulation models of a selected device. Existing post processing procedures were applied to assess delamination risk based on above mentioned techniques. The simulation study considers realistic monotonic loading conditions and results will also be compared to existing failure analysis images for demonstration and validation purpose. As an outcome, the paper will include a ranking of the approaches as well as a summary of advantages and disadvantages, based method and accuracy. An outlook on future developments such as fatigue or aging phenomena will finish the work.

Commentary by Dr. Valentin Fuster
2017;():V001T05A008. doi:10.1115/IPACK2017-74208.

The revolutionary changes in automotive industry towards fully connected automated electrical vehicles necessitates developments in automotive electronics at unprecedented speed. Signal, control, and power electronics will heterogeneously be integrated at minimum space with sensors and actuators to form highly compact and ultra-smart systems for functions like traction, lighting, energy management, computation, and communication. Most of these systems will be highly safety relevant with the requirements in system availability exceeding today’s already high automotive standards. Other than the human drivers of today, passengers in the automated car do not pay constant attention to the driving actions of the vehicle. Hence, reliability research is massively challenged by the new automotive applications. Guaranteeing the specified lifetime at statistical average is no longer sufficient. Assuring that no failure of an individual safety relevant part occurs unexpectedly, becomes most important. The paper surveys the priority actions underway to cope with the tremendous challenges. It highlights practical examples in all three directions of reliability research. i) Experimental reliability tests and physical analyses: New and highly efficient accelerated stress tests are able to cover the complex and multi-fold loading situation in the field. New analytics techniques can identify the typical failure modes and their physical root causes. ii) Virtual techniques: Schemes of validated simulations allow capturing the physics of failure proactively in the design for reliability process. iii) Prognostics health management (PHM): A new concept is introduced for adding a minimum of PHM features at the various levels of automotive electronics to provide functional safety as required for autonomous vehicles. This way, the new generation of reliability methods will continuously provide estimates of the remaining useful life (RUL) for each relevant part under the actual use conditions to allow triggering maintenance in time.

Commentary by Dr. Valentin Fuster
2017;():V001T05A009. doi:10.1115/IPACK2017-74300.

Electronics in automotive underhood environments may be subjected to high temperatures in the neighborhood of 175°C while subjected to high strain rate mechanical loads of vibration. Portable products such as smartphones and tablets stay in the powered on condition for a majority of their operational life during which time the device internals are maintained at higher than ambient temperature. Thus, it would be expected for interconnects in portable products to be at a temperature high than room temperature when subjected to accidental drop or shock. Furthermore, electronics in missile-applications may be subjected to high strain rates after prolonged period of storage often at high temperature. Electronics systems including interconnects may experience high strain rates in the neighborhood of 1–100 per sec during operation at high temperature. However, the material properties of SAC305 leadfree solders at high strain rates and high operating temperatures are scarce after long-term storage. Furthermore, the solder interconnects in simulation of product drop are often modeled using elastic-plastic properties or linear elastic properties, neither of which accommodate the effect of operating temperature on the solder interconnect deformation at high operating temperature. SAC305 solders have been shown to demonstrate the significant degradation of mechanical properties including the tensile strength and the elastic modulus after exposure to high temperature storage for moderate periods of time. Previously, Anand’s viscoplastic constitutive model has been widely used to describe the inelastic deformation behavior of solders in electronic components under thermo-mechanical deformation. Uniaxial stress-strain curves have been plotted over a wide range of strain rates (Display Formulaε. = 10, 35, 50, 75 /sec) and temperatures (T = 25, 50, 75, 100, 125, 150, 175, 200°C). Anand viscoplasticity constants have been calculated by non-linear fitting procedures. In addition, the accuracy of the extracted Anand constants has been evaluated by comparing the model prediction and experimental data.

Topics: Alloys , Storage
Commentary by Dr. Valentin Fuster

Transportation: Autonomous and Electric Vehicles: Thermal Management of Electric Motors and Power Systems

2017;():V001T05A010. doi:10.1115/IPACK2017-74096.

The development of complex electronic modules requires very efficient simulation technique for faster design and optimization process. For smaller component level models, current state of the art FEM/CFD tools is sufficient if appropriate boundary conditions are used. But for larger system level models, this approach can be computationally expensive as the finite element model can lead to very large set of equations. Hence, there is a need for much efficient computational methods such as model order reduction (MOR). MOR was developed to study property of dynamical systems to reduce their complexity without changing input/output to the system.

Commentary by Dr. Valentin Fuster
2017;():V001T05A011. doi:10.1115/IPACK2017-74149.

In this work, we investigate the thermal response of GaN PIN diodes grown on a sapphire substrate and compare the results to GaN PIN diodes grown on a free standing GaN substrate (FS-GaN). Until now, thermal characterization techniques have been developed to assess the temperature distribution across lateral devices. Raman thermometry has shown to accurately measure the temperature rise across the depth of the GaN layer. Implementing this technique to assess the temperature distribution across the depth of a vertical GaN device is more challenging since a volumetric depth average is measured. The use of TiO2 nanoparticles is shown to overcome this issue and reduce the uncertainty in the peak temperature by probing a surface temperature on top of the device. For the sapphire substrate, an additional temperature rise of about 15 K was seen on the surface of the PIN diode as compared to the average in the bulk. While the steady state thermal measurements show an accurate estimation of the device’s peak temperature, the PIN diodes are normally operated under pulsed conditions and the thermal response of these devices under periodic joule heating must be assessed. A recently developed transient thermoreflectance imaging technique (TTI) is used in this study to monitor transient temperature rise and decay of top metal contact. Under the same biasing conditions, the FS-GaN PIN diode is found to result in less than half the temperature rise obtained by the sapphire substrate diode. Extracting time constants, a longer rise and decay is also observed in the sapphire substrate diode.

Commentary by Dr. Valentin Fuster

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