ASME Conference Presenter Attendance Policy and Archival Proceedings

2015;():V002T00A001. doi:10.1115/IPACK2015-NS2.

This online compilation of papers from the ASME 2015 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems (InterPACK2015) represents the archival version of the Conference Proceedings. According to ASME’s conference presenter attendance policy, if a paper is not presented at the Conference, the paper will not be published in the official archival Proceedings, which are registered with the Library of Congress and are submitted for abstracting and indexing. The paper also will not be published in The ASME Digital Collection and may not be cited as a published paper.

Commentary by Dr. Valentin Fuster

Advanced Electronics and Photonics, Packaging Materials and Processing: Interconnects Materials

2015;():V002T01A001. doi:10.1115/IPACK2015-48389.

Electronics products may often be exposed to high temperature during storage, operation and handling in addition to high strain rate transient dynamic loads during drop-impact. Electronics subjected to drop-impact, shock and vibration may experience strain rates of 1–100 per sec. There are no material properties available in published literature at high strain rate at elevated temperature. High temperature and vibrations can contribute to the failures of electronic system. The reliability of electronic products can be improved through a thorough understanding of the weakest link in the electronic systems which is the solder interconnects. The solder interconnects accrue damage much faster when subjected to Shock and vibration at elevated temperatures. There is lack of fundamental understanding of reliability of electronic systems subjected to thermal loads. Previous studies have showed the effect of high strain rates and thermal aging on the mechanical properties of leadfree alloys including elastic modulus and the ultimate tensile strength. Extended period of thermal aging has been shown to affect the mechanical properties of lead free alloys including elastic modulus and the ultimate tensile strength at low strain rates representative of thermal fatigue [Lee 2012, Motalab 2012]. Previously, the microstructure, mechanical response and failure behavior of leadfree solder alloys when subjected to elevated isothermal aging and/or thermal cycling [Darveaux 2005, Ding 2007, Pang 2004] have been measured. Pang [1998] has showed that young’s modulus and yield stress of Sn-Pb are highly depending on strain rate and temperature. The ANAND viscoplastic constitutive model has been widely used to describe the inelastic deformation behavior of solders in electronic components. Previously, Mechanical properties of lead-free alloys, at different high strain rates (10, 35, 50, 75 /sec) and elevated temperature (25 C-125 C) for pristine samples have been studied [Lall 2012 and Lall 2014]. Previous researchers [Suh 2007 and Jenq 2009] have determined the mechanical properties of SAC105 at very high strain rate (Above 1000 per sec) using compression testing. But there is no data available in published literature at high strain rate and at elevated temperature for aged conditions. In this study, mechanical properties of lead free SAC105 has been determined for high strain rate at elevated temperature for aged samples. Effect of aging on mechanical properties of SAC105 alloy a high strain rates has been studied. Stress-Strain curves have been plotted over a wide range of strain rates and temperatures for aged specimen. Experimental data for the aged specimen has been fit to the ANAND’s viscoplastic model. SAC105 leadfree alloys have been tested at strain rates of 10, 35, 50 and 75 per sec at various operating temperatures of 50°C, 75°C, 100°C and 125°C. The test samples were exposed to isothermal aging conditions at 50°C for different aging time (30, 60, and 120 Days) before testing. Full-field strain in the specimen have been measured using high speed imaging at frame rates up to 75,000 fps in combination with digital image correlation. The cross-head velocity has been measured prior-to, during, and after deformation to ensure the constancy of cross-head velocity.

Commentary by Dr. Valentin Fuster
2015;():V002T01A002. doi:10.1115/IPACK2015-48619.

In the electronic packaging industry, it is important to be able to make accurate predictions of board level solder joint reliability during thermal cycling exposures. The Anand viscoplastic constitutive model is often used to represent the material behavior of the solder in finite element simulations. This model is defined using nine material parameters, and the reliability prediction results are often highly sensitive to the Anand parameters. In this work, an investigation on the Anand constitutive model and its application to SAC solders of various Ag contents (i.e. SACN05, with N = 1, 2, 3, 4) has been performed. For each alloy, both water quenched (WQ) and reflowed (RF) solidification profiles were utilized to establish two unique specimen microstructures, and the same reflow profile was used for all four of the SAC alloys so that the results could be compared and the effects of Ag content could be studied systematically. In addition, we have performed tensile testing on reflowed specimens subjected to 6 months of aging at 100 C. After this level of aging, any further changes in the mechanical response and properties will be rather small. Thus, the results for these tests can be regarded as approaching the highest level of mechanical behavior degradation possible for a “severely aged” lead free solder material.

The nine Anand parameters were determined for each unique solder alloy and microstructure from a set of stress strain tests performed at several strain rates and temperatures. Testing conditions included strain rates of 0.001, 0.0001, and 0.00001 (sec−1), and temperatures of 25, 50, 75, 100, and 125 C. As expected, the mechanical properties (modulus and strength) increase with the percentage of Ag content, and these changes strongly affect the Anand parameters. The sensitivity of the mechanical properties and Anand parameters to silver content is higher at lower silver percentages (1–2%). Also, the observed mechanical properties of water quenched samples were better (higher in magnitude) than the corresponding mechanical properties of the reflowed samples. Although the differences in elastic modulus between the water quenched and reflowed samples are relatively small, significant differences are present for the yield and ultimate tensile stresses of all four SAC alloys.

The changes in the Anand model parameters after severe aging (6 months at 100 °C) were significant. The measured experimental results have been used to illustrate the range of values possible for Anand parameters for the SACN05 alloys. The upper extreme was the water quenched limit, where the materials have extremely fine microstructures and high mechanical properties. The lower extreme was the severely aged limit, where the materials have extremely coarsened microstructures and highly degraded mechanical properties. While further degradations are certainly possible with even further aging, the limiting values found for a severely aged SAC alloy can be used by designers as a conservative set of constitutive parameters representing the lower end of the material properties for that alloy.

After deriving the Anand parameters for each alloy and microstructure, the stress-strain curves have been calculated for various conditions, and excellent agreement was found between the predicted results and experimental stress-strain curves.

Commentary by Dr. Valentin Fuster
2015;():V002T01A003. doi:10.1115/IPACK2015-48624.

In the electronic packaging industry, it is important to be able to make accurate predictions of board level solder joint reliability during thermal cycling exposures. The Anand viscoelastic constitutive model is often used to represent the material behavior of the solder in finite element simulations. This model is defined using nine material parameters, and the reliability prediction results are often highly sensitive to the Anand parameters.

In present work, three new doped lead free solder materials recommended for high reliability applications have been chemically analyzed and then mechanically tested in order to determine the nine Anand parameters. The alloys are referred to as Ecolloy (SAC_R), CYCLOMAX (SAC_Q), and Innolot by their vendors. The first two doped alloys (SAC_R and SAC_Q) were found to be composed of Sn, Ag, Cu, and a single X-element dopant. Such solders are commonly referred to as SAC-X in the literature. For the third material (Innolot), three different dopants are present along with Sn, Ag and Cu. The EDX method was used to determine the approximate chemical composition of the materials, and Bismuth (Bi) was found to be the X-additive for both SAC_R and SAC_Q. In addition, the SAC_R material was found to have no silver (Ag), which is the reason it is marketed as a low cost (economy) material.

The nine Anand parameters were determined for each unique solder alloy from a set of uniaxial tensile tests performed at several strain rates and temperatures. Testing conditions included strain rates of 0.001, 0.0001, and 0.00001 (sec−1), and temperatures of 25, 50, 75, 100, and 125 C. The Anand parameters were calculated from each set of stress-strain data using an established procedure that is described in detail in the paper. The mechanical properties and the values of Anand parameters for these new doped alloys were compared with those for standard SAC105 and SAC405 lead free alloys.

Although the SAC_R material does not have any silver, it was shown to have better mechanical behavior than SAC105 due to the presence of Bismuth (Bi) along with a little higher percentage of Copper (Cu). The SAC_Q and Innolot materials were shown to have significantly higher strength than SAC405. After deriving the Anand parameters for each alloy, the stress-strain curves have been calculated for various conditions, and excellent agreement was found between the predicted results and experimental stress-strain curves.

Topics: Solders
Commentary by Dr. Valentin Fuster
2015;():V002T01A004. doi:10.1115/IPACK2015-48638.

Decapsulation is one of the very powerful technique in failure analysis process. During this process, die and first level interconnects are exposed by dissolving molding compound around them using variety of methods. Typically decapsulation formulation uses red fuming nitric acid at elevated temperatures. This technique work for traditional Gold wire bonds, but does not work for its new alternative Copper. Gold, being inert metal does not react with acid. Copper on the other hand; tends to react with fuming nitric acid, and dissolves rapidly into acid. It is important to develop acid chemistry that can be successfully used to perform decapsulation of Cu-Al incorporated packages for different EMC’s.

In this paper, decap process based on combination of red fuming nitric acid and concentrated sulfuric acid at elevated temperatures is presented. Reduction in wire diameter was monitored for all devices. For some devices decap process was evaluated based on comparison of WB shear strength of decaped part with unmolded part. SEM was used extensively to track down degradation of copper wires. These tests were performed on packages with different EMC’s, wire diameters, pad thickness and some active dies.

Statistical principal components regression model has been developed correlating the decapsulation process parameters with the post decap wire diameter reduction. Principal component regression in conjunction with stepwise regression has been used to identify the influential variables, and to remove the multicollinearity between the predictor variables. Principal component analysis which combines two correlated variables into a single factor is a widely used image processing technique for pattern recognition and image compression. The post molded packages have then used to assess the effect of various decapsulation treatments.

Topics: Copper , Aluminum
Commentary by Dr. Valentin Fuster
2015;():V002T01A005. doi:10.1115/IPACK2015-48708.

This study focuses on the mechanical properties of two kinds of solders for high temperature interconnections (melting temperature above 280 °C after reflow). They are both lead-rich solders in wire form: 93.5Pb/5Sn/1.5Ag and 92.5Pb/5Sn/2.5Ag. The mechanical constitutive tests conducted in this study include: (i) monotonic elastic-plastic stress-strain response at constant strain rates and constant temperatures; and (ii) isothermal, viscoplastic creep strain response at several constant stress levels and different temperatures. The sensitivities of the material viscoplastic constitutive response to temperature, loading rate and stress level were systematically studied, so that the mechanical performance of these two solders could be compared with those of other solders, at similar test conditions. Both the Pb-rich solders studied had statistically similar behavior at the tested stress levels and temperatures in creep tests. The Ramberg-Osgood model and the Garofalo model were used to represent the elastic-plastic and creep behavior, respectively, of each solder and the corresponding model constants are presented in the paper.

Commentary by Dr. Valentin Fuster
2015;():V002T01A006. doi:10.1115/IPACK2015-48710.

A multiscale modeling framework is proposed in this study to capture the influence of the inherent elastic anisotropy of single crystal Sn and the inherent heterogeneous microstructure of a single crystal SnAgCu (SAC) solder grain on the secondary creep response of the grain. The modeling framework treats the SAC microstructure as having several distinct length scales. The smallest length scale (Tier 0) consists of the Sn BCT lattice. The eutectic Sn-Ag micro-constituent, consisting of nanoscale Ag3Sn IMC particles embedded in the single crystal BCT Sn matrix, is termed Tier 1. The single-crystal SAC microstructure, consisting of Sn dendrites and surrounding eutectic Sn-Ag phase, is termed Tier 2. Dislocation recovery mechanisms, such as Orowan climb and detachment from nanoscale Ag3Sn particles, are found to be the rate controlling mechanisms for creep deformation in the eutectic Sn-Ag phase (Tier 1) of a SAC single crystal. The anisotropic secondary creep rate of eutectic Sn-Ag phase (Tier 1), is then modeled using the above inputs and the saturated dislocation density calculated for dominant glide systems during secondary stage of creep. Saturated dislocation density is estimated as the equilibrium saturation between three competing processes: (1) dislocation generation; (2) dislocation impediment caused by back stress from pinning of dislocations at IMCs; and (3) dislocation recovery due to climb/detachment from IMCs. Secondary creep strain rate of eutectic Sn-Ag phase in three most facile slip systems is calculated and compared against the isotropic prediction. At low stress level secondary steady state creep rate along (110)[001] system is predicted to be ten times the creep rate along (100)[0-11] system. However, at high stress level, secondary steady state creep rate along (110)[001] system is predicted to be ten thousand times the creep rate along (100)[0-11] system. The above predictions are in strong agreement with (1–4) orders of magnitude of anisotropy observed in steady state secondary creep response in SAC305 solder joints tested under identical loading conditions in experiments conducted by several authors. The above model is then combined with Eigen-strain methods and average matrix stress concepts to homogenize the load sharing between the Sn dendrites and the surrounding eutectic Ag-Sn matrix. The resulting steady state creep rates are predicted for a few discrete single crystal SAC305 specimens. Very good agreement is observed between the predicted steady state creep rate and the measured creep rates for two SAC305 single crystal specimens.

Commentary by Dr. Valentin Fuster

Advanced Electronics and Photonics, Packaging Materials and Processing: Novel Modeling, Test and Characterization Methods

2015;():V002T01A007. doi:10.1115/IPACK2015-48594.

Design of new antenna mount with low effective projected area (EPA) and high load carrying capacity for telecommunication towers is discussed in this paper. The main aim is to reduce the EPA of the mount against the wind pressure direction at the desired elevation from ground by reducing the mount frame structure parts compared to the previous mount designs used in the market. The model in itself has to withstand its dead weight, operator’s weight along with five antenna-radio units. The new model has been designed with a single horizontal frame and four supporting structure for EPA reduction and also the EPA is calculated through Image Processing using MATLAB tool which has not been done previously for mounting structures in the telecommunication field. The preliminary stress and deformation results calculated using ANSYS 15.0 tool and future work that has to be carried out for the design are also discussed in this paper.

Topics: Design
Commentary by Dr. Valentin Fuster
2015;():V002T01A008. doi:10.1115/IPACK2015-48623.

In the current study, we have extended our previous work on nanoindentation of joints to examine a full test matrix of SAC solder alloys. The effects of silver content on SAC solder aging has been evaluated by testing joints from SACN05 (SAC105, SAC205, SAC305, and SAC405) test boards assembled with the same reflow profile. In all cases, the tested joints were extracted from 14 × 14 mm PBGA assemblies (0.8 mm ball pitch, 0.46 mm ball diameter) that are part of the iNEMI Characterization of Pb-Free Alloy Alternatives Project (16 different solder joint alloys available). After extraction, the joints were subjected to various aging conditions (0 to 12 months of aging at T = 125 C), and then tested via nanoindentation techniques to evaluate the stress-strain and creep behavior of the four aged SAC solder alloy materials at the joint scale.

The observed aging effects in the SACN05 solder joints have been quantified and correlated with the magnitudes observed in tensile testing of miniature bulk specimens performed in prior studies. The results show that the aging induced degradations of the mechanical properties (modulus, hardness) in the SAC joints were of similar order (30–40%) as those seen previously in the testing of larger “bulk” uniaxial solder specimens. The creep rates of the various tested SACN05 joints were found to increase by 8–50X due to aging. These degradations, while significant, were much less than those observed in larger bulk solder uniaxial tensile specimens with several hundred grains, where the increases ranged from 200X to 10000X for the various SACN05 alloys. Additional testing has been performed on very small tensile specimens with approximately 10 grains, and the aging-induced creep rate degradations found in these specimens were on the same order of magnitude as those observed in the single grain joints. Thus, the lack of the grain boundary sliding creep mechanism in the single grain joints is an important factor in avoiding the extremely large creep rate degradations (up to 10,000X) occurring in larger bulk SAC samples. All of the aging effects observed in the SACN05 joints were found to be exacerbated as the silver content in the alloy was reduced. In addition, the test results for all of the alloys show that the elastic, plastic, and creep properties of the solder joints and their sensitivities to aging are highly dependent on the crystal orientation.

Due to the variety of crystal orientations realized during solidification, it was important to identify the grain structure and crystal orientations in the tested joints. Cross-polarized light microscopy and Electron Back Scattered Diffraction (EBSD) techniques have been utilized for this purpose. The test results show that the elastic, plastic, and creep properties of the solder joints and their sensitivities to aging are highly dependent on the crystal orientation. In addition, an approach has been developed to predict tensile creep strain rates for low stress levels using nanoindentation creep data measured at very high compressive stress levels.

Topics: Silver , Solder joints
Commentary by Dr. Valentin Fuster
2015;():V002T01A009. doi:10.1115/IPACK2015-48653.

Due to its superior mechanical and electrical properties, as well as low cost, Cu is gradually replacing Au as wire bonding material. However, since copper is a stiffer material, it requires greater bonding force, which in turn increases risk of bond pad cratering and inter-layer dielectric (ILD) fracture. A critical challenge to numerically modeling the pad cratering or ILD fracture is the availability of appropriate constitutive models for the Cu free-air balls (FAB). In this work we first present rate and temperature dependent force-displacement response of micron-sized Cu FAB characterized using a custom-built high-precision microtester. From the experimental force-displacement data, Anand viscoplastic constitutive model parameters are obtained using an inverse finite element analysis procedure, where the material parameters are iterated through an automated procedure until the finite element and experimental force-displacement responses match. The constitutive model parameters to describe the FAB behavior at low and intermediate strain rates and at high temperatures are obtained and reported in this paper.

Commentary by Dr. Valentin Fuster
2015;():V002T01A010. doi:10.1115/IPACK2015-48727.

Electronics in high reliability applications may be subjected to cyclic thermo-mechanical loads after being deployed for extended periods of time in harsh environment. Cyclic thermal excursion may result in solder joint fatigue leading to failure. Previous researchers have shown that exposure to high temperature for extended periods of time results in evolution of the mechanical properties of SnAgCu alloys. Deployment of leadfree electronics in harsh environment applications may result in exposure to a multitude of thermal cycles. The effect of cyclic thermal range and thermal aging on the thermal fatigue reliability has been widely documented; however the effect of the mean temperature on the thermal fatigue reliability and the strain evolution of during cyclic exposure has not been studied. In this paper, an experimental investigation has been undertaken using digital image correlation to quantify the evolution in the strain state under different mean temperatures and cyclic thermal intervals. Three different test vehicles, BGA 144, 256 and 324 were used in this study under three different test conditions 50–150°C, 0–100°C and −50–50°C. A framework to evaluate the effect of mean temperature of thermal cycle has been developed.

Commentary by Dr. Valentin Fuster
2015;():V002T01A011. doi:10.1115/IPACK2015-48785.

A high-power LED can generate tremendous heat under the operation, which causes the LED chip undergo large deformation. LED Wire Bonds may undergo deformation because of the mismatch between the LED chip and substrate. Presently, measurements of deformation and strain in operational electronics are limited to measurement on a cut-plane using techniques including digital image correlation and moiré interferometry based techniques. There is need for tools and techniques that can help quantify the in-situ chip deformation and interconnects inside the LED. Digital Volume Correlation (DVC) has been used in conjunction with X-ray Micro-CT for three-dimensional measurement of deformation and strain in LEDs under operational stresses. The Digital Volume Correlation has been used to correlate the undeformed image with deformed images by computing correlation functions throughout each voxel. The deformed images have been generated by CT scanning over the object while the LED is operational. The correlation function computation starts at specific fixed subset window in the reference image, and searches every possible subset window in the deformed image to identify the deformation in the electronic structure. Once the displacement components have been derived, the strain components have been computed by calculating the gradients of the displacement field. In this paper, the full strain field, both in-plane and out-plane strain, will be presented, and the LED chip deformation shape will be analyzed.

Commentary by Dr. Valentin Fuster

Advanced Electronics and Photonics, Packaging Materials and Processing: Overmold Compounds, Adhesives, Underfills, Seals, Thermal Interface and Heat Spreader Materials

2015;():V002T01A012. doi:10.1115/IPACK2015-48447.

As the microelectronics industry continues to advance the boundaries of size and performance, focus on the impact of systems packaging has risen to the forefront of design and material considerations. As interfaces are often constructed of multiple heterogeneous layers, interfacial delamination is an important failure mechanism to consider in microelectronic packaging. This failure is due to, among other factors, the stresses arising from high mismatches in coefficient of thermal expansion (CTE). Most work to date has focused on interfacial crack propagation under monotonic loading that is incurred during fabrication steps such as deposition or curing which occur at elevated temperatures and subsequent cooling to room temperature. This is an important design consideration but it is not sufficient as the operational life of these devices involve high numbers of heating and cooling cycles which result in crack propagation under fatigue loading. As such the study of fatigue effects on these interfaces is paramount to improving the lifetime of microelectronic devices as the field pushes towards both thinner and wider packages.

One such exploration, which is the subject of this work, is to determine the interface incremental crack growth rate as it relates to cyclic loading. In this work, double cantilever beam (DCB) tests are performed at various stress ratios on samples with epoxy mold compound (EMC) atop a copper leadframe. For these tests, force versus displacement curves will be obtained. Given the small dimensions of the interfaces in question, it is desirable to develop a test methodology that does not require in-situ measurement of crack length. Thus, in these tests the compliance of the samples is determined from the force versus displacement curves and used to infer the progress of the crack through an indirect approach. The advantage of this method is that it does not require the observational measurement of the crack length potentially allowing crack monitoring absent any optical or imaging methods. Using the determined crack propagation rate with fatigue cycle under various loading conditions, a generalized fatigue crack propagation model will be developed for mold compound and copper interface, and such a model can be employed to assess packaging reliability in operating conditions.

Commentary by Dr. Valentin Fuster
2015;():V002T01A013. doi:10.1115/IPACK2015-48622.

Microelectronic encapsulants exhibit evolving properties that change significantly with environmental exposures such as isothermal aging and high humidity conditions. In this work, the material behavior changes occurring in underfill materials subjected to moisture exposures in an humidity chamber have been characterized using 60 × 3 × 0.5 mm uniaxial test specimens which were cured with production equipment using the same conditions as those used in actual flip chip assembly. After curing, the samples were divided into two groups and subjected to different preconditioning: (1) no preconditioning, (2) prebaking at 85 C for 24 hours. The fabricated and preconditioned uniaxial test specimens were then exposed in an adjustable thermal and humidity chamber to combined hygrothermal exposures at 85 C and 85% RH for various durations (0, 1, 3, 10, 30, 60 days). After the moisture exposures, a microscale tension-torsion testing machine was used to evaluate the complete stress-strain behavior of the material at room temperature (25 C). In addition, the viscoelastic mechanical response of the underfill encapsulant has also been characterized via creep testing at room temperature for several applied stress levels after the moisture exposures. From the recorded results, it was found that the moisture exposures strongly degrade the mechanical properties of the tested underfill including the initial elastic modulus, ultimate tensile stress, and tensile creep rate. Prebaking was found to increase the initial material properties, but the degradations due to subsequent moisture exposures occurred in a similar manner.

Commentary by Dr. Valentin Fuster
2015;():V002T01A014. doi:10.1115/IPACK2015-48712.

Highly filled thermally conductive silicone gels are routinely used as first level thermal interface materials (TIMs) between the die and lid, in flip-chip organic packages. The main challenge for these TIMs is overcoming the Coefficient of Thermal Expansion (CTE) mismatch between the die and lid materials. The TIMs must maintain excellent adhesion to both the die and lid surfaces in order to achieve and maintain optimal thermal performance. The CTE mismatch leads to increased mechanical stress and degradation of the TIM, which in turn degrades the thermal performance. In this work, the effective modulus of several TIMs was calculated by finite element modeling (FEM) in concert with mechanical testing of thin bond-line aluminum-TIM sandwiches subjected to varied stress conditions. These results are correlated to the corresponding stress die shear testing and the impact on package performance is analyzed.

Commentary by Dr. Valentin Fuster
2015;():V002T01A015. doi:10.1115/IPACK2015-48738.

Three dimensional integrated circuits (3D-IC) have been proposed for the purpose of low power and high performance in recent years. Pre-applied inter chip fill is required for fine pitch interconnections, large chips, and also thin chips. In addition to them, pre-applied joining process with high thermal conductive inter chip fill (HT-ICF) is strongly required for the cooling of 3D-IC. Some kinds of matrix resins and thermal conductive fillers were simulated and evaluated for pre-applied ICF. As a result, matrix and cure agent appeared to be important to both pre-applied ICF process compatibility and thermal conductivity, so that we’d selected epoxy type matrix based on controlling super molecular structure due to its mesogen unit. And not only matrix but also filler appeared to be the key to improve thermal conductivity for pre-applied ICF at the same time. The thermal conductivity of conventional silica filler was only 1W/mK, so that, taking into account of thermal conductivity, density and its stability, we’d selected aluminum oxide and boron nitride as thermal conductive filler and optimized HT-ICF for pre-applied process. After composite was mixed and cured, some physical properties were measured and thermal conductivity was 1.8W/mK, CTE was below 21ppm/K and Tg was 120°C. Furthermore, new high thermal conductive filler was also studied. We’d synthesized completely new spherical BN (diameter <5um) and applied it to HT-ICF and the thermal conductivity was almost two times higher than conventional BN. In this study, we confirmed ICF physical characteristics and its pre-applied joining for 3D-IC and void-less joining was also discussed.

Topics: Joining
Commentary by Dr. Valentin Fuster
2015;():V002T01A016. doi:10.1115/IPACK2015-48741.

Coefficient of thermal expansion (CTE) characteristic of organic materials for substrates in flip chip package application demanded by semiconductor package requirements is becoming lower than ever. In general, height restrictions are imposed on package-on-package (PoP) devices in mobile applications. One should hence establish a tight budget on the height variation in manufacturing of the devices. Given such background, a lowering of the CTE characteristic of package substrates is an attractive solution for reducing package deformation upon manufacturing, since it contributes to minimize CTE mismatch of the substrates with silicon chips. In large-die flip chip applications such as high-end processors, a lower CTE substrate can mitigate mechanical stress not only on low-k layers in back end of the line (BEOL) underneath the chip bumps, but also on underfill layers during thermal cycling. Therefore an introduction of lower CTE materials in organic substrates is becoming essential for future applications of electronic devices. In this paper, thermal deformation behaviors of organic substrates associated with lowering of the CTEs of their constituent materials are analyzed by finite element analysis (FEA). The analyses are done on a 3-2-3 build-up layer structure substrate in order to focus onto typical application specific integrated circuit (ASIC) products. A finite element model for a test substrate is constructed by a method in which the substrate is divided into sections according to its circuitry patterns so that the lateral inhomogeneity of mechanical property is taken into account. The finite element analyses using the model showed that the package warpage decreases with lowering of the effective CTE of the substrate, but the warpage of the substrate itself increases and its surface profile changes from a concave shape to a convex shape. The analysis result of substrate warpage variation with the build-up material’s CTE showed that the selection of build-up materials with appropriate material properties can contribute to reduce the substrate warpage. The analysis also showed that the adverse impact to the substrate’s CTE reduction by such material selection is limited.

Commentary by Dr. Valentin Fuster

Advanced Electronics and Photonics, Packaging Materials and Processing: Wafer Finishing, Dicing and Bond and Assembly Development

2015;():V002T01A017. doi:10.1115/IPACK2015-48749.

Plasma dicing has rapidly gained traction as a viable alternative to conventional blade and laser techniques for wafer singulation. This has been due mostly to the significant benefits plasma dicing delivers in relation to the quality and reliability of devices singulated in this manner.

Key to the successful integration of plasma dicing, into the established hierarchy of singulation techniques, is how the ancillary parts of the process flow can be utilized or adapted to accommodate it. More importantly, is the ease at which this can happen and also, how implementation can be achieved in a cost effective manner.

Commentary by Dr. Valentin Fuster
2015;():V002T01A018. doi:10.1115/IPACK2015-48836.

The thinner and higher density PKG (package) is being required strongly for the growth of smaller mobile devices. Especially, package on package technology (PoP) has become a mainstream for application processors which are installed in smartphones and tablets.

However, the warpage of thinner PKG often causes a problem at the chip mounting process. The main factor of warpage is the mismatch of CTE (coefficient of thermal expansion) between substrate and chip. Therefore, the lower CTE core materials are needed for the thinner PKG.

Recently, Hitachi Chemical has developed the super-low CTE material, core and prepreg, applying our new resin system and filler treatment technology, and placed it on the market. Furthermore, a super-low CTE material of 0.7 ppm/K is currently under development. The super-low CTE material shows the best warpage performance in our low CTE core material lineups, maintaining its higher Tg, high modulus and low Dk/Df values.

Commentary by Dr. Valentin Fuster

Advanced Electronics and Photonics: Packaging, Interconnect and Reliability: Advances in 2.5D, 3D and Stacked Packaging

2015;():V002T02A001. doi:10.1115/IPACK2015-48088.

2.5-D package with through silicon vias (TSVs) on interposer has been envisioned as the most viable way in heterogeneous integration. In this work, several design approaches are considered in the thermal analysis and enhancements of a 2.5-D package with multi chips on through silicon interposer (TSI), which include overmolding materials, metal slug, lid attachment, pin fin heat sink and fan-driven heat sink cooling. The analysis models consist of two dummy flip chips on a silicon interposer to represent the logic die and memory die, respectively. Package submodels, especially the TSV ones, are analyzed with good modeling accuracy. Package thermal modeling indicates that the thermal conductivity of the epoxy overmolding has minimal effect on the thermal performance of copper slug package. Lid attachment further enhances the thermal performance through peripheral substrate attachment. Both designs largely rely on thermally conductive PCB (4L) to maximize power dissipation. Pin-fin heat sink, made of aluminum, can be mounted on the package top to further minimize thermal resistance and extend the power dissipation beyond 10W. For high power application, fan cooled heat sink is used to reduce excessive heat. Copper based aluminum heat sink can remove the heat of 120W from the bare-die package. Self heating due to high current density through the TSV is analyzed. The proposed analytical expression gives good prediction on the local TSV hot spot. It is demonstrated that a distributed TSV network design provides lower temperature rise, which shall have lower risk of failures and is preferred in practice.

Topics: Design
Commentary by Dr. Valentin Fuster
2015;():V002T02A002. doi:10.1115/IPACK2015-48124.

In conjunction with micro bumps, Through-Silicon-Vias (TSVs) are used for die stacking, leading to reduced footprints and a higher performance due to shorter communication bus-length. However the large difference between the thermal expansion of silicon and copper and an increased temperature of the die stack due to Joule heating lead to shear stress at the interface between TSV and substrate. Temperature activated interfacial diffusion in combination with the shear stress leads to diffusional interfacial sliding, resulting in TSV pro- or intrusion. In addition, electromigration (EM) at the interface leads to TSV motion.

Against this background the protrusion/intrusion of Cu TSVs (ø 10 μm, length 100 μm) during fast and slow rate thermal cycling (TC) and during EM experiments was investigated.

Parallel to the experimental investigation a finite element analysis (FEA) was performed to study the micro-mechanical responses of Cu-filled TSV during thermal cycling. For this purpose interfacial sliding was incorporated into the FE model by diffusional creep mechanism. The FE model captures the main features being observed in experiments such as stress hysteresis and intrusion/protrusion of the TSV relative to Si substrate.

Topics: Reliability , Silicon
Commentary by Dr. Valentin Fuster
2015;():V002T02A003. doi:10.1115/IPACK2015-48125.

Solder micro-bumps, which serve as interconnects between stacked dies in 3D electronic packages, are typically very thin (25μm or less) and contain a high proportion of intermetallic compounds (IMCs). This makes micro-bumps brittle, and prone to fracture, particularly under drop conditions. In this paper, the fracture mechanics and mechanisms of SAC305 solder micro-bumps attached to Cu metallizations are studied as functions of the proportion of IMC in the joint. The effects of IMC content, IMC composition (i.e., the relative amounts of Cu3Sn and Cu6Sn5), strain rate, and mode mixity on both fracture toughness and fracture mechanism were investigated. The fracture mechanisms were studied via quantitative fractography. It was found that fracture toughness decreases dramatically (∼80%) with increase in IMC content (from ∼22% to 100%IMC). In all samples, the majority of the fracture surface comprised IMC/Sn interface failure, which constitutes the predominant fracture mechanism. With increasing aging, the proportion of ductile fracture of Sn decreases, fracture through Cu6Sn5 cleavage increases, and more Cu3Sn/Cu6Sn5 interface failure is observed. In general, bulk fracture properties of Cu3Sn plays little role in the fracture process. Thin joints also frequently display an alternating crack path between the two solder-substrate interfaces with the crack transitioning from one interface to the other, through the intervening Sn. Such crack transition between two surfaces increases with increase in IMC content, as long as there is intervening Sn, and may be utilized to improve the fracture toughness of thin joints. Finally, joint fracture toughness decreased with increase in both strain rate and mode mixity.

Commentary by Dr. Valentin Fuster
2015;():V002T02A004. doi:10.1115/IPACK2015-48168.

The mechanical reliability of electronic packages is one of the critical problems in the reliability of electronic products in general. Estimating the warpage of an electronic package is useful for increasing its mechanical reliability. The warpage of an electronic package often shows a hysteresis curve during a thermal cycle. However, this hysteresis is difficult to simulate. We measured the master curves of the relaxation modulus using a Dynamic Mechanical Analyzer (DMA) before and after the first heating. Measured equilibrium elastic modulus after heating was two times higher than before heating. Curing rate of the resin before heating was already more than 99%. Change of elastic modulus in the range over 99% curing rate was much stronger than expected according to the conventional theory of rheology. We then analyzed the warpage of the specimen considering the change in the master curve of the relaxation modulus of the underfill resin. The hysteresis of the warpage of the bonded specimen was successfully predicted using the proposed method. In this study, we extended this method to a package on package (PoP). The PoP package also showed temperature hysteresis of the warpage. We considered the same viscoelastic material properties for the underfill resin. We also took the multi layered print circuit board and the viscoelastic material properties of solder resist into account. Simulated thermal hysteresis of the warpage of a PoP successfully corresponded with the measured warpage.

Commentary by Dr. Valentin Fuster
2015;():V002T02A005. doi:10.1115/IPACK2015-48197.

Electroplated copper thin films are indispensable for the interconnections in the advanced electronic products, such as TSV (trough silicon via) structures, fine bumps, and thin-film interconnections in various devices and interposers. However, it has been reported that both electrical and mechanical properties of the films vary drastically comparing with those of conventional bulk copper. The main reason for the variation can be attributed to the fluctuation of the crystallinity of grains and grain boundaries in the films. Porous or sparse grain boundaries cause the increase in electrical resistivity and the embrittlement of the films. Thus, the thermal conductivity of the electroplated copper thin films should be varied drastically depending on their micro texture based on Wiedemann-Franz law. Since copper interconnections are used for not only electrical conductor but also thermal heat conductor, it is important to clarify the relationship between the crystallinity and thermal properties of the films.

In this study, the local distributions of the crystallinity and physical properties were investigated experimentally. As the result of the temperature distribution due to local Joule heating along an interconnection, it was suggested that the variation in the quality of the grain boundaries in the electroplated copper thin-films caused the non-uniformity of the resistivity and thus, Joule heating in the thin films. In this study, the effect of the seed layer material on the thermal properties of the electroplated copper thin film was investigated. When a Ru seed layer was deposited as a buffer layer between the electroplated copper thin film and the Ta diffusion barrier layer, both the crystallinity and uniformity of grain boundaries in the electroplated copper films were improved since lattice mismatch between copper and the seed layer metal was decreased. The improvement of the crystallinity increased the long-term reliability of the interconnections under the loads of electromigration and stress-induced migration.

Commentary by Dr. Valentin Fuster
2015;():V002T02A006. doi:10.1115/IPACK2015-48200.

Electroplated copper thin films have started to be employed as the interconnection material in TSV structures of 3D semiconductor modules because of its low electric resistivity and high thermal conductivity. However, electrical and mechanical properties of electroplated copper thin-films have been found to vary drastically depending on their microtexture. In particular, the crystallographic quality (crystallinity) of grain boundaries in the electroplated copper thin-films plays an important role on the variations of these properties and the long-term reliability of the interconnections. This is because grain boundaries are the area where the atomic alignment of mateerials is disordered and thus, various defects such as vacancies, dislocations, impurities, and strain easily concentrate around them. This disorder of the atomic alignment causes the increase in the electrical resistivity, diffusion constant along the grain boundaries, and the brittleness of the material. Therefore, it is very important to evaluate the characteristics of a grain boundary quantitatively in order to control and assure the properties of the electroplated copper thin films. In this study, a novel tensile test method that can measure the strength of a grain boundary has been developed by using a focused ion beam system. In order to investigate the effect of the crystallinity of grain boundaries on their strength, an electron back-scatter diffraction method (EBSD) was employed for the quantitative characterization of grain boundaries. It was confirmed that the strength of grain boundaries with low crystallinity was much lower than that with high crystallinity.

Commentary by Dr. Valentin Fuster
2015;():V002T02A007. doi:10.1115/IPACK2015-48387.

During the fabrications of 2.5D and 3D advanced packages, the needs for intermediate thinning and planarization processes persistently exit. This paper highlights the attributes of successful implementations, i.e., increased performances and yields for these processes, which have been identified by the market requirements for a variety of applications. Different packages with different materials systems and product goals lead to different requirements. This paper includes the thinning and polishing of TSV wafers in bonded wafer pairs for Si IC devicess or interposers, the thinning of overmolded, reconstituted wafers in eWLB applications, and the planarizations of metal bumps and RDL features in PoP, CSP, or fine line-and-space (L/S) substrate fabrications.

Commentary by Dr. Valentin Fuster
2015;():V002T02A008. doi:10.1115/IPACK2015-48656.

Through-Silicon Vias are a key enabler of 3D technology and reliability of these structures is a source of concern. TSVs are typically made of copper and therefore have a large CTE mismatch with the surrounding Si. When subjected to a thermal load during BEOL processing, they experience stress and deform. An important reliability concern that the stress poses is the debonding of the TSV-Si interface, and has been observed experimentally. A possible reason for the debonding is the high interfacial shear stress which could potentially be singular. The authors have obtained analytical estimates of the far-field stress and protrusion in a prior work. In this work the stress singularity at the tip of the TSV-Si interface is obtained. The order of the singularity is correlated to the risk of interfacial delamination.

Topics: Risk , Shear stress
Commentary by Dr. Valentin Fuster
2015;():V002T02A009. doi:10.1115/IPACK2015-48811.

The convergence and miniaturization of computing and communications dictates building up rather than out. As planar device miniaturization continues to its ultimate limits, the complexity of circuit interconnections for 2-D devices becomes a limitation for performance and drives up power dissipation [1]. As the consumers demand more functions on their hand-held electronic devices, the need for more devices such as memory, CPU and GPU in hand-held type footprints is increasing. Chip-stacking (3-D) is emerging as a powerful tool that satiates such IC package requirements. A 3-D FPGA would overcome the interconnect limitations, resulting in greater silicon efficiency per function (number of used gates/total number of gates), faster signal/data throughput, and faster switching of the gate-level configuration. 3-D through-silicon-via (TSV) technology is being termed as the “next big thing” in the semiconductor arena and has the potential of revolutionizing the packaging industry but it has some inherent issues that need to be addressed before it could be implemented in the mainstream electronics industry. TSV fabrication process, thermal management of 3-D TSV packages, TSV joule heating, and chip package interaction (CPI), are some of the key issues in this technology [2, 3, 4, 5, 6].

In this paper, the thermo-mechanical chip-package-interaction (CPI) analysis is carried out and a full field compact 3D modeling methodology has been leveraged to assess the mechanical integrity of a 2 die 3D TSV package during attachment to substrate. This modeling methodology would provide damage predictions caused due to global and local CTE mismatch between the different package components. Mechanical interaction at the Si/TSV regions, back-end Cu/low-k stack, and the inter die μ-bumps during chip attachment is demonstrated in this paper.

Commentary by Dr. Valentin Fuster

Advanced Electronics and Photonics: Packaging, Interconnect and Reliability: Advances in Interconnect Technologies

2015;():V002T02A010. doi:10.1115/IPACK2015-48136.

Solder joints are sometimes opened under thermal cyclic loads as low cycle fatigue phenomena. The fatigue crack is usually initiated around the edge of the interface where stress and strain very severely concentrate, having stress strain singularity. In this study, Sn-3.0Ag-0.5Cu test pieces with V shape notch were supplied to low cycle fatigue tests at 100°C. And inelastic stress strain simulations, which were based on time-dependent non-unified material model, were carried out under several cyclic load levels to obtain strain distributions around the bottom of the V notch. By results of fatigue test and inelastic simulation, the depth from the bottom of the V notch, where the strain range agrees with the prediction of the fatigue life based on smooth test pieces on Coffin-Manson rule, was investigated as the mechanical design rule for lead free solder joints.

Commentary by Dr. Valentin Fuster
2015;():V002T02A011. doi:10.1115/IPACK2015-48180.

The electronic hardware miniaturization trend continues unabated. The reduced feature spacing expose the high voltage power supply circuits to arcing. The power MOSFET gate to drain and the drain to source lead gaps are narrow enough for zinc whiskers emanating from under the raised floor zinc plated tiles to arc across the MOSFET leads. Arcing can also occur because of paper cellulose fibers and dust in high relative humidity environments. The physics of arcing will be presented. Paschen’s law of arcing will be described; it will be shown how the law led to a novel way of testing power supplies for propensity to arcing. Examples of application of the test, called the partial vacuum test, to power supplies will be described. Testing the integrity of conformal coating is one useful application of the partial vacuum test. A novel zinc whisker spray test, developed to determine the spacing required to avoid arcing between features at high electric potential between them, will be described and its results will be presented that verify the UL feature spacing guidelines.

Commentary by Dr. Valentin Fuster
2015;():V002T02A012. doi:10.1115/IPACK2015-48639.

The increasing price of gold has resulted in industry interest in use of copper as alternative wire bonds interconnect material. Copper wire has the advantages of the lower cost, lower thermal resistivity, lower electrical resistivity, higher mechanical strength and higher deformation stability over the gold wire. In spite of the upside above, the Cu-Al wire bond is susceptible to the electrolytic corrosion and the reliability of Cu-Al wire bond is of great concern. Typical electronic molding compounds are hydrophilic and absorb moisture when exposed to humid environmental conditions. EMC contain ionic contaminants including chloride ions as a result of the chemical synthesis of the subcomponents of the resin, etching of metallization and the decomposition of the die-attach glue. The presence of moisture in the operating environment of semiconductor package makes the ion more mobile in the EMC. The migration of chloride ions to the Cu-Al interface may induce electrolytic corrosion inside the package causing degradation of the bond interface resulting in eventual failure. The rate at which the corrosion happens in the microelectronic packages is dependent upon the rate at which the ions transport through the EMC in addition to the reaction rate at the interface. In this effort, a multiphysics model for electrolytic corrosion in the presence of chloride has been presented. The contaminant diffusion along with the corrosion kinetics has been modeled. In addition, contaminated samples with known concentration of KCl contaminant have been subjected to the temperature humidity conditions (130°C/100RH)The resistance of the Cu-Al interconnects in the PARR test have been monitored periodically using resistance spectroscopy. The diffusion coefficients of chloride ion at various temperatures in the molding compound have been measured using inductively coupled plasma. Measured diffusion coefficients have been incorporated into the COMSOL multiphysics model. Moisture ingress into the EMC has been quantified through measurements of the weight gain in the EMC. Predictions from the COMSOL multiphysics model have been correlated with experimental data.

Topics: Corrosion
Commentary by Dr. Valentin Fuster
2015;():V002T02A013. doi:10.1115/IPACK2015-48655.

Diffusion is an important mechanism for failure inducing phenomena in many applications. The common Pb-free solder alloys used in the current generation of electronics packages are complex multiphase multicomponent materials. As the scale of the solder joint decreases, it becomes increasingly important to account for the effect of surface phenomena such as grain boundary evolution, surface diffusion and interfacial reactions in the mechanics of the solder joints. The dynamics of these diffusion driven interfacial phenomena are affected by the state of stress and the electric current in the solid. The primary challenges to modeling the dynamics of evolution are the tracking of the interface while satisfying the boundary conditions for the bulk problem.

In previous work, the authors utilized the phase field method in conjunction with a commercial finite element code to study the effect of stress and electrical fields on the diffusion driven evolution of voids in solder interconnects. The utilization of commercial tools for the simulation of the stress, electrical and thermal fields allowed for the use of pre-existing meshes and allowed the study of electromigration failure in assemblies of solder joints. However, the use of commercial tools can be expensive and the options for parallel simulation are limited, restricting the size and complexity of the simulations.

In this work, the authors describe DiffCode, a parallel adaptive finite element code for three-Dimensional simulation of electromigration and stress migration driven failure due to void evolution and growth in solder as well as line interconnects using the phase field method. Several illustrative two-dimensional and three-dimensional electromigration driven void evolution simulations are demonstrated using the code.

Commentary by Dr. Valentin Fuster
2015;():V002T02A014. doi:10.1115/IPACK2015-48720.

In the present work two different types of case studies are modelled, carried out involving the fusing of a material using the CFD (Computational Fluid Dynamics) software Ansys Fluent, using the VOF method (Volume of Fluid) to capture the position of the existing interfaces and the Solidification/melting method which uses an enthalpy-porosity approach to simulate the fusion of the material.

The first case focus itself in the analysis of fusing process and dropping behavior of the melted plate in the presence of a thermal source. The validation is made using a study found in the bibliography and then using water as the melting material given that its behavior is well known. Then tin is used as the melting material followed by the use of SAC 405 as the melting plate. This study compares various materials properties and verifies the influence of some of these particular properties by changing them (surface tension and heat of fusion).

The second case focus on the simulation of a geometry obtained at balance at a constant temperature by the SAC 405 soldering alloy in the presence of a component and the copper substrate on top of a PCB.

Commentary by Dr. Valentin Fuster
2015;():V002T02A015. doi:10.1115/IPACK2015-48744.

The high current density induces electromigration (EM) in metal lines used for electric wirings in integrated circuits. The growth of voids formed by EM in the line material leads to the line failure. Recently, multilevel interconnections are widely used in the circuit in electronics devices and MEMS. Metal lines aligned on upper and lower layer are connecting through the vias in the multilevel interconnections. The reservoir structure is often constructed in the line structure to prevent the EM damages. There is a threshold current density relating to the EM damage of the lines in the interconnection with vias. It is important to evaluate the threshold value for determination of an allowable electric current of the line. In this study, a numerical simulation technique for analyzing the atomic density distributions in the line material under high current density was used to evaluate the EM risks of metal lines in the several cases of interconnect tree structure with reservoir. The thresholds of current density leading to EM damage were calculated in the simulations considering the reservoir locations and pattern of electric current flow in the tree.

Commentary by Dr. Valentin Fuster
2015;():V002T02A016. doi:10.1115/IPACK2015-48795.

This study investigates the effect of silver paste composition on reliability of sintered silver interconnections. The interconnections are formed between SMD 1206 chip jumpers and electroless nickel immersion gold (ENIG) coating of FR4 printed circuit board (PCB) solder pads. They are made of pastes that vary in their composition (various proportions of micro and nano particles). The sintering process was conducted in convective oven. After the process the interconnections were subjected to X-Ray inspection in order to characterize the structure of interconnections (presence of voids, total surface of interconnection etc.). During accelerated reliability tests the PCBs were subjected to combined temperature cycling and vibration loading. During the tests daisy chains of interconnections were connected to dedicated programmable multichannel event detector developed in LIPEC lab. The event detector is able to detect and store information about object condition based on the real-time resistance measurements and applied novel algorithm of event detection. Failure modes were confirmed by using X-Ray computed tomography. The paper presents results of comparative Weibull analysis.

Commentary by Dr. Valentin Fuster

Advanced Electronics and Photonics: Packaging, Interconnect and Reliability: Advances in Packaging

2015;():V002T02A017. doi:10.1115/IPACK2015-48105.

Recent electronic device packaging, for instance, CSP has a bonded structure of IC chip and polymers, and delamination occurs frequently at the interface between IC and a resin. Furthermore, thermal stresses which are caused by a temperature variation in the bonding process of CSP and heat cycles for environment temperature will influence on the strength of interface. In the present paper, the delamination test for specimens with different thicknesses of an interlayer is carried out to investigate the strength of multi-layered joints, and the critical value for the intensity of singularity at delamination of interface is determined through a numerical analysis using a boundary element analysis. In experiment, a silicon wafer is joined with a silicon-on-sapphire (SOS) plate by a resin. The SOS is composed of silicon film and sapphire plate. The joining strength in silicon, resin and SOS joints with a rectangular bonding area is investigated. The bonded specimens are prepared under different cooling rate. Load is applied to the specimen so as to delaminate at the interfaces of silicon film and sapphire. Delamination occurs at the interface between silicon film and sapphire plate in the specimen. Nominal stress for delamination is about 2.23–3.59 MPa. From a comparison of the strength of joint for rapid and slow cooling conditions, it is found that the residual stress reduces the strength of joint. In the numerical analysis, the intensity of singularity at the corner of interface for a unit load is determined. The intensity of singularity at the corner of the interface is related to the intensities of singularity in the radial direction and on the angle from the side free surface. The critical intensity of singularity for delamination of the interface is obtained by multiplying the force at delamination. Then, the critical intensity of singularity is determined as 168 MPa•mm0.18 regardless of the thickness of silicon film.

Commentary by Dr. Valentin Fuster
2015;():V002T02A018. doi:10.1115/IPACK2015-48111.

A numerical analysis using Finite Element Models of different stress buffer configurations has been proposed for improving the reliability of solder joints and at the same time decrease the induced stresses in the back-end-of-line (BEOL). A non-underfilled Flip Chip with a silicon die size of 10×10 mm2 mounted on a FR4 board has been used as test vehicle. The die to substrate interconnection is done by using copper pillars and Sn solder with a diameter of 50 μm and a total standoff of 50 μm. The thickness of the passivation, a copper pedestal fabricated as a redistribution I/O pad and a polymeric buffer layer with different geometric configurations were used in combination to minimize the induced stresses in the BEOL and increase the flexibility of the copper pillar interconnections. It was found that a stiff layer below the copper pillar has the major contribution to reduce the stress in the BEOL, while the softer buffer layer minimizes the induced plastic strain in the solder interconnection. Fabrication of the samples with optimal configuration are under progress.

Commentary by Dr. Valentin Fuster
2015;():V002T02A019. doi:10.1115/IPACK2015-48138.

Sn-Ag-Cu solder materials have been widely used for the mount process of electronics devices or semiconductor packages on print circuit board (PCB). The solder joints are sometimes opened under thermal cyclic loads as low cycle fatigue phenomenon. The fatigue life of solder joint has been investigated by many researchers with experimental and numerical methods. Generally, the induced thermal stress in solder joints should be relaxed as soon and creep damage is considered to be ignored in order to estimate lives of joints. However, it is probable that long term stress is applied to solder joints by the elastic follow-up phenomenon which are depending on the stiffness ratio between solder joints and the electronics device, because the elastic strain in PCB or the electronics device shifts to creep strain in solder joints gradually during a long time. Then the creep damage of solder joint should be counted for the mechanical design of mounted PCBs. And it is known that the interaction between creep damage and fatigue damage significantly shorten the life. In this study, it was discussed whether the interaction between fatigue damage and creep damage has to be considered or not for the mechanical design of the lead free solder joint with basic creep-fatigue tests at an elevated temperature.

Commentary by Dr. Valentin Fuster
2015;():V002T02A020. doi:10.1115/IPACK2015-48142.

3D packaging technology and TSV (Through Silicon Via) technology have been developed to reduce size and improve performance of semiconductor devices. On the other hand, cooling performance is decreased because thermal sources are accumulated and concentrated by chip stacking. In particular, unsteady thermal loads by hot spot, which is steep temperature elevation within a local area, produce damage in stacked semiconductor chips. In this study, temperature elevation in stacked chips and stresses around TSV structure in 3D SiP (Three Dimensional System in Package) are discussed with a large scale and a parallel computing simulator, which was based on FEM (Finite Element Method), under unsteady thermal conditions as hot spot. The level of heat generation was varied and conditions for device operation were suggested. In addition, stresses of Cu-TSV and Si chips are discussed as function of level of heat generation by hot spot to ensure the reliability of 3D SiP.

Commentary by Dr. Valentin Fuster
2015;():V002T02A021. doi:10.1115/IPACK2015-48155.

Due to world wide Pb-free regulation for electroplated tin, whisker formation has returned as a long term reliability problem for tin coated electronic components. In addition the exact mechanism(s) responsible for Sn whisker growth mitigation by Pb were never clearly indentified, which makes the search for an replacement of Pb a difficult process. In this work the effects of In doping on tin whisker growth were investigated. In order to maintain Sn as a single phase material only small additions of In were incorporated, approximately 5–10 wt.% In. Indium was incorporated into Sn using a 100 nm over-plate of In on 1 μm thick Sn followed by heat treatments at 125°C and 160°C to permit diffusion of In into Sn. Control samples of pure Sn in the as-plated as well as 125 C heat treated conditions were also used. Whisker density results show a dramatic decrease of almost two orders of magnitude for the 160°C HT Sn-In sample. This is a new result in whisker mitigation studies, and we interpret it as a real effect of In, although further verification including the use of control samples are required. The segregation of dopants at the grain boundaries (GB) of tin, which might lead to reduced self diffusion of Sn, was investigated by performing molecular dynamic (MD) simulations on randomly added Pb atoms. Segregation of Pb clusters to GB was observed. While simulations with In dopant has not been conducted as yet, nevertheless such segregation may be one of several mechanisms responsible for the In effect.

Commentary by Dr. Valentin Fuster
2015;():V002T02A022. doi:10.1115/IPACK2015-48247.

The Cu through-hole is a structure of electroplated Cu thin film, which penetrates the substrate. Because of the mismatch of the thermal expansion coefficient between the Cu thin film and the substrate along the thickness direction, thermal strain occurs repeatedly at the Cu through-hole part with the variation of temperature. As a result, the thermal fatigue failure of Cu through-hole part is one of the failure modes of the substrate. In this study, the effects of thermal cycle conditions on the thermal fatigue life of the substrate with Cu through-hole were investigated by thermal cycle tests and Finite Element Method (FEM)-based analyses. Thermal cycle tests of the substrate with Cu through-hole were conducted under different thermal conditions. The effects of dwell time, temperature range and maximum temperature were investigated. Among these factors, the maximum temperature shows the greatest influence on the thermal fatigue life of Cu through-hole part. FEM-based thermal cycle analyses were also carried out to understand the effects of thermal cycle conditions. The glass cloth structures of the substrate should be considered in the analyses, because their rigid properties probably affect the generation of the failure at the through-hole part. In this study, glass cloth structures were modeled by taking advantage of a homogenization method. On the other hand, the inelastic constitutive model of the electroplated Cu thin film was introduced in the analyses in order to describe the creep deformation during the dwell process of thermal cycles. The inelastic strain range of the Cu through-hole during thermal cycles was calculated from the analysis results and the effectiveness of the Coffin-Manson law was evaluated. The results showed that the fatigue life prediction using the Coffin-Manson model was effective in the range of the same substrate thickness and the same maximum temperature. Additionally the influences of material model and material constants of epoxy resin were investigated to expand the range of application of the fatigue life prediction.

Topics: Cycles , Fatigue life
Commentary by Dr. Valentin Fuster
2015;():V002T02A023. doi:10.1115/IPACK2015-48275.

In the present study, a conservative integral based on the Betti reciprocal principle is formulated in order to obtain the intensity of singularity at a vertex of the interface in three-dimensional piezoelectric bi-material bonded joints. To our knowledge, there are few studies on the determination of the intensity of singularity in the three-dimensional piezoelectric bonded joints. In addition, no study on the determination of the intensity of singularity in the 3D piezoelectric bonded joints using the conservative integral has been conducted. Eigenanalysis formulated using a three-dimensional finite element method (FEM) is used to calculate the order of stress singularity, angular variables of mechanical displacements, stresses, electric displacements and electric potential. In order to investigate the influence of an integral area on the accuracy of the results, models with various integral areas are used. The results are compared with those obtained from FEM.

Commentary by Dr. Valentin Fuster
2015;():V002T02A024. doi:10.1115/IPACK2015-48553.

The reliability of solder joints on printed circuit boards (PCBs) is significantly affected by thermal fatigue processes due to downsizing and high density packaging in electronic components. Accordingly, there is a strong desire in related industries for development of a new nondestructive inspection technology to detect fatigue cracks appearing in these joints. The authors have applied the SP-μCT, a synchrotron radiation X-ray microtomography system, to the nondestructive observation of such cracks. However, for planar objects such as PCB substrates, reconstruction of CT images is difficult due to insufficient X-ray transmission along the parallel axis of the substrate. In order to solve this problem, a synchrotron radiation X-ray laminography system was developed to overcome the size limits of such specimens. In this work, this system was applied to the three-dimensional, nondestructive observation of thermal fatigue cracks in solder joints, for which X-ray CT inspection has been extremely difficult. The observed specimens included two typical joint structures formed using Sn-3.0Ag-0.5Cu solder: (1) a fine pitch ball grid array (FBGA) joint specimen in which an LSI package is connected to a substrate by solder bumps 360 μm in diameter, and (2) a die-attached specimen in which a 3 mm square ceramic chip is mounted on a substrate. The optical system developed for use in X-ray laminography was constructed to provide a rotation axis with a 30° tilt from the right angle to the X-ray beam, and to obtain X-ray projection images via the beam monitor. The same solder joints were observed successively using the laminography system at beamline BL20XU at SPring-8, the largest synchrotron radiation facility in Japan. In the FBGA type specimen, fatigue cracks were clearly observed to appear at the periphery of the joint interface, and to propagate gradually to the inner regions of the solder bumps as thermal cycling proceeded. In contrast, in the die-attached joint specimen, micro-cracks were observed to appear and propagate through the thin solder layer. An important observation was that these micro-cracks become interconnected prior to propagation of the main fatigue crack. The fatigue crack propagation lifetime was also estimated in both specimens by measuring the crack surface area and calculating the average crack propagation rate through the three-dimensional images. Consequently, the sectional images obtained by the laminography system clearly show the process of crack propagation due to thermal cyclic loading.

Commentary by Dr. Valentin Fuster
2015;():V002T02A025. doi:10.1115/IPACK2015-48605.

Fatigue damage in solder joints is one of the most significant factors in the failure of electronic components. Accordingly, many research studies on the fatigue lifetime evaluation of solder joints have been undertaken to improve the reliability of the components. The authors have devised a lap-joint specimen with high stiffness fixtures in order to carry out shear fatigue testing on thin solder joints, which have thickness of a few hundred μm and are manufactured via a reflow process similar to that used in actual printed circuit boards (PCBs). In this work, using the developed lap-joint specimen, the fatigue properties, including crack initiation and propagation of Sn-3.0Ag-0.5Cu solder joints were evaluated under low cycle shear loading conditions with creep deformation. The lap-joint specimen was fabricated by the reflow soldering of two copper adherend, and was assembled with high stiffness loading fixtures. The dimensions of the solder joint are 4 mm (length) × 2 mm (width), with a thickness ranging from 100 to 400 μm. In the shear fatigue test, under the assumption of thermal loading conditions of actual PCBs, the inelastic strain amplitude and total strain rate were set to from 0.5 to 1.2 % and 1×10−4 s−1, respectively. In addition, the fatigue crack initiation lifetime is defined as the number of cycles N20% at which the load amplitude has decreased by 20 % from the initial value. As the first study result, the experimental relations between the fatigue crack initiation lifetime and the inelastic strain range were obtained. Next, in order to apply the experimental data to the evaluation of fatigue crack initiation in actual solder joints via finite element analyses, the lifetime data were related to the calculated inelastic strain at the interface corners of the solder joint of the specimen, where fatigue cracks initiate due to strain concentration. Finally, assuming that the reduction of the load amplitude corresponds linearly to the fatigue crack length, the experimental relations between the fatigue crack propagation rate and J-integral range were also obtained. The experimental data are regarded to be valid, given a comparison to other crack propagation curves for solder obtained by tensile cyclic loading of a flat specimen with a center crack. Consequently, the developed lap-joint specimen with high rigidity is effective for acquiring the material properties regarding fatigue crack initiation and propagation in actual thin solder joints.

Commentary by Dr. Valentin Fuster
2015;():V002T02A026. doi:10.1115/IPACK2015-48613.

Despite being a critical phenomenon of tremendous technological significance in ultrasonic flip-chip and wire bonding processes of today’s microelectronic devices, interfacial bond formation still calls for better understanding at a fundamental level. The goal of the research is to improve these processes through better understanding and modeling of bond formation. This paper presents a micromechanics model that addresses increasing contact area during ultrasonic cyclic loading cycle. The micromechanics model provides interfacial shear stress as boundary condition to FEM simulations of ultrasonic bonding processes. Comparison between preliminary results and experimental data is conducted.

Topics: Wire bonding
Commentary by Dr. Valentin Fuster
2015;():V002T02A027. doi:10.1115/IPACK2015-48707.

The focus of this paper is on the stress-strain behavior and creep response of a pressure-sensitive adhesive (PSA) with and without carrier layers. This study consists of two phases. The first phase focuses on understanding of the effects of fabrication profiles, including bonding pressure, bonding temperature, bonding time, and aging time, on the PSA joint strength. This part of the study is used to identify an acceptable bonding and aging conditions for manufacturing a robust PSA bonded assembly. Specimens fabricated with this selected set of bonding process conditions are then used for mechanical characterization. The second phase focuses on the assembly’s mechanical behavior (stress-strain behavior and the creep curves) under different loading conditions, including loading stress, loading rate, and loading temperature. The mechanical behavior of PSA bonded assemblies is affected not only by the loading conditions, but also by the assembly architecture. The mechanical behaviors and failure modes of PSAs with and without carrier layers are compared. The reasons for these differences are also discussed.

Topics: Pressure , Adhesives
Commentary by Dr. Valentin Fuster
2015;():V002T02A028. doi:10.1115/IPACK2015-48812.

During ultrasonic ball bonding of copper wire to aluminum pad, the two alloys are joined over an immensely short period of time (<100ms), at a relatively low temperature (< 200°C). Bond formation in such condition is related to accelerated diffusional processes and formation of intermetallic compounds (IMC). Despite the industrial importance of the phenomenon, the micro-mechanism of IMC formation is not clearly understood, nor deeply studied. One of the main barriers toward understanding the phenomena is the limited capability of experimental analysis for analyzing processes occurring over short period of time. In this research, a combination of theoretical analysis and finite element simulation is used to investigate the mechanisms that lead to diffusion enhancement and, as a result, IMCs formation.

Commentary by Dr. Valentin Fuster

Advanced Electronics and Photonics: Packaging, Interconnect and Reliability: Flexible and Wearable Electronics

2015;():V002T02A029. doi:10.1115/IPACK2015-48130.

Interconnects that can deform under monotonous and/or repeated loading are increasingly important to a new class of electronic devices used for wearable applications. Such interconnects integrate different material sets such as polymers and metallic conductors and are subjected to large strain levels. A typical method to overcome the material incompatibility involves the conductor in the form of a serpentine or an out-of-the plane buckled geometry. In this paper, we demonstrate a novel combination of interconnect materials that enables significant improvement in the interconnect stretchability using Indium over the state-of-the-art without affecting the system performance. This was achieved without the necessity of the serpentine interconnects geometry that significantly improves the routing density. The manufacturing method used for this approach is also described. Finally, we discuss the cost competitiveness of the materials and the manufacturing method to assess the commercial viability of this approach. (5nm)

Commentary by Dr. Valentin Fuster
2015;():V002T02A030. doi:10.1115/IPACK2015-48503.

Ultra-thin ceramic films deposited by atomic layer deposition (ALD) can provide an excellent oxygen and moisture barrier for diverse applications, such as organic light emitting devices, micro heat pipes, vacuum packaging, and flexible electronics. Due to their nano-scale thickness, these films exhibit a certain degree of flexibility despite being ceramic. Above a critical strain, the ALD films will crack, and this cracking has been shown to be governed by a fracture mechanics model. This paper shows the critical cracking strain of Al2O3 deposited on polymers can be improved by incorporating the ceramic film into a nano-laminate (NL) structure, with alternating layers of ALD Al2O3 and a compliant polymer film. We find that the critical cracking strain depends on the elastic modulus of the polymer film. We experimentally demonstrate a factor of 2 improvement in critical cracking strain using an 8-layer polymer/ALD NL, with 3 different polymers, independent of the polymer thickness.

Commentary by Dr. Valentin Fuster
2015;():V002T02A031. doi:10.1115/IPACK2015-48704.

A novel interconnect approach was developed to enable packaging of miniature (<0.5 mm) MEMS pressure sensors for minimally invasive sensing applications. The interconnect approach is a variant of traditional flexible laminate circuits but does not require expensive patterning steps. It provides tight tolerance and assembly automation at relatively lower costs. In this paper, details of the novel interconnect and cabling approaches are disclosed. Examples of applications that benefit from this approach are also discussed. Experimental results on new ultra-miniature sensors utilizing the developed interconnect approach are presented.

Commentary by Dr. Valentin Fuster
2015;():V002T02A032. doi:10.1115/IPACK2015-48711.

A smart watch is one of the most popular wearable devices now. The end user cares about the electronic performance and safety. Along with the battery life and security, thermal safety is the most common concern. We show how to meet the ergonomic standard of user, predict the thermal performance on the typical sceneries. A thermal simulation software Flotherm or Icepack can be applied to the design stage.

Commentary by Dr. Valentin Fuster

Advanced Electronics and Photonics: Packaging, Interconnect and Reliability: Harsh Environments and High Temperature Electronics

2015;():V002T02A033. doi:10.1115/IPACK2015-48009.

This study illustrates test results and comparative literature data on the influence of isothermal aging and thermal cycling associated with Sn-1.0Ag-0.5Cu (SAC105) and Sn-3.0Ag-0.5Cu (SAC305) ball grid array (BGA) solder joints on three board finishes (ImAg, ENIG, ENEPIG). The resulting degradation shows that the characteristic lifetimes for both SAC105 and SAC305 decrease in the order ENIG > ENEPIG > ImAg. SAC305, with a higher relative fraction of Ag3Sn IMC within the solder, performs better than SAC105. SEM and EDX analysis shows continuous growth of Cu-Sn intermetallic compounds (IMC) on SAC/ImAg systems and Cu-Ni-Sn IMC on SAC/ENIG/ENEPIG systems at board side solder joints, which eventually cause fatigue failures.

Commentary by Dr. Valentin Fuster
2015;():V002T02A034. doi:10.1115/IPACK2015-48049.

The reliability of the data center equipment is being compromised as the American Society of Heating, Refrigeration and Air Conditioning Engineers recommendable psychometric limits are stretched outside the recommendable zones. When the ambient conditions are conducive enough the humidity and the gaseous contaminants present in the data centers react with the elements of Printed Circuit Boards (PCB) at various temperatures. The products of the reaction may lead to short circuit or extra resistance to the passage of current. This poses an increased threat to the reliability of the PCB. Contamination has become a serious problem in the developing nations like China and India where new data centers are rapidly coming up. The heavy industrialization and vehicular activities are the major source of the contamination. The losses due the corrosion of PCB by contaminants depends on various factors like concentration of gases, amount of humidity present, time of the day, location of the data center, filtration technique used for the air-conditioning system, etc. An actual study of effects of contaminants in data centers across the world would be a tedious task. Computational study saves the time as well as cost for this study. This research study gives deeper insights of the reaction mechanism. A computational study of the reaction of copper foils (representing the PCB) placed in a Paddle Wheel Test setup would be carried out. A Paddle Wheel Test setup gives us the flexibility to test various gases, that could pose a threat to data center equipment, without disturbing the actually data center servers. A reaction of hydrogen sulfide and sulfur dioxide on copper in the presence of humidity will be carried out in this study.

Commentary by Dr. Valentin Fuster
2015;():V002T02A035. doi:10.1115/IPACK2015-48323.

Solid liquid inter diffusion (SLID) is an interconnection technique for electronic packaging, particularly beneficial for high power and harsh environments conditions. It consists of the bonding of two materials with different melting points at a low processing temperature to achieve a high melting point interconnection. The materials investigated in this work are a gold-tin bond attaching a SiC diode to an AlN direct-bond-copper (DBC) substrate. Gold (Au) is the high melting point constituent while the eutectic gold-tin (80 wt.% Au-20 wt.%Sn) offers the low melting point (280°C). This work is aimed at the microstructural evaluation of the joints at different bonding and aging conditions in an effort to get the insights of this interconnection technology from a metallurgical perspective. Four different bonding conditions were used: 315°C-5min, 315°C-10min, 340°C-1min and 340°C-5min; from which a base-line as built condition was assessed by means of metallographical analysis. Furthermore, the samples were aged at 250°C from 1000 to 4000 hours in increments of 1000hrs to study and quantify the microstructural stability and intermetallic (IMC) growth at the interface. This aging experiment has been designed to obtain accelerated information on the kinetics of this reaction so that predictive models can be developed for the real application conditions. The samples were diced, polished and analyzed following standard metallographical techniques; both optical and electronic microscopy (SEM-EDS) was employed. The as-built samples, for the four bonding conditions, presented differences in IMC growth with the thickest layers appearing at the harshest processing conditions. After aging the IMC kept growing and the formation of a new IMC layer was discovered and investigated, furthermore, cracks started to show in some of the samples. It was observed that after 4000 hours some of the cracks extended across the whole interface.

Topics: Stability , Tin
Commentary by Dr. Valentin Fuster
2015;():V002T02A036. doi:10.1115/IPACK2015-48576.

This study focuses on the implications that the indiscriminate use of empirical shock metrics can have on shock risk assessment of Ball Grid Array (BGA) components in board level tests. Empirical shock metrics discussed are: 1) shock table applied acceleration, 2) top package acceleration and 3) board strain. Computational modeling and fundamental physics considerations were used to prove that the empirical metrics can lead to wrong conclusions about capability of the BGAs and their performance in the field. These empirical metrics can be considered an indirect indicator of solder joint failure, but because there is no universal (setup independent) correlation to solder joint failure, they are not directly transferable. For a metric to be universal it has to have a unique correlation to solder joint damage, i.e. it has to be based on the physics of failure. For the shock failures, such a metric can be solder joint stress or strain. There are two important implications of this study: 1) when indirect metrics are used, the value determined in the system condition should not be directly used as a test condition requirement and 2) BGA capability when measured by indirect metric will vary as a function of board setup. The indirect metrics can still be used, but they must be scaled to account for structural differences among board setups. For that scaling to be valid, it must be rooted in the knowledge of failure physics and the application of physics based metric. The study provides examples on how empirical metrics scaling should be done and discusses the physics behind it.

Commentary by Dr. Valentin Fuster
2015;():V002T02A037. doi:10.1115/IPACK2015-48577.

In this paper, we assess the high temperature shear strength of interconnects formed by sinter pastes via a Transient Liquid Phase Sintering (TLPS) process. The joints assessed in this study were formed by the transient liquid phase sintering of Sn and Cu. The shear strength of Cu dies sintered to Cu substrates with Cu-Sn sinter pastes was assessed at temperatures of 200°C and compared to that of specimens attached with Sn3.5Ag solder. In contrast to the shear strength of the sintered specimens, the shear strength of the soldered specimens drops below 10MPa under these conditions. High temperature creep tests were performed at the same temperature level for the soldered and sintered specimens. It was found that the Sn3.5Ag interconnects show extensive creep with short time-to-failure. The joints of sintered specimens did not undergo considerable deformation due to creep. Microstructural analyses have been performed on interconnects formed between Cu dies and Cu substrates and Si diodes on Direct Bond Copper (DBC) substrates. The joint microstructure consists of a matrix of Cu-Sn intermetallic compounds (IMCs) either with or without additional Cu particles dispersed in the matrix. It is demonstrated that the paste-based TLPS interconnects assessed combine short durations for process completion with both high shear strength and high resistance to creep under elevated temperature conditions. This, in combination with high thermal conductivity, shows that transient liquid phase sinter pastes have the potential to be an excellent high temperature and high power interconnect technology.

Commentary by Dr. Valentin Fuster
2015;():V002T02A038. doi:10.1115/IPACK2015-48578.

This paper discusses a new approach for definition of temperature cycling qualification requirement that accounts for the physics of the deformation process in use condition and in the accelerated temperature cycling test condition. The methodology is used to define solder joint reliability (SJR) requirement for Package on Package (PoP) components. Included in the study is the impact of adhesives on SJR requirements. The approach used is different from standards-based approaches that define the requirements in the way that is often independent of package materials and geometries. Physics based damage metrics and numerical modeling was used to comprehend design, technology, material, and temperature profile and provide an in-depth understanding of package deformation and failure mechanism. This, coupled with a developed fatigue law was then used to translate use conditions to test condition requirement.

The study shows that accelerated test will not accelerate all PoP solder joints equally and that requirements for PoP to board interconnects will be different from requirements for top–to–bottom package interconnects. Similarly, for component with adhesives, when requirements are based on physics, they must be different than requirements for component without adhesive and those requirement should be a function of adhesive thermo-mechanical material properties.

Given rapid changes in technology, explosion of new devices and new use conditions, manufacturers constantly make tradeoffs between performance, cost and reliability. The qualification process needs to be optimized to meet these increasing challenges and qualification based on knowledge of physics presented in this paper is designed to meet these challenges.

Commentary by Dr. Valentin Fuster
2015;():V002T02A039. doi:10.1115/IPACK2015-48620.

The microstructure, mechanical response, and failure behavior of lead free solder joints in electronic assemblies are constantly evolving when exposed to isothermal aging and/or thermal cycling environments. In our prior work on aging effects, we have demonstrated that the observed material behavior degradations of Sn-Ag-Cu (SAC) lead free solders during room temperature aging (25 C) and elevated temperature aging (50, 75, 100, 125, and 150 C) were unexpectedly large. The measured stress-strain data demonstrated large reductions in stiffness, yield stress, ultimate strength, and strain to failure (up to 50%) during the first 6 months after reflow solidification.

In this study, we have used both accelerated life testing and finite element modeling to explore how prior isothermal aging affects the overall reliability of PBGA packages subjected to thermal cycling. In the experimental work, an extensive test matrix of thermal cycling reliability testing has been performed using a test vehicle incorporating several sizes (5, 10, 15, 19 mm) of BGA daisy chain components with 0.4 and 0.8 mm solder joint pitches (SAC305). PCB test boards with 3 different surface finishes (ImAg, ENIG and ENEPIG) were utilized. In this paper, we concentrate on the reporting the results for a PBGA component with 15 mm body size.

Before thermal cycling began, the assembled test boards were divided up into test groups that were subjected to several sets of aging conditions (preconditioning) including 0, 6, and 12 months aging at T = 125 °C. After aging, the assemblies were subjected to thermal cycling (−40 to +125 °C) until failure occurred. The Weibull data failure plots have demonstrated that the thermal cycling reliabilities of pre-aged assemblies were significantly less than those of non-aged assemblies.

A three-dimensional finite element model of the tested 15 mm PBGA packages was also developed. The cross-sectional details of the solder ball and the internal structure of the BGA were examined by scanning electron microscopy (SEM) to capture the real geometry of the package. Simulations of thermal cycling from −40 to 125 C were performed. To include the effects of aging in the calculations, we have used a revised set of Anand viscoplastic stress-strain relations for the SAC305 Pb-free solder material that includes material parameters that evolve with the thermal history of the solder material. The accumulated plastic work (energy density dissipation) was used is the failure variable; and the Darveaux approach to predict crack initiation and crack growth was applied with aging dependent parameters to estimate the fatigue lives of the studied packages. We have obtained good correlation between our new reliability modeling procedure that includes aging and the measured solder joint reliability data. As expected from our prior studies on degradation of SAC material properties with aging, the reliability reductions were more severe for higher aging temperature and longer aging times.

Commentary by Dr. Valentin Fuster
2015;():V002T02A040. doi:10.1115/IPACK2015-48626.

In this work, an investigation has been performed on hygrothermally induced die stresses in flip chip assemblies caused by moisture absorption by the underfill encapsulant. Silicon test chips were first applied to perform a variety of measurements of moisture and thermally induced die stresses in flip chip on laminate assemblies. The sample die stresses were first measured after underfill encapsulation and cure, and then subsequently after long term storage (10 years) at room temperature and ambient humidity. The assemblies were then exposed to and 85 °C and 85% RH high humidity harsh environment for various durations, and the die stresses were evaluated as a function of the exposure time. Finally, reversibility tests were conducted to see whether the effects of moisture uptake were permanent. After long term storage, the experimental measurements showed that the normal stresses in the flip chip die relaxed significantly, while the shear stresses exhibited only small variations. In addition, the 85/85 hygrothermal exposure had strong effects, generating tensile die normal stress changes of up to 30 MPa in the flip chip assemblies. Thus, the initial compressive die normal stresses due to flip chip assembly were found to relax significantly during the moisture exposure. Upon fully redrying, it was observed that the moisture-induced stress changes were fully recovered.

The results of the experimental measurements were subsequently correlated with predictions from finite element numerical simulations. When performing moisture diffusion modeling, the conventional method is to use a thermal analogy based on the similarity of governing equations of heat transfer and moisture diffusion. However, this method has some drawbacks including giving incorrect results when dealing with time- and temperature-dependent problems or discontinuities in the moisture concentrations at material boundaries. In this study, we have used a new feature in ANSYS v14 to perform coupled multi-physics simulations of the moisture diffusion process without the aforementioned limitations. The simulation results were found to show strong correlations with experimental measurements.

Commentary by Dr. Valentin Fuster
2015;():V002T02A041. doi:10.1115/IPACK2015-48627.

Stress sensing test chips are a powerful tool for measuring in-situ stresses in electronic packages. In this study, we have applied (111) silicon test chips to perform a variety of measurements of die stresses in plastic packages. In particular, stresses were characterized in 240 pin Quad Flat Packs (QFPs) subjected to various thermal and moisture loadings. The utilized 10 × 10 mm sensor chips incorporated optimized eight-element piezoresistive rosettes that were capable of measuring the complete state of stress at the die surface (including the interfacial shear stresses).

The fabricated test chips were initially used to measure die stresses in the QFPs after molding and post mold bake. Measurement results were correlated with finite element simulations of the molding process. Subsequently, the effects of thermal cycling on the measured die stress distributions for selected packages were investigated. After these initial measurements, the samples were stored at room temperature and ambient humidity for 17 years. The samples were then re-measured after this long term storage to evaluate the degree of die stress relaxation that had occurred. Several packages were then exposed to a harsh high temperature and high humidity environment (85 C, 85% RH) for various time durations, and allowed to absorb moisture. The die stresses at several locations were characterized as a function of time during the hygrothermal exposure. The weight variations in each sample were also measured during the 85/85 exposure to gauge the moisture uptake, and reversibility tests were conducted to see whether the effects of moisture uptake were permanent. Using these measurements and numerical simulations, valuable insight has been gained on moisture induced failure phenomena in plastic packages.

Good agreement was found between the predicted and measured die normal stress distributions occurring after molding of the QFP. The magnitudes of the in-plane normal and shear stresses were found to have decreased by up to 30% after moderate levels of thermal cycling. After long term storage, the experimental measurements showed that the die normal stresses in the QFPs relaxed significantly (up to 40%), while the die shear stresses exhibited only small variations. In addition, the 85/85 hygrothermal exposures had strong effects, generating tensile die normal stress changes of up to 130 MPa. Upon fully redrying in reversibility tests, it was observed that the moisture-induced normal stress changes were not recovered. Good correlations were observed between the variations of sample weight (increases in moisture content) and the variations of the die normal and shear stress changes.

Topics: Stress
Commentary by Dr. Valentin Fuster
2015;():V002T02A042. doi:10.1115/IPACK2015-48669.

Thinner printed wiring assemblies (PWA) and smaller clearances are driven by the continuing increase of functionality and miniaturization in portable electronic devices. The probability of secondary impact during accidental drop and impact between a circuit card and adjacent components increases with the decrease in the size and weight of the product. In particular, compared to the initial impact, impulses caused by contact during secondary impacts are typically characterized by significant increase of amplitudes and extremely short pulse widths. As a result, stress wave transmission and reflection in printed wiring boards (PWBs) can be at a frequency range close to the resonant frequencies of PWA components with miniature internal structures, such as MEMS. This study focuses on analyzing the high frequency content of the accelerations due to stress wave propagation, reflections and dispersions in the thickness direction of multilayered PWBs, caused by secondary impact, and on the consequential effects on typical failure modes with high resonant frequencies.

Commentary by Dr. Valentin Fuster
2015;():V002T02A043. doi:10.1115/IPACK2015-48709.

Shaker table vibration testing is nothing new for electronic components. Such environmental tests are most often conducted in a sequential uniaxial setup, where the test article is sequentially rotated and excited along three different orthogonal orientations. While sequential axis testing does excite modes in all three directions sequentially, it does not quantify or qualify how modes along different axes interact with one another when excited simultaneously.

Traditional linear dynamics does not predict any cross-axis interactions between different spectral modes in vibrating structures, but this has long been suspected to be an oversimplification for many cases. The authors demonstrated this in a previous experiment, in which printed wiring assemblies (PWAs) of the same design were subjected to sequential uniaxial and simultaneous biaxial excitations. Boards undergoing bi-axial excitation suffered fatigue damage accumulation rates much higher than the superposition of damage rates from sequential uniaxial tests. Even as far back as 2010, the military added multi degree of freedom (MDoF) vibration tests to their 810G standard — so MDoF testing is rapidly gaining traction in the accelerated stress testing community. The cost of performing MDoF vibration durability testing can be significant, so an important technical issue turns into identifying when MDoF testing is necessary, and when single degree of freedom (SDoF) testing is sufficient.

This study addresses this issue using a combination of mathematical models and FEA simulations. It is intuitively obvious that larger and more massive circuit components are more susceptible to these nonlinear cross-axis interactions, especially as the excitation levels become significant; however our long term goal is to quantify the effects of such parameters on the nonlinear interactions. The focus of the study is a simple beam with a tip mass — representing a circuit component with leads for mounting to the printed wiring board (PWB). The study also considers the effect of the PWB dynamics on the mechanical response of the circuit element, as it undergoes worst case excitation. The effects of several parameters are investigated, including component properties (e.g. mass, and height) as well as bi-axial excitation conditions (eg. frequency, relative phase and amplitude).

Commentary by Dr. Valentin Fuster

Advanced Electronics and Photonics: Packaging, Interconnect and Reliability: Silicon Photonics and LED

2015;():V002T02A044. doi:10.1115/IPACK2015-48023.

Phosphor sedimentation has a great impact on the LED’s correlated color temperature (CCT) and the angular color uniformity (ACU). But fewer solutions have been proposed to overcome this effect. In this paper, we analysed the fundamental mechanism behind the phosphor sedimentation effect on LED’s ACU and proposed a simple structure to eliminate the effect. Monte Carlo ray-tracing simulations were conducted to validate the idea. The results show that the maximum CCT deviation with the proposed structure is within 100 K while that of the conventional one is as high as 680 K, and the ACU increases from 0.8811 to 0.9809 by 11.33%. It is concluded that this proposed structure has potential to be used to eliminate the phosphor sedimentation effect.

Commentary by Dr. Valentin Fuster
2015;():V002T02A045. doi:10.1115/IPACK2015-48257.

Today’s lighting technology is steadily becoming more energy efficient and less toxic to the environment since the passing of the Energy Independence and Security Act of 2007 (EISA) [1]. EISA has mandated a higher energy efficiency standard for lighting products and the phase out of the common incandescent lamp. This has led lighting manufacturers to pursue solid-state lighting (SSL) technologies for consumer lighting applications. However, two major roadblocks are hindering the transition process to SSL lamps: cost and quality. In order to cut cost, manufactures are moving towards cheaper packaging materials and a variety of package architecture construction techniques which may potentially erode the quality of the lamp and reduce its survivability in everyday applications. Typically, SSL lamps are given product lifetimes of over twenty years based off of the IES TM-21-11 lighting standard which does not include moisture effects or large operational temperatures [2]. A group of recently released off-the-shelf lamps have undergone a steady-state temperature humidity bias life test of 85°C/85%RH (85/85) to investigate the reliability in harsh environment applications.

The lack of accelerated test methods for lamps to assess reliability prior to introduction into the marketplace does not exist in literature. There is a need for SSL physics based models for the assessment and prediction of a lamp’s lifetime which is being spearheaded by the DOE [3]. In order to be fully accepted in the marketplace, SSL lamps must be able to perform similarly to incandescent lamps in these environments, as well as live up to the lifetime claims of manufacturers.

A lamp’s package architecture must be designed with performance factors in mind, as well as address some of the known and published package related failure mechanisms, such as carbonization of the encapsulant material, delamination, encapsulant yellowing, lens cracking, and phosphor thermal quenching [4]. Each failure mechanism produces the similar failure mode of lumen degradation predominately due to two contributing factors: high junction temperature and moisture ingress. The current state-of-the-art has focused on individual areas of the lamp, such as the LED chip, substrate material, electrical driver design and thermal management techniques. [5] – [16] Looking at the lamp as a whole is a novel approach and has not been seen before in literature.

This work followed the JEDEC standard JESD22-A101C of 85/85 with a one hour interval of applied voltage followed by a one hour interval of no applied voltage [17]. This test was performed continuously for each SSL lamp until it became nonoperational, i.e. did not turn on. Periodically, photometric measurements were taken following the IES LM-79-08 standard at room temperature using an integrating sphere, a spectrometer, and lighting software. The overall health of the SSL lamps was assed using the relative luminous flux (RLF), correlated color temperature (CCT) and the color difference (Δu′v′) using the Euclidean distance of the CIE 1976 color space coordinates. Finally, a Weibull analysis was completed to compare the characteristic lifetime of the SSL lamp to the actual rated lifetime. An important result from this work shows that the rated lifetime does not come close to the actual lifetime when the SSL lamps are used in a harsh humid environment which is fairly common in outdoor applications across the U.S. Also, the photometric results are presented for the entire lifetime of each SSL lamp under test.

Commentary by Dr. Valentin Fuster
2015;():V002T02A046. doi:10.1115/IPACK2015-48664.

In this study, we proposed and demonstrated an effective approach to model and predict spectral power distribution (SPD) for a phosphor-converted light emitting diode (pc-LED). For emission and excitation, broadband diffuse transmittances of 1 mm YAG:Ce phosphor plates with different concentrations were measured by a spectrophotometer. For emission, it was found that transmittance for all wavelengths was almost identical. This result indicates that emission spectrum prediction could be simplified by simulating the radiant power of the peak wavelength only. At the peak wavelength (560 nm), our simulation results, in which optical constants were calculated by the Lorenz-Mie theory, agreed well with our measurements. For excitation, a novel transmittance measurement setup based on an LED goniophotometer was proposed to obtain the absorption coefficient. By adjusting the optical parameter in our ray-tracing model to fit measured transmittances, accurate absorption coefficients were determined. Based on our calculation and measured optical parameters, we simulated the radiant power of the blue light and yellow light of commercial white LED packages. By expanding the total blue and yellow power into linear combinations of wavelengths in both regions, we successfully predicted the SPD of our LED package. Our predicted SPD has good agreement with the measured results.

Commentary by Dr. Valentin Fuster
2015;():V002T02A047. doi:10.1115/IPACK2015-48724.

The reliability consideration of LED products includes both luminous flux drop and color shift. Previous research either talks about luminous maintenance or color shift, because luminous flux degradation usually takes very long time to observe. In this paper, the impact of a VOC (volatile organic compound) contaminated luminous flux and color stability are examined. As a result, both luminous degradation and color shift had been recorded in a short time. Test samples are white, phosphor-converted, high-power LED packages. Absolute radiant flux is measured with integrating sphere system to calculate the luminous flux. Luminous flux degradation and color shift distance were plotted versus aging time to show the degradation pattern. A prognostic health management (PHM) method based on the state variables and state estimator have been proposed in this paper. In this PHM framework, unscented kalman filter (UKF) was deployed as the carrier of all states. During the estimation process, third order dynamic transfer function was used to implement the PHM framework. Both of the luminous flux and color shift distance have been used as the state variable with the same PHM framework to exam the robustness of the method. Predicted remaining useful life is calculated at every measurement point to compare with the tested remaining useful life. The result shows that state estimator can be used as the method for the PHM of LED degradation with respect to both luminous flux and color shift distance. The prediction of remaining useful life of LED package, made by the states estimator and data driven approach, falls in the acceptable error-bounds (20%) after a short training of the estimator.

Commentary by Dr. Valentin Fuster

Fundamentals of Thermal and Fluid Transport in Nano, Micro, and Mini Scales: Continuum/Atomistic Modeling and Simulations

2015;():V002T06A001. doi:10.1115/IPACK2015-48032.

The thermal conductivities of the alloys of wurtzite AlN, GaN and InN are usually analyzed with the virtual crystal model based on the values of the constituent compounds. However, latest experiments and calculations reveal that the thermal conductivity of wurtzite InN is about three times larger than the previously used value. Thus it is necessary to reanalyze the thermal conductivities of these alloys. In this work, the intrinsic thermal conductivities of AlxGa1−xN, InxGa1−xN and InxAl1−xN are calculated with first-principles calculations along with the virtual crystal treatment. It is found that the thermal conductivities of these alloys are strongly suppressed even after a small amount of alloying. For instance, the in-plane and out-of-plane thermal conductivities of In0.99Ga0.01 N are 66 Wm−1K−1 and 76 Wm−1K−1 respectively, while they are 40 Wm−1K−1 and 48 Wm−1 K−1 for In0.99Al0.01 N, compared with the corresponding values of 130 Wm−1 K−1 and 145 Wm−1 K−1 for bulk wurtzite InN. When the fraction x varies from 0.2 to 0.8, the thermal conductivities of the alloys do not change much. Additionally, the distribution of mean free path indicates that the size effect can persist up to 10μm for both pure compounds and their alloys at room temperature.

Commentary by Dr. Valentin Fuster
2015;():V002T06A002. doi:10.1115/IPACK2015-48114.

Gallium arsenide is the second most used semiconductor material with applications in light-emitting diodes, field-effect transistors, and integrated circuits. Thus, understanding and controlling the thermal conductivity of gallium arsenide is crucial to design devices for such applications. The goal of this study is to predict the thermal conductivity of gallium arsenide as a function of temperature and vacancy concentration. Thermal conductivities are predicted using an equilibrium molecular dynamics method based on the Green-Kubo formalism with temperatures between 300 K and 900 K and vacancy concentrations up to 0.5%. Our results show that the thermal conductivities of the vacancy-free system predicted by our model are in good agreement with experimental values around the Debye temperature. In addition, our model predicts that conductivities significantly decrease with increasing vacancy concentration. At 300 K conductivities drop by 39.5% with a 0.1% defect content and 74.4% with 0.5% respect to that of the pure system. The power spectra of thermal conductivities and heat current autocorrelation functions indicate that phonon scattering produced near the vacancies reduces the contribution of the acoustic frequencies. The density of states quantifies the decrease of acoustic and optic frequencies by increasing the vacancy concentration.

Commentary by Dr. Valentin Fuster

Fundamentals of Thermal and Fluid Transport in Nano, Micro, and Mini Scales: Micro/Nano Structures in Phase Change Heat Transfer

2015;():V002T06A003. doi:10.1115/IPACK2015-48153.

In this study heat transfer due to vaporization is investigated for low concentration binary mixtures of 2-propanol/water on nanostructured surfaces. The surfaces are comprised of zinc oxide (ZnO) nanocrystals grown by hydrothermal synthesis on a smooth copper substrate having an average roughness of 0.06 μm. Three nanostructured surfaces used in this study differ only in the duration of the hydrothermal synthesis consisting of 4, 10, and 24 hours of surface growth. Surface geometries were observed to be a function of hydrothermal synthesis time with an increase in area coverage, length, and diameter of nanocrystals with increase synthesis time. ZnO nanocrystals exhibit mean diameter of 500–700 nm, mean length of 1.7–3.3 μm and porosities of 0.04–0.58. Individual droplets between 2.5–3.9 mm in diameter consisting of a binary mixture of 2-propanol/water with concentration of either 0.01 M or 0.03 M were deposited at a minimum distance above the surface that would be sufficient for droplets to detach on their own due to gravity onto a nanostructured surface at temperatures between 110–140 °C. High speed video was used to record the deposition and vaporization process and through image analysis it was possible to measure heat transfer coefficients based on the wetted area, as well as other parameters. Through the video analysis it was observed that droplets which are approximately spherical, impact the surface and spread into a thin film with mean film thickness between 65–400 μm which then evaporated by film evaporation without nucleate boiling. Wettability of each of the surfaces was characterized through contact angle measurements from photographs of the droplet profile when the droplet profile was discernible. When profiles were not discernible due to hydrophilicity of some surfaces, contact angles were calculated by utilizing droplet volume and spread area. Contact angle measurements were performed on the surfaces before and after each experiment in order to document changes in wettability as a result of experimentation. Results from this experiment are compared to water droplet vaporization results from a previous experiment in order to determine whether 2-propanol enhances the heat transfer, and found that the heat transfer coefficient was increased by up to 128% in some cases. Heat transfer enhancement was found to be a function of droplet diameter as well as mixture concentration with 3.9 mm 0.01 M 2-propanol/water droplets showing larger enhancement. Potential uses of heat transfer in this application are also discussed.

Topics: Drops
Commentary by Dr. Valentin Fuster
2015;():V002T06A004. doi:10.1115/IPACK2015-48262.

Microporous metals are extensively applied in convective cooling of high heat flux systems such as electronics. Traditional fabrication approaches, such as sintering of metallic particles, however, produce materials with limited fluid transport capability. Here, we demonstrate control and enhancement of the permeability of porous copper inverse opals produced via electrodeposition around a sacrificial polymer template. Sintering of the template is used to control the fluid transport network microstructure, with permeability increasing for increasing sintering times. These electrodeposited structures achieve permeabilities greater than 1×10−12 m2 with 5 μm pores, roughly 5 times larger than those of porous sintered copper with comparable feature sizes. The high permeability and small feature sizes, with attendant high specific surface area and strong capillarity, offered by the sintered template electrodeposited copper are attractive for two phase cooling applications.

Commentary by Dr. Valentin Fuster
2015;():V002T06A005. doi:10.1115/IPACK2015-48628.

Boiling/evaporation characteristics of a water droplet on nanoparticles-accumulated bi-porous layers produced by boiling adhesion method are evaluated. In the boiling adhesion method, the bi-porous layer is coated by dropping or spraying nanoparticles-contained solution on a heated metal substrate. By this method, it is possible to produce nanoscale of pore layer formed by accumulating the nanoparticles that have high wettability and microscale of pores formed by boiling bubbles blowing through the layer that work as vapor discharging. Visualization experiments with a high speed camera clarify that the boiling/evaporation performance is improved on the nanoparticles bi-porous layer and also a wetting limit temperature drastically increases. Furthermore, there are many cases where the life time of the droplet shortens even in a low superheated temperature regime. These results suggest that the nanoparticles bi-porous layer would contribute not only to boiling heat transfer enhancement but also to the increase in the critical heat flux.

Commentary by Dr. Valentin Fuster
2015;():V002T06A006. doi:10.1115/IPACK2015-48737.

Two-phase microchannel heat sink is promising in cooling high power electronics with dielectric fluids. Compared to water, dielectric fluids can assure system safety in case of working fluid leakage. However, two-phase heat transfer of these hydrofluorocarbon refrigerants is restricted by their relatively low thermal conductivities and low latent heats. Numerous nanoscale/submicron structures have been developed to enhance the single and two-phase heat transfer in microchannels; but these techniques usually require nanoparticle seeds in multi-step wet processes or nanolithography to integrate these nanostructures. Therefore, most of these techniques were time-consuming and costly. In this study, we present a plasma etching method using a modified Bosch process to create silicon tips with nanoscale scallops in microchannels. This is a rapid and cost-effective method to integrate large density of nucleation sites without involving nanolithography method or using nanoparticle seeds. Then, these silicon tip arrays were aligned with side walls of microchannels. As a result, flow boiling heat transfer of a dielectric refrigerant, HFE-7000, is substantially enhanced in a microchannel heat sink (five parallel channels: 10 mm L × 220 μm W × 250 μm H). Compared to plain-wall microchannels, the average junction temperature can be reduced up to 10 °C at a heat flux of 55 W/cm2 and the equivalent thermal resistance of microchannel heat sink is reduced up to 31% at a mass flux of 1018 kg/m2·s.

Commentary by Dr. Valentin Fuster

Fundamentals of Thermal and Fluid Transport in Nano, Micro, and Mini Scales: Pool Boiling and Condensation

2015;():V002T06A007. doi:10.1115/IPACK2015-48667.

Boiling heat transfer has enormous impact on the effectiveness of various industrial processes like steam generation, desalination, and nuclear reactor operations. Heat transfer in the film boiling regime is significantly reduced as compared to the nucleate boiling regime due to the existence of a vapor layer at the solid-liquid interface (Leidenfrost effect). This vapor layer degrades heat transfer by up to two orders of magnitude and causes dryout, which can result in severe temperature excursions. This work maps out the heat transfer benefits of electrostatic suppression of the Leidenfrost state. Electrical suppression of the Leidenfrost state is observed for a variety of liquids, including organic solvents, water and electrically conducting salt solutions. Successful Leidenfrost state suppression is observed with moderate voltages even at ultrahigh temperatures exceeding 550 °C. Elimination of the vapor layer increases heat dissipation capacity of film boiling by more than one order of magnitude; up to 45X enhancement was measured in this work. This work also introduces the concept of tunable film boiling heat transfer. Overall, electrically-enhanced boiling can enable a new class of technologies for active control and enhancement of boiling heat transfer, with various applications in energy systems.

Commentary by Dr. Valentin Fuster

Fundamentals of Thermal and Fluid Transport in Nano, Micro, and Mini Scales: Single Phase Flows

2015;():V002T06A008. doi:10.1115/IPACK2015-48055.

In military applications, cooling of high heat flux antenna is a challenging problem considering the thermal, mechanical and limited space requirements. In addition to system cooling, thermal uniformity among the high power amplifiers is one of the main issues that should be taken into account for electrical performance requirements. Cold plate is the main mechanical part of the radar antenna structure where it serves as a cooler and a carrier. Liquid path and fin pattern are critical parts of the cold plate design that needs to be carefully studied. These topics are comprehensively discussed in this work. Finite element method software has been used for CFD and thermal analysis. Although cold plate is designed to cool high heat flux, it is known that there is liquid flow in it which applies some amount of hydraulic pressure. Some precautions are taken to withstand high pressure inside the cold plate. The system solution together with manifold design is examined in this study. The internal pressure drop in cold plate has a direct relation with the manifold design. All these topics are discussed in this work.

Commentary by Dr. Valentin Fuster
2015;():V002T06A009. doi:10.1115/IPACK2015-48122.

This study considers CFD simulations with conjugate heat transfer performed in the framework of designing a complex micro-scale cooling geometry. The numerical investigation of the three-dimensional, laminar flow (Reynolds number smaller than 480) and the solid conduction is done on a reduced model of the heat sink micro-structure to enable exploring a variety of configurations at a limited computational cost. The reduced model represents a unit-cell, and uses periodic and symmetry boundary conditions to mimic the conditions in the entire cooling manifold. A simulation of the entire heat sink micro-structure was performed to verify the unit-cell set-up, and the comparison demonstrated that the unit-cell simulations allow reducing the computational cost by two orders of magnitude while retaining accurate results. The baseline design for the unit-cell represents a configuration used in traditional electronic heat sinks, i.e. a simple channel geometry with a rectangular cross section, with a diameter of 50 μm, where the fluid flows between two cooling fins. Subsequently three types of modified geometries with feature sizes of 50 μm were considered: baffled geometries that guide the flow towards the hotspot region, geometries where the fins are connected by crossbars, and a woodpile structure without cooling fins. Three different mass-flow rates were tested. Based on the medium mass-flow rate considered, the woodpile geometry showed the highest heat transfer coefficient with an increase of 70% compared to the baseline geometry, but at the cost of increasing the pressure drop by more than 300%. The crossbar geometries were shown to be promising configurations, with increases in the heat transfer coefficient of more than 20% for a 70% increase in pressure drop. The potential for further optimization of the crossbar configurations by adding or removing individual crossbars will be investigated in a follow up study. The results presented demonstrate the increase in performance that can be obtained by investigating a variety of designs for single phase cooling devices using unit-cell conjugate heat transfer simulations.

Commentary by Dr. Valentin Fuster
2015;():V002T06A010. doi:10.1115/IPACK2015-48318.

The recent years have witnessed the tremendous development in electronics with high power density, such as highly integrated chips and high power LEDs. As a result, the continuous increase in power consumption of electronics is gradually leading to an urgent need for high performance cooling strategies. Among the existed cooling methods, liquid cooling has been proved to be a kind of effective cooling technology for the removal of a large amount of heat from high power devices. Traditional liquid cooling technique commonly refers to utilizing water as the coolant, which is low cost and owns a relatively higher specific heat capacity, however, lower convective coefficient. On the contrary, liquid metal owns much higher convective coefficient, however, lower specific heat capacity. In addition, the higher cost of liquid metal also limits its utilization with large quantity in electronic cooling areas. In this study, a hybrid mini/micro-channel heat sink, based on both of liquid metal and water, was demonstrated. The new system combines the advantages of the two coolants. Experimental studies were conducted to evaluate the capability of the cooling performances of the hybrid system under different operation conditions, including different flow rates, flow directions, pump failure and thermal shock. The experimental results indicate that the hybrid mini/micro channel heat sink owns better cooling performance than water-based heat sink.

Commentary by Dr. Valentin Fuster
2015;():V002T06A011. doi:10.1115/IPACK2015-48417.

The purpose of this paper is to demonstrate the possibility to selectively tune the convective heat transfer coefficient in different sections of a heat sink by varying the density of micro-features in order to minimize temperature gradients between discrete heat sources positioned along the flow path. Lifetime of power electronics is strongly correlated to the thermal management of the junction. Therefore, it is of interest to have constant junction temperatures across all devices in the array. Implementation of micro-feature enhancement on the convective side improves heat transfer due to an increase in surface area. Specific shapes such as micro hydrofoils offer a reduced pressure drop allowing for combined improvement of heat transfer and flow performance. This study presents experimental results from an array of three discrete heat source (20 × 15 mm) generating 100 W/cm2 and positioned in line along the flow path with a spacing of 10 mm between each of the sources. The heat sink was machined out of aluminum 6061 and micro-hydrofoils with a characteristic length of 500 μm were embedded in the cold plate. The cooling medium used is water at a flow rate of 3.6–13.4 g/s corresponding to a Reynolds number of 420–1575. It is demonstrated that the baseplate temperature can be maintained below 90°C and the difference between the maximum temperatures of each heat source is less than 6.7 °C at a heat flux of 100 W/cm2 and a water flow rate of 4.8 g/s.

Commentary by Dr. Valentin Fuster

Fundamentals of Thermal and Fluid Transport in Nano, Micro, and Mini Scales: Thin Film/Surface Tension Driven Flows

2015;():V002T06A012. doi:10.1115/IPACK2015-48149.

Large-scale evaporative cooling is one of the leading sources of fresh water consumption. Dry cooling based on existing heat exchangers, however, has found limited usage due to the high cost and large foot prints/weights. Development of alternative low-cost light-weight heat exchangers for dry cooling is therefore urgently needed. One promising design for such alternative heat exchangers is what we call Direct-contact Liquid-on-String Heat Exchangers (DILSHE). DILSHE consists of a vertically aligned array of inexpensive polymer strings. A nonvolatile liquid flows over the strings, forming thin liquid films. Large surface areas provided by these films enable efficient heat transfer to counter-flowing cooling air. Physics-based design and optimization of DILSHE requires rigorous understanding of flow and heat transfer phenomena of falling liquid films on highly curved surfaces. Formation of travelling beads through the Rayleigh-Plateau or Kapitza instability can enhance heat transfer across liquid-gas interfaces. We have developed a numerical model for liquid-gas flows and heat transfer in the drop-like regime, where the Rayleigh-Plateau instability dominates and the shape of travelling beads is governed mainly by the influence of surface tension. We solve the Young-Laplace equation to obtain the liquid bead shape, which was then used to construct a finite element model. The time-dependent Navier-Stokes equation and the energy equation were then solved to obtain velocity and temperature distributions in the liquid and the surrounding counter-flowing air. The temporal and spatial variations in the temperature of travelling beads are analyzed to evaluate the effective heat transfer coefficients, which are key input parameters for an overall heat exchange model to quantify the heat transfer characteristic of DILSHE. The present work helps build foundation for systematic design of new generations of heat exchangers for dry cooling.

Commentary by Dr. Valentin Fuster
2015;():V002T06A013. doi:10.1115/IPACK2015-48532.

In concentrating solar power plants, there is a strong incentive to increase the collection temperature and the overall exergy efficiency of the system. Some molten glass mixtures are attractive working fluids for high temperature solar thermal heat collection because optimized glass mixtures can be more stable, less-toxic, and less-corrosive at high temperatures (≥1000 °C). A specific phosphate glass mixture is considered in this study to explore its performance in a molten glass falling film central receiver design for collection of heat at conditions resulting in a mini-film with a thickness equal or less than 3mm. In our falling molten glass thin film, the phosphate glass flow is treated as a laminar, Newtonian and gravity-driven flow over a slightly inclined flat plate using an explicit finite difference scheme to evaluate its heat transfer performance for a direct absorption receiver concept. One of the main challenges of modeling transport in molten glass is the strong dependence of its viscosity on temperature. To incorporate this effect in our numerical analysis, a temperature-dependent viscosity model is used in the momentum equation to model the fluid behavior as it flows down the surface and is progressively heated. Using viscosity versus temperature data provided by Halotechnics, Inc. for the phosphate glass considered here, an exponential function is used to model the viscosity as it changes with temperature. Also, a variable film thickness model is implemented that adjusts to the viscosity variation with temperature. In order to avoid stability issues, the finite difference scheme is organized in terms of non-dimensional parameters that includes all important properties that govern the system. The results of our model indicate that thinning of the film as it flows over the heated surface enhances the heat transfer performance on the lower portion of the receiver system. The heat transfer coefficient increases instead of remaining constant (as normally expected for fully developed laminar flows) on the lower portion of the heated surface. Our analytical results further indicate that using a thin mini-film of molten glass for solar thermal heat collection provides high heat transfer performance.

Commentary by Dr. Valentin Fuster

Fundamentals of Thermal and Fluid Transport in Nano, Micro, and Mini Scales: Two Phase Flows

2015;():V002T06A014. doi:10.1115/IPACK2015-48177.

Slug flow is a commonly encountered flow regime in microchannels due to the influence of surface tension and vapor confinement at small length scales. Few experimental studies have considered diabatic vapor-liquid slug flow, owing to difficulties in generating a well-controlled and repeatable slug flow regime; generation of vapor by wall heating typically leads to large, stochastic variations in the vapor bubble characteristics. To facilitate the study of flow behavior and vapor-liquid interfaces under precisely controlled conditions, a diabatic, one-component, two-phase microchannel flow was generated by separately injecting HFE-7100 vapor and liquid into a T-junction. Injection at independently controllable liquid and vapor flow rates allows the creation of vapor-liquid slug flow patterns in a downstream borosilicate microchannel of circular cross-section with a 500 μm inside diameter. The outside surface of the microchannel was coated with a 100 nm-thick layer of indium tin oxide (ITO) to generate a uniform wall heat flux via Joule heating while allowing full optical access for flow visualization. The growth of individual vapor bubbles was quantitatively visualized at different imposed heat fluxes, in terms of the percentage change in vapor bubble length along the heated microchannel. The results demonstrate the ability of the T-junction to generate diabatic, one-component, two-phase microchannel slug flow that is suitable for generating results for the validation of flow boiling models.

Commentary by Dr. Valentin Fuster
2015;():V002T06A015. doi:10.1115/IPACK2015-48184.

Two-phase liquid-vapor flow field measurements of confined jet impingement with boiling are performed using time-resolved stereo particle image velocimetry (stereo-PIV). A single circular jet of water, impinges normally from a 3.75 mm-diameter orifice onto a submerged circular heat source at an orifice-to-target spacing of 4 jet diameters. The impinging jet outflow including the vapor generated at the heat source are confined between the jet orifice plate and the bottom test section wall. Fluorescent seeding particles (10 μm in diameter) and time-resolved PIV measurements (taken at a sampling rate of 750 Hz) allow for imaging of the instantaneous interactions between the liquid and vapor structures. Liquid-phase velocity vectors within the two-phase flow field (with high vapor fractions) are presented as a function of heat flux at jet Reynolds numbers of 5,000 and 15,000 and contrasted with single-phase flow. The time-resolved measurements are used to highlight the influence of the vapor phase on the liquid flow field. It is found that bubble formation effectively blocks the developing wall-jet flow on the heated surface. The resulting liquid flow field in the confinement gap is dominated by vapor motion rather than by the entrainment from the developing wall jet.

Commentary by Dr. Valentin Fuster
2015;():V002T06A016. doi:10.1115/IPACK2015-48241.

Coalescence phenomena of droplets in a tube creeping flow were examined. Coalescence time of two droplets was measured. Clearance diameter of clearance area between droplets was also measured. The coalescence time obtained experimentally is compared with semi-theoretical formulas. Trends of semi-theoretical formulas of coalescence time and those of the experiments generally agreed. Influence of Reynolds number of tube creeping flow on coalescence of droplets was investigated.

Commentary by Dr. Valentin Fuster
2015;():V002T06A017. doi:10.1115/IPACK2015-48581.

This work examines the microscale physics of heat transfer processes in flow boiling of FC-72 in a single microchannel. Experimental results discussed in this paper provide new physical insight on the nature of heat transfer events. The study is enabled through development of a device with a composite substrate that consists of a high thermal conductivity material coated by a thin layer of a low thermal conductivity material with embedded temperature sensors. This novel arrangement enables measurement of local heat flux with a spatial resolution of 40–65 μm and a temporal resolution of 50 μs. The device generates isolated bubbles from a 300 nm in diameter artificial cavity fabricated at the center of a pulsed function micro-heater. Analysis of the temperature and heat flux data along with synchronized images of bubbles show that four mechanisms of heat transfer are active as a bubble grows and flows through the channel. These mechanisms of heat transfer are 1) microlayer evaporation, 2) interline evaporation, 3) transient conduction, and 4) micro-convection. The magnitude and time period of activation of these mechanisms of heat transfer are determined and their characteristics are discussed in details.

Commentary by Dr. Valentin Fuster
2015;():V002T06A018. doi:10.1115/IPACK2015-48670.

This study explores an extreme heat flux limit of microcooler for GaN-based HEMTs (high electron mobile transistors) which have local power densities exceeding 30 kW/cm2 using both solid conduction simulation and single-phase/two-phase conjugate simulations. Solid conduction simulation models are developed for full geometry of the microcooler to account for the overall thermal resistances from GaN HEMT to working fluid. This allows investigating the temperature distribution of the suggested microcooler. Parametric studies are also performed to investigate the impact of geometries and heat transfer coefficients on the junction temperature. The solid conduction simulation results using COMSOL Multiphysics agree well with single-cell ANSYS Fluent simulation results.

Separately, fluid-solid conjugate CFD (Computational Fluid Dynamics) simulation models provide the detailed flow information in the microchannel using a single-channel geometry with symmetry boundary conditions. Single-phase CFD simulations obtain the lower bound of total pressure drop and heat transfer coefficient at the microchannel walls for a mass velocity range of G = 6000–24000 kg/m2-s. The local temperatures and velocity distributions are reported that can help with identifying the locations of the maximum velocity and recirculation regions that are susceptible to dryouts. Two additional alternative tapered inlet designs are proposed to alleviate the significant pressure loss at the entrance of the SiC channel. The impact of the tapered inlet designs on pressure drops and heat transfer coefficients is also investigated.

Two-phase simulations in microchannel are conducted using Volume-of-Fluid (VOF) method embedded in ANSYS Fluent to investigate two-phase flow patterns, flow boiling, and temperature distributions within the GaN HEMT device and SiC etched mircochannels. A user-defined function (UDF) accounts for the phase change process due to boiling at the microchannel walls. The results show that the time relaxation factor, ri has a strongly influence on both numerical convergence and flow solutions.

Commentary by Dr. Valentin Fuster

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