ASME Conference Presenter Attendance Policy and Archival Proceedings

2013;():V001T00A001. doi:10.1115/IPACK2013-NS1.

This online compilation of papers from the ASME 2013 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems (InterPACK2013) represents the archival version of the Conference Proceedings. According to ASME’s conference presenter attendance policy, if a paper is not presented at the Conference, the paper will not be published in the official archival Proceedings, which are registered with the Library of Congress and are submitted for abstracting and indexing. The paper also will not be published in The ASME Digital Collection and may not be cited as a published paper.

Commentary by Dr. Valentin Fuster

Advanced Packaging

2013;():V001T01A001. doi:10.1115/IPACK2013-73029.

Cadmium plated circular connectors and chromate conversion coated aluminum chassis are widely used on electronic equipment for both civilian and military aerospace applications. This article discusses electrical bonding resistance problems associated with cadmium plated circular connectors and chromate conversion coated aluminum chassis and proposes an innovative way to solve that problem.

Topics: Bonding
Commentary by Dr. Valentin Fuster
2013;():V001T01A002. doi:10.1115/IPACK2013-73119.

In this paper, a modeling flow has been developed for the analysis of large-area die-package power delivery networks. The analysis is implemented in an early pathfinding phase of a product development cycle so that technology options such as bump pitch and pattern can be defined before the real physical design is completed. The flow utilizes a popular commercially available on-die power delivery simulator, combined with a suite of custom software developed internally, and delivers worst-case static and dynamic voltage drops across a sufficiently representative portion of the die (larger than 1mm2 and with full silicon metal stack). Scenarios of different bump depopulation are then compared and any potential power delivery risk is identified. The flow has been employed to analyze the power delivery problem of a realistic on-die region containing logics from graphics block, where the impact of increasing levels of bump depopulation due to encroachment from adjacent I/O circuits was studied. Results have shown the effectiveness and efficiency of the proposed flow.

Commentary by Dr. Valentin Fuster
2013;():V001T01A003. doi:10.1115/IPACK2013-73177.

Modern integrated circuits (IC) and package design has scaled into the deep submicron regime and the nanometer regime. Fast and broadband frequency-domain electromagnetic analysis has become increasingly important. The large problem size encountered in the analysis of ICs and packages is a major challenge especially for a finite element method (FEM) based electromagnetic analysis.

To reduce the computational cost for large-scale electromagnetic analysis, model order reduction (MOR) methods have been developed to preprocess the huge linear system into reduced order models. However, in order to meet the modeling and simulation challenges arising from the IC and package design, existing MOR methods still have to overcome the following shortcomings. First, many existing MOR methods lack a closed-form error bound. Given an accuracy requirement, the model generated from existing methods may not be compact enough. Second, most of the existing reduced order models depend on frequency and right hand side. They lose efficiency when analyzing frequency-dependent problems with a large number of right hand sides. Last but not least, many existing MOR methods suffer from low frequency breakdown problem. Additional models have to be built if low frequency solutions, including DC solution, are required.

This paper proposes a minimal order model for any prescribed accuracy for the finite element based solution of general 3-D problems having arbitrary lossless/lossy structures and inhomogeneous materials. This model entails no theoretical approximations. It is frequency and right hand side independent, and hence can be employed for both fast frequency and right hand side sweep. Moreover, the model does not suffer from low-frequency breakdown and is accurate from zero to high frequencies. To facilitate the application of such a minimal order model, we have also developed an efficient algorithm to generate this model. Numerical experiments have demonstrated the accuracy and efficiency of the proposed method. In addition to frequency-domain analysis, the proposed model can also be used for fast time-domain analysis.

Commentary by Dr. Valentin Fuster
2013;():V001T01A004. doi:10.1115/IPACK2013-73209.

Pastes consisting of micron-sized particles of a low melting point metal (i.e. Sn) and a high melting point metal (e.g. Ag, Cu) embedded in organic binder have been developed to attach silicon or wideband gap semiconductor devices to metallic or ceramic substrates for power electronic applications requiring operation at high temperatures. The attachment is made by a pressure-less, low temperature transient liquid phase sintering (LT-TLPS) process in air. Process time and temperature, along with binder type and amount are adjusted to minimize the formation of voids in the joints. Test samples consisting of copper dice on copper substrates joined by these LT-TLPS sinter pastes have been manufactured for shear testing. A shear fixture for high-temperature testing has been designed, and shear tests have been performed at temperatures of 25°C, 125°C, 250°C, 400°C, and 600°C. The influence of process time, process temperature, and the ratio of low-melting point metal (Sn) to high-melting point metal (Ag, Cu) on the shear strength at each temperature has been assessed. It has been shown that the shear strength of TLPS sinter joints remains high up to the melting point of the dominant intermetallic phase of the joint. The joints show no softening below the melting point of these phases. AgSn sinter joints show only limited change in shear strength up to 400°C. CuSn joints exhibit high shear strength up to 600°C for high copper ratios. While process times of 5–15 minutes are sufficient to drive the sintering reaction to near completion, extended curing improves the strength of the sinter joints even more. Failure analyses for joints of different compositions have been conducted along with cross-sectioning of sintered but non-sheared specimens to correlate reliability to microstructure.

Commentary by Dr. Valentin Fuster
2013;():V001T01A005. doi:10.1115/IPACK2013-73244.

In the current work, we have extended our past studies on Flip Chip Ceramic Ball Grid Array (FC-BGA) microprocessor packaging configurations to investigate in-situ die stress variation during thermal and power cycling. The utilized (111) silicon sensor rosettes were able to measure the complete three-dimensional stress state (all 6 stress components) at each sensor site being monitored by the data acquisition hardware. The test chips had dimensions of 20 × 20 mm, and 3600 lead free solder interconnects (full area array) were used to connect the chips to high CTE ceramic chip carriers. A unique package carrier was developed to allow measurement of the die stresses in the FC-CBGA components under thermal and power cycling loads without inducing any additional mechanical loadings.

Initial experiments consisted of measuring the die stress levels while the components were subjected to a slow (quasi-static) temperature changes from 0 to 100 C. In later testing, long term thermal cycling of selected parts was performed from 0 to 100 C (40 minute cycle, 10 minute ramps and dwells). After various durations of cycling, the sensor resistances at critical locations on the die device surface (e.g. die center and die corners) were recorded. From the resistance data, the stresses at each site were calculated and plotted versus time. Finally, thermal and power cycling of selected parts was performed, and in-situ measurements of the transient die stress variations were performed. Power cycling was implemented by exciting the on-chip heaters on the test chips with various power levels. During the thermal/power cycling, sensor resistances at critical locations on the die device surface (e.g. die center and die corners) were recorded continuously. From the resistance data, the stresses at each site were calculated and plotted versus time.

Topics: Manufacturing , Stress
Commentary by Dr. Valentin Fuster
2013;():V001T01A006. doi:10.1115/IPACK2013-73280.

Through-silicon via (TSV) technology is expected to overcome the limitations of I/O density and helps in enhancing system performance of conventional flip chip packages. One of the challenges for producing reliable TSV packages is the stacking and joining of thin wafers or dies. In the case of the conventional solder interconnections, many reliability issues arise at the interface between solder and copper bump. As an alternative solution, Cu-Cu direct thermo-compression bonding (CuDB) is a possible option to enable three-dimension (3D) package integration. CuDB has several advantages over the solder based micro bump joining, such as reduction in soldering process steps, enabling higher interconnect density, enhanced thermal conductivity and decreased concerns about intermetallic compounds (IMC) formation. Critical issue of CuDB is bonding interface condition. After the bonding process, Cu-Cu direct bonding interface is obtained. However, several researchers have reported small voids at the bonded interface. These defects can act as an initial crack which may lead to eventual fracture of the interface. The fracture could happen due to the thermal expansion coefficient (CTE) mismatch between the substrate and the chip during the postbonding process, board level reflow or thermal cycling with large temperature changes. In this study, a quantitative assessment of the energy release rate has been made at the CuDB interface during temperature change finite element method (FEM). A parametric study is conducted to analyze the impact of the initial crack location and the material properties of surrounding materials. Finally, design recommendations are provided to minimize the probability of interfacial delamination in CuDB.

Commentary by Dr. Valentin Fuster
2013;():V001T01A007. doi:10.1115/IPACK2013-73314.

Cadmium Zinc Telluride (CZT) based radiation detectors have been developed over the past decade and are, increasingly, being used in security and healthcare applications. Improvements in radiation detector performance, size, and cost have been achieved; however, the manufacturability and reliability of the individual CZT detector package continues to limit widespread use and new applications.

To date, most CZT detector packages are designed, manufactured, and tested to requirements defined by manufacturers, rather than military, commercial, or industry standards, as is common for semiconductor packages. The lack of test standards has led to use restrictions and/or complex detector system design, as required to mitigate unknown or low detector package reliability. CZT detector packaging, as was the case for semiconductor packaging, has reached the point in technology maturation where a focus on optimizing detector design for manufacturability and reliability is appropriate and necessary.

This paper reviews the systematic approach, including design, process development, and testing, utilized in the development and demonstration of a highly manufacturable and reliable (95% reliability at 1000 cycles) CZT detector package. Finite Element Model (FEM) based design and material trade-off studies, development of highly manufacturable and reliable commercial electronic assembly processes, failure mode identification and mitigation, selection and use of reliability test standards, and analyses are detailed for a flip-chip-CZT-on-ceramic substrate, detector package targeted for field deployment. As well, the next steps in package and system design, manufacturing, and reliability testing are proposed.

Topics: Sensors
Commentary by Dr. Valentin Fuster

Emerging Technologies

2013;():V001T03A001. doi:10.1115/IPACK2013-73092.

This work presents enhanced composite joints that support both electrical or thermal transport in electronic packages. The joints are sequentially formed by applying a nanoparticle suspension, evaporating a solvent, self-assembling of nanoparticles by capillary bridging, and the formation of so called “necks” between micron-sized features. This sequence is used to either form low temperature electrical joints under copper pillars or enhanced percolating thermal underfills with areal contacts between filler particles of the composite. The report discusses processing aspects of the capillary bridges evolution and of uniform neck formation, it discusses strategies to achieve mechanically stable necks, and it compares the performance of the achieved joints against state-of-the-art solutions.

The capillary bridge evolution during liquid evaporation was investigated in copper pillar arrays and random particle beds. The vapor-liquid interface first penetrates locations of low pillar or particle density resulting in a dendritic fluid network. Once the network breaks up individual necks form. For aqueous nano-suspensions highly uniform necks with high yield were obtained by evaporation at 60°C. Isothermal conditions were preferred to yield equal neck counts at the cavity’s top and bottom surfaces. Mechanically stable silver necks required an annealing at only 150°C, dielectric necks an annealing at 140°C with a bi-modal approach. Therein polystyrene nanoparticles occupy interstitial positions in densly packed alumina necks, then melt and adhere to the alumina. The electrical necks showed a shear strength of 16 MPa, equivalent to silver joints used in power electronic packages. The thermal necks yielded a thermal conductivity of up to 3.8 W/mK, 5-fold higher than commercially available capillary thermal underfills.

Commentary by Dr. Valentin Fuster
2013;():V001T03A002. doi:10.1115/IPACK2013-73125.

There is an urgent need in surface mount technology (SMT) for a nontoxic, reusable and low temperature bonding technique which can afford good mechanical support as well as electrical contact. Meanwhile in the nanotechnology, many excellent and unique structure-related properties such as the high mechanical strength, the high conductivity and the adhesion ability of gecko feet have been studied. Our lab proposes a new patterned structure of Au nanowire array named nanowire surface fastener (NSF), which cold bonding for surface mount technology can be realized at room temperature. Then various methods have been developed to fabricate nanowire, such as arc discharge, catalytic CVD growth and template synthesis, and so on. Among these methods, the template method has been widely used for preparing one-dimensional nanostructures such as metals, semiconductors, polymers, and other materials by electrochemical, electroless deposition or sol-gel technique. Especially anodic aluminum oxide template assisted way has attached considerable attention due to its unique structure properties, such as controllable pore diameter, extremely narrow pore size distribution with high densities, high aspect ratios, and ideally cylindrical pore shape.

The well arranged porous anodic aluminum oxide membrane is fabricated from aluminum film by two steps zM oxalic acid electrolytes. The anodic aluminum oxide membrane was investigated for features such as pore size, interpore distance, and thickness by 40 V. It is important for fabrication of porous anodic aluminum oxide template to find out elimination of the barrier layer of oxide and the pore extending rate by 0.5 M phosphoric acid. Morphologies of surface of aluminum film between anodization process and the anodic aluminum oxide barrier layer was researched by using atomic force microscope and scanning electron microscope. Results showed that the anodic aluminum oxide having the same diameter of the pore and the well arranged pore array without branching channel was obtained. The diameter of the pore before the pore extending treatment is 42 nm and the diameter of the pore after the pore extending treatment for 30 minutes is 86 nm. It was found that the diameter of the pore increased per 15 nm by the pore extending treatment for 10 minutes. We fabricated the through-hole anodic aluminum oxide template and made Cu nanowire by the template of our own making. By using Cu nanowire, we try to produce nanowire surface fastener and evaluate its properties.

Commentary by Dr. Valentin Fuster
2013;():V001T03A003. doi:10.1115/IPACK2013-73130.

Carbon nanotube (CNT) has a great tolerance to high current density which is a cause of electromigration (EM). Therefore, CNT is expected to use as the materials of nanoscale components of electronic devices. The damage mechanisms of CNT are regarded as the effects of oxidation by Joule heating and/or the EM by high-density electron flows. In this study, we investigated the damage mechanism of CNT structures used as nano-component of electronic devices. An EM acceleration testing system was designed using the CNT structures collected at the gap of thin-film electrodes. The EM tests were conducted under the several kinds of current density conditions and the surrounding environments. An indicator of lifetime was determined by voltage measurements during the acceleration tests and their fracture phenomena were evaluated by means of microscopic observations. As the results, the amounts of lifetime of CNT were longer in the lower oxygen concentrations than in the air condition. In the microscopic studies, it was confirmed that the local evaporation of carbon atoms due to oxidation appeared at the cathode side of the CNT structures under low current density, and the center area of CNT under high current density. Both types of damage morphologies induced by oxidation and EM were observed at the damaged CNT. The results showed the dominant damage mechanism alternated between oxidation and EM depending on current density under oxygen rich conditions.

Commentary by Dr. Valentin Fuster
2013;():V001T03A004. doi:10.1115/IPACK2013-73166.

Heterogeneous integration in microelectronic systems using interposer technology has attracted significant research attention in the past few years. Interposer technology is based on stacking of several heterogeneous chips on a common carrier substrate, also referred to as the interposer. Compared to other technologies such as System-on-Chip (SoC) or System-in-Package (SiP), interposer-based integration offers several technological advantages. However, the thermal management of an interposer-based system is not well understood. The presence of multiple heat sources in various die and the interposer itself needs to be accounted for in any effective thermal model. While a finite-element based simulation may provide a reasonable temperature prediction tool, an analytical solution is highly desirable for understanding the fundamentals of the heat transfer process in interposers. In this paper, we describe our recent work on analytical modeling of heat transfer in interposer-based microelectronic systems. The basic governing energy conservation equations are solved to derive analytical expressions for the temperature distribution in an interposer-based microelectronic system. These solutions are combined with an iterative approach to provide the three-dimensional temperature field in an interposer. Results are in excellent agreement with finite-element solutions. The analytical model is utilized to study the effect of various parameters on the temperature field in an interposer system. Results from this work may be helpful in the thermal design of microelectronic systems containing interposers.

Commentary by Dr. Valentin Fuster
2013;():V001T03A005. doi:10.1115/IPACK2013-73195.

Thermoelectric (TE) generators have a potential advantage of the wide applicable temperature range by a proper selection of materials. In contrast, a steam turbine (ST) as a Rankine cycle thermodynamic generator is limited up to more or less 630 °C for the heat source. Unlike typical waste energy recovery systems, we propose a combined system placing a TE generator on top of a ST Rankine cycle generator. This system produces an additional power from the same energy source comparing to a stand-alone steam turbine system. Fuel efficiency is essential both for the economic efficiency and the ecological friendliness, especially for the global warming concern on the carbon dioxide (CO2) emission.

We report our study of the overall performance of the combined system with primarily focusing on the design parameters of thermoelectric generators. The steam temperature connecting two individual generators gives a trade-off in the system design. Too much lower the temperature reduces the ST performance and too much higher the temperature reduces the temperature difference across the TE generator hence reduces the TE performance. Based on the analytic modeling, the optimum steam temperature to be designed is found near at the maximum power design of TE generator. This optimum point changes depending on the hours-of-operation. It is because the energy conversion efficiency directly connects to the fuel consumption rate. As the result, physical upper-limit temperature of steam for ST appeared to provide the best fuel economy. We also investigated the impact of improving the figure-of-merit (ZT) of TE materials. As like generic TE engines, reduction of thermal conductivity is the most influential parameter for improvement. We also discuss the cost-performance. The combined system provides the payback per power output at the initial and also provides the significantly better energy economy [$/KWh].

Commentary by Dr. Valentin Fuster
2013;():V001T03A006. doi:10.1115/IPACK2013-73291.

Response of brittle plate to impact loads has been the subject of many research studies [1–7]. Specifically, glass presents a wide variety of applications in daily life, and helps to protect the displays of smartphones, tablets, PCs, and TVs from everyday wear and tear. Therefore, the necessity of glass to resist scratches, drop impacts, and bumps from everyday use leads to the importance of investigation of the glass response under dynamic impact loading. The ball drop test has been applied in the past, specifying an energy threshold as a prediction metric. Use of energy as the key parameter in impact testing is limited, since it does not account for the time spent in contact during the impact event. This study attempts to establish a reliable metric for impact testing based on a momentum change threshold. The deformation and the strain of the glass will be obtained by the Digital Image Correlation (DIC) system, while the rebound velocity will be measured with the high speed cameras. The global and local measurements are conducted to verify the accuracy of the experimental results. Finally, the FEA model is developed using ANSYS/LS-DYNA to provide a comprehensive understanding of the dynamic response of the glass. Excellent correlation in deflection is obtained between the measurements and predictions.

Commentary by Dr. Valentin Fuster
2013;():V001T03A007. doi:10.1115/IPACK2013-73292.

The needs of glass to resist the scratches, drops impact, and bump from everyday use lead to the importance of investigation of the glass fracture under dynamic impact loading. The strength of the glass under dynamic fracture conditions is significantly larger than that under quasi-static loading. There are several theoretic models. In this study, an accumulated damage model is implemented. The relation among the stress, loading rate, contact time and the fracture is investigated. The effect of impact area, impact energy and impact momentum on the glass fracture has been proved to further improve the dynamic fracture criterion of glass. For the experimental studies, the Digital Image Correlation (DIC) method enables one to obtain the first principal strain of the glass during the impact process. Moreover, the FEA model is developed in ANSYS/LS-DYNA™.

Commentary by Dr. Valentin Fuster
2013;():V001T03A008. doi:10.1115/IPACK2013-73293.

Glass is widely used as cover glass to protect the smartphones, tablets, PCs, and TVs from everyday wear and tear nowadays. There has been an increasing effort to understand the global behavior of glass substrate under impact, but the behavior of the edge for the thin glass has rarely been touched. In this study, the dynamic response of the glass edge when impacted with 1.75-inch steel ball from different heights (different potential energy) and different angles is studied. High-speed camera is applied for the direct visualization of the whole impact process. The Digital Image Correlation (DIC) method enables to obtain displacements (in-plane displacement and out-of-plane displacement) of the glass during the impact process. The failure mode for the edge impact is found to be predominantly buckling. The tape used in this study decreases wave propagation from the impact location. In addition, the FEA model of edge impact test is developed in ANSYS/LS-DYNA™.

Topics: Glass
Commentary by Dr. Valentin Fuster
2013;():V001T03A009. doi:10.1115/IPACK2013-73297.

Compact thermoelectric generators operating with small temperature differences can be used to power autonomous circuitry and low-power electronics. This work presents an analysis of potential design optimizations for such devices, also called μTEGs. The analysis considers the effects of external thermal resistances, fill factor, ZT values, and the choice of insulating filler material on the thermoelectric performance. Many of the trends are strongly related to the ratio of internal to external thermal resistance, which determines the proportion of the total temperature drop realized across the active region of the thermoelectric. The results of this analysis provide a framework for thermal optimization of thermoelectric devices designed for small-scale heat to electricity conversion. Further, external thermal resistances are shown to be a dominant factor in performance for compact devices.

Commentary by Dr. Valentin Fuster

Modeling and Simulation

2013;():V001T04A001. doi:10.1115/IPACK2013-73053.

Free-standing electrically conductive nanotube and nano-bridge structures offer a simple, small-scale, low-power option for pressure and temperature sensing. To sense pressure, a constant voltage is applied across the bridge. At small scales, the heat transfer coefficient is pressure-dependent. The change in the heat transfer coefficients result in the circuit operating at higher temperatures, with different resistances, at low pressures. This in turn will lead to a change in the electrical resistivity of the system. If the system is held at constant voltage, this can be measured as a change in the current in such systems, representing a simple alternative to existing Pirani gauges. The current work simulates the Joule heating, conduction and convection heat transfer of a 5 micron long suspended single-wall carbon nanotube, incorporating temperature-sensitive material properties. The simulation allows prediction of the thermo-electrical response of the systems. The results agree with the trends observed in existing devices. Additional results look at the effects of system length, temperature, and contact resistances between the substrate and the device.

Topics: Sensors , Modeling , Nanotubes
Commentary by Dr. Valentin Fuster
2013;():V001T04A002. doi:10.1115/IPACK2013-73061.

This study provides a thermo-structural simulation to investigate the behavior of nano-bridge resonators. A three-dimensional doubly clamped bridge with a length of 10 microns, a width of 1 micron and a thickness of 300 nm vibrating in the air is simulated. A free molecular heat transfer model is used to define the heat transfer coefficient and the damping coefficient. A Finite Difference method is used to solve the transient heat transfer equation coupled with the dynamic structural equation at each time step. The study is performed for silicon. The results show the steady state amplitude variations and vibration amplitude variations by the total heat amplitude correspond to a linear system. The results also show that increasing the total heat amplitude has more significant effects on increasing the vibration amplitude rather than the steady state amplitude by a factor of 1.2. The steady state amplitude and vibration amplitude variation by the surrounding gas pressure is investigated over a range of pressures from 1 kPa to 500 kPa for a total heat amplitude of 5000 MW/m2 (50 mW). The steady state amplitude and the vibration amplitude decrease by increasing the pressure due to an increase in the damping coefficient and the heat transfer coefficient. The rate of decrease is significantly higher for the vibration amplitude. This is due to the combination of increasing heat transfer coefficient, and increased damping, as the pressure increases.

Commentary by Dr. Valentin Fuster
2013;():V001T04A003. doi:10.1115/IPACK2013-73062.

Thermoelectric modules utilize available temperature differences to generate electricity by the Seebeck effect. The current study investigates the merits of employing thermoelectrics to harvest additional electric energy instead of just cooling concentrating photovoltaic (CPV) modules by heat sinks (heat extractors). One of the attractive options to convert solar energy into electricity efficiently is to laminate TE modules between CPV modules and heat extractors to form a CPV-TE/thermal hybrid system. In order to perform an accurate estimation of the additional electrical energy harvested, a coupled field model is developed to calculate the electrical performance of TE devices, which incorporates a rigorous interfacial energy balance including the Seebeck effect, the Peltier effect, and Joule heating, and results in better predictions of the conversion capability. Moreover, a 3D multiphysics computational model for the hybrid concentrating PV-TE/thermal (CPV-TE/T) water collector system consisting of a solar concentrator, 10 serially-connected GaAs/Ge PV cells, 300 couples of bismuth telluride TE modules, and a cooling channel with heat-recovery capability, is implemented by using the commercial FE–tool COMSOL™. A conjugate heat transfer model is used, assuming laminar flow through the cooling channel. The performance and efficiencies of the hybrid system are analyzed. As compared with the traditional PV/T system, a comparable thermal efficiency and a higher 8% increase of the electrical efficiency can be observed through the PV-TE hybrid system. Additionally, with the identical convective surface area and cooling flow rate in both configurations, the PV-TE/T hybrid system yields higher PV cell temperatures but more uniform temperature distributions across the cell array, which thus eliminates the current matching problem; however, the higher cell temperatures lower the PV module’s fatigue life, which has become one of the biggest challenges in the PV-TE hybrid system.

Commentary by Dr. Valentin Fuster
2013;():V001T04A004. doi:10.1115/IPACK2013-73074.

A unified creep plasticity damage (UCPD) model for Sn-Pb and Pb-free solders was developed and implemented into finite element analysis codes. The new model will be described along with the relationship between the model’s damage evolution equation and an empirical Coffin-Manson relationship for solder fatigue. Next, developments needed to model crack initiation and growth in solder joints will be described. Finally, experimentally observed cracks in typical solder joints subjected to thermal mechanical fatigue are compared with model predictions. Finite element based modeling is particularly suited for predicting solder joint fatigue of advanced electronics packaging, e.g. package-on-package (PoP), because it allows for evaluation of a variety of package materials and geometries.

Topics: Plasticity , Creep , Solders
Commentary by Dr. Valentin Fuster
2013;():V001T04A005. doi:10.1115/IPACK2013-73080.

Three-dimensional (3D) chip stacking is a promising approach for high performance microsystems. Such vertical integration could increase the clock frequency and reduce the signal delay. During operation, the input signal and the resulting input power change with time. Realistic power maps on active chip tiers produce highly non-uniform heat flux patterns with hotspots, which change with time. In this paper, a transient compact model of a multi-layer chip stack subjected to time dependent power map was developed. Inter-tier single phase microfluidic cooling with a pin fin array was used to enhance heat transfer. The validity of the compact model was confirmed by comparison with full computational fluid dynamics/heat transfer (CFD/HT) modeling. It was found that the transient compact model ran thousand times faster than the CFD/HT model. The maximum deviation between the two models was 1 °C. The compact model was then used to analyze the transient thermal response of a 4 layer dual core stack of Penryn microprocessors when a total power of 172.4 W with a 300 W/cm2 hot spot was suddenly applied. The hotspot temperature rise approaches 35 °C, at a steady state time of about 0.015 s. The temperature rise of bottom tier was always higher than the other three tiers during the transient process because it has only single side cooling, while other tiers have double sided cooling. Also, different power maps and flow patterns, including parallel and counter flow for different layers were investigated. It was found that controlling the flow in different layers individually instead of applying the same flow conditions could achieve better thermal performance and energy savings.

Commentary by Dr. Valentin Fuster
2013;():V001T04A006. doi:10.1115/IPACK2013-73112.

Portable electronics devices such as mobile phone and portable music player become compact and improve their performance. High-density packaging technology such as CSP (Chip Size Package) and Stacked-CSP is used for improving the performance of devices. CSP has a bonded structure composed of materials with different properties. A mismatch of material properties may cause stress singularity, which lead to the failure of bonding part in structures.

In the present study, a strain singular field near inter-face edge in three-dimensional joints is investigated using digital image correlation method. A specimen which silicon chip was embedded in resin is used in experiment and tensile load is applied to the specimen. Photograph of specimen surface is taken before and after loadings by laser microscope. Displacement on the surface was evaluated by the digital image correlation method (DICM) using data of surface pattern on the specimen, which the cross correlation coefficients for surface pattern are maximized. Strain on surface of specimen is calculated by using the moving least square method. On the other hand, 3D element free Galerkin method is applied to compute the displacement and strain distribution in a three-dimensional model of the specimen. In the element free Galerkin method, the physical values, i.e., displacement, strain and stress, can be obtained by using the displacement data at node. In this research, strain distribution near the edge of interface is computed based on the element free Galerkin method. Finally, the strain distribution obtained by the digital image correlation method and the moving least square method is compared with that obtained by the element free Galerkin method. The intensity of strain singularity is determined numerically and experimentally.

Commentary by Dr. Valentin Fuster
2013;():V001T04A007. doi:10.1115/IPACK2013-73115.

We develop and employ a self-consistent electro-thermal model to study the high field breakdown of carbon nanotube (CNT) network thin film transistors (CN-TFTs). We investigate the effects of the CNT alignment angle and length distribution on the breakdown process caused by excessive self-heating. We examine relevant breakdown characteristics such as the peak current and corresponding voltage and power in relation to these two network parameters. We find that the breakdown behavior can significantly vary with respect to the CNT length and alignment distribution even when the network density is kept the same. Results suggest that an optimum alignment (∼ 65°) can be found for a network with constant CNT lengths to obtain higher current/power without setting off an early breakdown. When both CNT length and alignment angle are varied, we find that networks with higher average CNT length have lower optimum alignment such that doubling the average CNT length lowers the optimum alignment angle by half. Therefore these network parameters need to be carefully selected to achieve greater thermal reliability and higher electrical performance.

Commentary by Dr. Valentin Fuster
2013;():V001T04A008. doi:10.1115/IPACK2013-73118.

The transient and steady-state response of single pass constant-flow (concentric parallel flow, concentric counter flow) heat exchangers was investigated using a finite volume method. Heat exchanger transients initiated by both step-change and sinusoidally varying hot stream inlet temperatures were investigated. The wall separating the fluid streams was modeled by conduction with thermal mass; hence the heat exchanger transient behavior is dependent on the thermal mass of the fluid streams as well as the internal wall. The outer wall is approximated as fully insulating. The time dependent temperature profiles were investigated as a function of heat exchanger dimensionless length and dimensionless time for both fluids. It was found that the transient response of the heat exchanger is controlled by a combination of the residence time and thermal capacitance of the fluid streams, the overall heat transfer coefficient between the fluid streams, and the thermal capacitance of the internal wall.

Commentary by Dr. Valentin Fuster
2013;():V001T04A009. doi:10.1115/IPACK2013-73151.

Stresses and mechanical strength of brittle materials (Si chip and insulator) around TSV (Through Silicon Via) structures in 3D SiP (Three Dimensional System in Package) were discussed under device operation condition and reflow process condition by using a large scale simulator ADVENTURECluster®, which was based on FEM (Finite Element Method), for ensuring the reliability of 3D SiP.

In case of the device operation, the equivalent stress of TSV were lower than yield stress of copper, and the maximum principal stress of Si and insulator were also lower than its bending strength. In case of the reflow process, the equivalent stress of TSV were over the yield stress of copper, and the maximum principal stresses of Si and insulator were closed to its bending strength. In addition, steep stress elevations were shown at edge part of Si and insulator. It will be a singular stress field by stress concentration. Its stress singularity was evaluated and the local strength of Si chip and insulator was discussed.

Commentary by Dr. Valentin Fuster
2013;():V001T04A010. doi:10.1115/IPACK2013-73161.

There is high demand for fatigue life prediction of solder joints in electronic packages such as ball grid arrays (BGAs). A key component of fatigue life prediction technology is a canary device, which warns of the impending risk of failure through loss of function before other important parts become severely impaired. In a BGA package, thermal fatigue of solder joints normally starts from the solder joints at the outermost part of the package. This can be taken advantage of by using the outermost solder joints as canary devices for detecting the degree of cumulative mechanical fatigue damage. To accurately estimate the lifetimes of other functional solder joints, it is essential to understand the relationship between the fatigue lives of canary joints and other functional joints. Damage path simulation is therefore proposed for predicting the crack propagation in solder joints on electronic packages through numerical simulation. During the process of designing the layout of canary joints and other joints, it is very useful to know not only the relationship between the fatigue lives of the canary and other joints, but also the path of crack propagation through all joints. This paper presents a method for estimating the relationship between the fatigue lives of canary joints and other joints by using damage path simulation. Some BGA packages mounted on a printed circuit board are modeled to demonstrate the process of estimating the lifetime of each joint under thermal cycle loading. A large-scale finite element model is used to accurately represent the geometrical properties of the printed circuit board and package. Both crack initiation and crack propagation processes can be simultaneously evaluated by modeling all of the solder joints on each package. The results show that damage path simulation and large-scale modeling are useful for determining the layout of canary joints in electronic packages.

Commentary by Dr. Valentin Fuster
2013;():V001T04A011. doi:10.1115/IPACK2013-73173.

Today, the transient Fourier heat conduction equation is not considered valid for the derivation of temperatures from the dissipation of Joule heat in nanoelectronics because the dimension of the circuit element is comparable to the mean free path of phonon energy carriers. Instead, the Boltzmann transport equation (BTE) for ballistic transport based on the scattering of phonons within the element is thought to govern heat transfer. However, phonons respond at acoustic frequencies in times on the order of 10–100 ps, and therefore the BTE would not have meaning if the Joule heat is conserved by a faster mechanism.

Unlike phonons with response times limited by acoustic frequencies, heat transfer in nanoelectronics based on QED induced heat transfer conserves Joule heat in times < 1 fs by the creation of EM radiation at optical frequencies. QED stands for quantum electrodynamics. In effect, QED heat transfer negates thermal conduction in nanoelectronics because Joule heat is conserved well before phonons respond.

QED induced heat transfer finds basis in Planck’s QM given by the Einstein-Hopf relation in terms of temperature and EM confinement of the atom as a harmonic oscillator. QM stands for quantum mechanics and EM for electromagnetic. Like the Fourier equation, the BTE is based on classical physics allowing the atom in nanoelectronic circuit elements to have finite heat capacity, thereby conserving Joule heat by an increase in temperature. QM differs by requiring the heat capacity of the atom to vanish. Conservation of Joule heat therefore proceeds by QED inducing the creation of excitons (hole and electron pairs) inside the circuit element by the frequency up-conversion of Joule heat to the element’s TIR confinement frequency. TIR stands for total internal reflection. Under the electric field across the element, the excitons separate to produce a positive space charge of holes that reduce the electrical resistance or upon recombination are lost by the emission of EM radiation to the surroundings.

TIR confinement of EM radiation is the natural consequence of the high surface to volume ratio of the nanoelectronic circuit elements that concentrates Joule heat almost entirely in their surface, the surfaces coinciding with the TIR mode shape of the QED radiation. TIR confinement is not permanent, present only during the absorption of Joule heat.

Charge creation aside, QM requires nanoelectronics circuit elements to remain at ambient temperature while dissipating Joule heat by QED radiation to the surroundings. Hot spots do not occur provided the RI of the circuit element is greater than the substrate or surroundings. RI stands for refractive index.

In this paper, QED radiation is illustrated with memristors, PC-RAM devices, and 1/ f noise in nanowires, the latter of interest as the advantage of QM in avoiding hot spots in nanoelectronics may be offset by the noise from the holes created in the circuit elements by QED induced radiation.

Commentary by Dr. Valentin Fuster
2013;():V001T04A012. doi:10.1115/IPACK2013-73178.

In this paper, we develop a multi-level modeling procedure for copper wirebonding that provides insights into (a) deformation and stress in wire, pad, and die (b) an assessment of the risk of ULK fracture during impact stage and ultrasonic vibration steps. First, we construct a nonlinear, dynamic finite element model (global) to study the mechanical responses of wire, pad, and the underlying ULK stacks during the impact stage and the last cycle of ultrasonic vibration in copper wirebonding. Specifically, these process steps are modeled through prescribing touch down and in-plane oscillatory motions on capillary, which result in dissimilar critical states of stress locally in the ULK stacks. Next, we develop a isogeometric model (local) for a generic configuration of ULK stacks with eight levels of metallization by composing the geometric primitives representing ILD layers, copper lines/vias, as well as the material interfaces following the Hierarchical Partition of Unity Field Composition technique. The description for material moduli in the entire ULK stacks is further enriched with a bi-linear damage law. The critical states of stress obtained in the global wirebond model are then converted into boundary conditions for the local ILD model under plane strain condition to simulate the crack initiation in the ULK stacks. We observe, from the simulation results, potential crack initiation sites along vertical /horizontal interfaces in the ULK stacks due to local compressive/tensile loading during impact/vibration step, respectively.

Commentary by Dr. Valentin Fuster
2013;():V001T04A013. doi:10.1115/IPACK2013-73191.

Multilayer ceramic capacitors (MLCCs) are used very widely as electric devices on printed circuit boards (PCBs). Impact loads are applied on MLCCs during PCB manufacturing processes with fast mounting machines or floor dropping of mobile appliances and MLCCs may crack sometime due to the mechanical design. In this paper, impact stresses, which were induced in MLCCs by split Hopkinson bar impact tests, were analyzed with large scale parallel computing method.

Topics: Ceramics , Stress
Commentary by Dr. Valentin Fuster
2013;():V001T04A014. doi:10.1115/IPACK2013-73200.

Time-domain dynamic analysis of vibratory systems becomes useful in finite element analysis (FEA) when the structure’s response can no longer be assumed linear, as frequency-domain (spectral superposition) methods require. Time-domain analysis also permits the use of cycle-counting methods when assessing the vibration durability of electronic assemblies. The analyst is often limited to simulating only the first few cycles of the vibration response in very complex models, to minimize the computational burden. However, the accuracy of time domain analysis can be questionable during these first few cycles, due to unwanted transients, unless the initial conditions are properly modeled to correctly produce the steady state response. This paper explores this sensitivity to initial conditions for undamped and damped structures. Strategies for calculating and implementing proper initial conditions within FEA are discussed. Two illustrative examples are presented for simplicity. The first consists of a simple cantilever beam so that the numerical results can be compared to known analytic solutions and the basic theory can be demonstrated. The second example is a 2D representation of a circuit card assembly containing multiple leadless chip resistor components, so that implementation details can be demonstrated for more complex structures. This paper is intended to have tutorial value to FEA users who have to conduct time-domain dynamic analysis.

Commentary by Dr. Valentin Fuster
2013;():V001T04A015. doi:10.1115/IPACK2013-73225.

Constrained by low thermodynamic efficiencies, thermoelectric generators (TEGs) require a comparatively large amount of heat to produce a given quantity of electricity. Therefore, further improvements in thermoelectric designs are needed. In this paper, a coupled-field thermoelectric model, which presents a rigorous interfacial energy balance by capturing Joule heating, Seebeck, Peltier and Thomson effects, is developed to gauge the feasibility of the two promising solutions to enhance power generated by the TEGs, utilizing the commercial FEA package COMSOL™ through the Physics Interface Builder. First, the patterned topography on wall surfaces is implemented and the improved performance has been observed by introducing stirred flows into the heat exchangers and equalizing the temperature across the channels. Referring to the analysis, approximately 10% enhancement in power generation can be addressed for the base-relief TEG. Second, the prospect of increasing the thermal transport capability of water by loading CuO nanoparticles in the TEGs with multi-scale heat exchangers is explored. It is found that the conversion performance of the water/CuO nanofluid-based TEG is superior when compared to the water-based TEG at the micro-scale, where the flow rate is relatively low. The significant insight is gained to fabricate the ideal TEGs with optimum power performance.

Commentary by Dr. Valentin Fuster
2013;():V001T04A016. doi:10.1115/IPACK2013-73228.

Convergence and miniaturization of consumer electronic products such as cameras, phones, etc. has been driven by enhanced performance and reduced microelectronics size. For past few decades Moore’s law has been driving the microelectronics industry to achieve high performance with small form-factors at a reasonable cost. While the continued miniaturization of the transistors has resulted in unparalleled growth of the electronics industry, further performance increment via size scaling could be cost-ineffective and difficult to manufacture. To satisfy the current/future integrated Circuit (IC) package requirements, vertical integration of chips holds the key, i.e., 3-D packaging. Chip-stacking (3-D) is emerging as a powerful technology to reduce package footprint, decrease interconnection power, higher frequencies, and provide efficient integration of heterogeneous devices. It allows further reduction in the form factor of current systems and eases the interconnect performance limitation since the components are integrated on top of each other instead of side-by-side, resulting in shorter interconnect lengths. Due to high package density and chip-stacking on top of each other, heat dissipation from the stacked chips becomes a concern. To overcome these thermal challenges and provide shorter/faster inter-chip electrical connection, Through Silicon Via (TSV) technology is being implemented in 3-D ICs.

TSVs allow 3-D chips to be interconnected directly and provide high speed signal propagation. TSVs provide inter-chip heat/current path but the current flowing through the TSVs results in localized heat generation (Joule Heating) within the silicon, which could be detrimental to the overall performance of the system. In this paper, the effect of Joule heating on the device performance measured by trans-conductance, electron mobility (e mobility), and channel thermal noise is analyzed. Thinned (100 μm) chips with a uniform power map and evenly distributed TSVs are analyzed in this work. Thermal distribution in the package is studied for different TSV currents including a base-line case of no-current (thermal TSV only) and the junction temperature is determined for each case. The response from the thermal analysis is correlated to the device performance through existing relations. Results indicate that joule heating has a significant effect on the thermal response of the 3D IC and subsequently proves to be detrimental to the chip performance. An understanding of the electrical performance dependence on TSV joule heating is developed through this work.

Topics: Joules , Heating
Commentary by Dr. Valentin Fuster
2013;():V001T04A017. doi:10.1115/IPACK2013-73245.

Current trends in the automotive industry warrant a variety of electronics for improved control, safety, efficiency and entertainment. Many of these electronic systems like engine control units, variable valve sensor, crankshaft-camshaft sensors are located under-hood. Electronics installed in under-hood applications are subjected simultaneously to mechanical vibrations and thermal loads. Typical failure modes caused by vibration induced high cycle fatigue include solder fatigue, copper trace or lead fracture. The solder interconnects accrue damage much faster when vibrated at elevated temperatures. Industry migration to lead-free solders has resulted in a proliferation of a wide variety of solder alloy compositions. Presently, the literature on mechanical behavior of lead-free alloys under simultaneous harsh environment of high-temperature vibration is sparse. In this paper, the reduction in stiffness of the PCB with temperature has been demonstrated by measuring the shift in natural frequencies. The test vehicle consisting of a variety of lead-free SAC305 daisy chain components including BGA, QFP, SOP and TSOPs has been tested to failure by subjecting it to two elevated temperatures and harmonic vibrations at the corresponding first natural frequency. The test matrix includes three test temperatures of 25C, 75C and 125C and simple harmonic vibration amplitude of 10G which are values typical in automotive testing. PCB deflection has been shown to increase with increase in temperature. The full field strain has been extracted using high speed cameras operating at 100,000 fps in conjunction with digital image correlation. Material properties of the PCB at test temperatures have been measured using tensile tests and dynamic mechanical analysis. FE simulation using global-local finite element models is thus correlated with the system characteristics such as modal shapes, natural frequencies and displacement amplitudes for every temperature. The solder level stresses have been extracted from the sub-models. Stress amplitude versus cycles to failure curves are obtained at all the three test temperatures. A comparison of failure modes for different surface mount packages at elevated test temperatures and vibration has been presented in this study.

Commentary by Dr. Valentin Fuster
2013;():V001T04A018. doi:10.1115/IPACK2013-73250.

This paper will show an investigation of off-the-shelf luminaires with the focus on the LED electronic drivers, specifically the aluminum electrolytic capacitors (AECs), that have been aged using high temperature shelf life (HTSL) testing of 135°C in order to prognosticate the remaining useful life of the luminaires. Luminaires have the potential of seeing excessive temperatures when being transported across the country or being stored in non-climate controlled warehouses. They are also being used in outdoor applications in desert environments that see little or no humidity but will experience extremely high temperatures during the day. This makes it important to increase our understanding of what effects being stored at high temperatures for a prolonged period of time will have on the usability and survivability of these devices. The U.S. Department of Energy has made a long term commitment to advance the efficiency, understanding and development of solid-state lighting (SSL) and is making a strong push for the acceptance and use of SSL products. In this work, the four AECs of three different types inside each LED electronic driver were studied. The change in capacitance and the change in equivalent series resistance (ESR) of the AECs were measured and considered to be a leading indication of failure of the LED system. These indicators were used to make remaining useful life predictions to develop an algorithm to predict the end of life of the AECs. The luminous flux of a pristine downlight module was also monitored using each LED electronic driver that was subjected to HTSL through the progression of the testing to determine a correlation between the light output of the lamp and the failing components of the LED electronic driver. Prognostic and Health Management (PHM) is a useful tool for assessment of the remaining life of electrical components and is demonstrated for AECs in this work.

Commentary by Dr. Valentin Fuster
2013;():V001T04A019. doi:10.1115/IPACK2013-73252.

This paper compares three prognostic algorithms applied to the same data recorded during the failure of a solder joint in ball grid array component attached to a printed circuit board. The objective is to expand on the relative strengths and weaknesses of each proposed algorithm. Emphasis will be placed on highlighting differences in underlying assumptions required for each algorithm, details of remaining useful life calculations, and methods of uncertainty quantification. Metrics tailored specifically for Prognostic Health Monitoring (PHM) are presented to characterize the performance of predictions. The relative merits of PHM algorithms based on a Kalman filter, extended Kalman filter, and a particle filter all demonstrated on the same data set will be discussed. The paper concludes by discussing which algorithm performs best given the information available about the system being monitored.

Commentary by Dr. Valentin Fuster
2013;():V001T04A020. doi:10.1115/IPACK2013-73263.

For the next generation of high performance computers, the new challenges are to shorten the distance for transporting data (to accelerate the transfer of information) between multi-microprocessors and memories, and to cool these electronic components despite the increased heat flux that results from increased transistor density. Recent technological advances show a tendency for the development of 3D integrated circuit stacked architectures with interlayer cooling (multi-microchannels in the silicon layers). However, huge challenges exist in such design/concept, i.e. flow distribution to hundreds microchannels distributed in the different interlayers, thermo-hydrodynamic and geometrical limitations, manufacturing etc. 3D-ICs with interlayer cooling are still about a decade away, so a viable shorter term goal is 3D stacks with backside cooling, taking advantage of Si layers now able to be thineer down to only 50 μm thickness. Thus, the present work presents thermo-hydrodynamic simulations for 3D stacks considering only a backside cooler, which simplifies considerably the assembly and guarantees a high level of reliability. In summary, the results showed that this concept is thermally feasible and potentially that interlayer microchannels (between stacks) will not be necessary.

Topics: Microchannels
Commentary by Dr. Valentin Fuster
2013;():V001T04A021. doi:10.1115/IPACK2013-73264.

Transient modeling and control of two-phase on-chip microevaporator cold plates of a liquid pump cooling cycle is studied. The purpose is to cool down multiple micro-processors in parallel and their auxiliary electronics (memories, DC/DC converters, etc.) in series. The cooling system is composed of multiple on-chip microevaporators in parallel, a condenser, a liquid accumulator, a liquid pump and all piping joining these components. In order to achieve high heat transfer and chip temperature uniformity, two-phase flow of HFC134a is considered for the coolant. The dynamics of the system are relevant aspects to be studied since the heat dissipated by the microprocessors is changing continuously. Thus, a new simulation code has been developed here to emulate the operation during transients. Such transient simulations allow us to verify whether critical heat flux (CHF) conditions are reached during heat load disturbances and to track the available heat at the condenser for energy recovery purposes.

Presently, a case study with four microprocessors cooled in parallel flow is simulated considering different levels of uniform heat flux (36, 30, 25 and 10 Wcm−2), which showed the robustness of the predictive-corrective solver used. For a desired exit mixing vapor quality of 30%, at an inlet pressure and subcooling of respectively 16 bar (saturation temperature of 57.9 °C) and 2 K, the resulting distribution of the mass flow rates in the microevaporators were 3.6, 4.0, 4.5 and 7.4 kg/h (largest flow rate for lowest heat load) and the total pressure drop over the entire section was 0.6 kPa. The CHF and maximum chip temperature remained below of the critical limits. Preliminary comparisons with experimental tests showed errors in the predictions of mean chip temperature and mixing vapor quality to be within ±10%.

Commentary by Dr. Valentin Fuster
2013;():V001T04A022. doi:10.1115/IPACK2013-73275.

Wave soldering process with a simple model has been studied numerically. Wave soldering process is one of major soldering process used in the manufacture of electronics. The purpose of this study is to clarify how a lifting velocity and an arrangement of parts affect the solder volume on the joint after wave soldering process. Open source computational fluid dynamics software, OpenFOAM, is used. Solder is assumed to be kept at the constant temperature over the melting point. Flow of melting solder and surrounding air is simulated and the dynamic movement of the interface between two fluids is captured using VOF method. Two dimensional arrangements of the parts were adopted. The dynamic movement of the solder surface is visualized from numerical results. The size of a rear land affects the solder volume on the front parts. It is confirmed that the changes of the volume is closely related to the solder surface configuration at the moment of the detachment from the solder bath.

Commentary by Dr. Valentin Fuster
2013;():V001T04A023. doi:10.1115/IPACK2013-73276.

This study concerns cooling of electronic components of intense background heat flux with one ultra intense hot spot (e.g. 1000 Wcm−2 on a footprint of 1 cm × 1 cm with 5000 Wcm−2 applied to a 0.02 cm × 0.02 cm region at the center). To manage these extreme heat fluxes and consequently surpass the thermal-hydrodynamic challenges and design paradigms, for example as specified in a recent DARPA request for proposals (Intrachip/Interchip Enhanced Cooling Fundamentals - ICECool Fundamentals [1]), on-chip two-phase multi-microchannel cooling integrated with a superlattice (SL) thin-film thermoeletric cooling (TEC) technology was investigated via computer simulations.

The simulations showed that increasing TEC electrical current results in greater enhancement of heat flow through the TEC, but at high currents this benefit is offset by a net addition of heat to the system, which must also be evacuated by the microchannels. When optimized, a minimum peak junction temperature of about 86 °C for a current of about 8 A was found, which represented a reduction of about 4 °C from a maximum allowed 90 °C at the ultra-intense hot-spot, thus potentially significantly capable of exceeding the DARPA [1] requirement, due to the embedded SL TEC within the microevaporator (ME) structure.

Commentary by Dr. Valentin Fuster
2013;():V001T04A024. doi:10.1115/IPACK2013-73305.

The development of light-emitting diode (LED) technology has resulted in widespread solid state lighting use in consumer and industrial applications. Previous researchers have shown that LEDs from the same manufacturer and operating under same use-condition may have significantly different degradation behavior. Applications of LEDs to safety critical and harsh environment applications necessitate the characterization of failure mechanisms and modes. This paper focuses on a prognostic health management (PHM) method based on the measurement of forward voltage and forward current of bare LED under harsh environment. In this paper experiments have been done on single LEDs subjected to combined temperature-humidity environment of 85°C, 85% relative humidity. Pulse width modulation (PWM) control method has been employed to drive the bare LED in order to reduce the heat effect caused by forward current and high frequency (300Hz). A data acquisition system has been used to measure the peak forward voltage and forward current. Test to failure (luminous flux drops to 70 percent) data has been measured to study the effects of high temperature and humid environment loadings on the bare LEDs. A solid state cooling method with a peltier cooler has been used to control the temperature of the LED in the integrating sphere when taking the measurement of luminous flux. The shift of forward voltage forward current curve and lumen degradation has been recorded to help build the failure model and predict the remaining useful life. Particle filter has been employed to assess the remaining useful life (RUL) of the bare LED. Model predictions of RUL have been correlated with experimental data. Results show that prediction of remaining useful life of LEDs, made by the particle filter model works with acceptable error-bounds. The presented method can be employed to predict the failure of LED caused by thermal and humid stresses.

Commentary by Dr. Valentin Fuster
2013;():V001T04A025. doi:10.1115/IPACK2013-73309.

Electronic systems may be subjected to prolonged and intermittent periods of storage prior to deployment or usage. Prior studies have shown that leadfree solder interconnects show measurable degradation in the mechanical properties even after brief exposures to high temperature. In this paper, a method has been developed for the determining equivalent storage time to produce identical damage at a different temperature. Electronics subjected to accelerated tests often have a well-defined thermal profile for a specified period of time. Quantification of the thermal profile in field deployed electronics may be often difficult because of variance in the environment conditions and usage profile. There is need for tools and techniques to quantify damage in deployed systems in absence of macro-indicators of damage without knowledge of prior stress history. Approach for mapping damage in leadfree second-level interconnects under between thermal conditions is new. High reliability applications such as avionics and missile systems may be often exposed to long periods of storage prior to deployment. Effect of storage at different temperature conditions can be mapped using the presented approach. A framework has been developed to investigate the system state and estimate the remaining useful life of solder ball subjected to a variety of isothermal aging conditions including 60°C, 75°C and 125°C for periods of time between 1-week and 4-week. Data on damage precursors has been collected and analyzed to derive physics based damage mapping relationships for aging. Mathematical relationships have been derived for the damage mapping to various thermal storage environments to facilitate determining appropriate time-temperature combination to reach a particular level of damage state. Activation energy for the leading indicators of failure is also computed. Specific damage proxies examined include the phase-growth indicator and the intermetallic thickness. The viability of the approach has been demonstrated for leadfree test assemblies subjected to multiple thermal aging at 60° C, 75°C and 125°C. Damage mapping relationships are derived from data based on the two separate leading indicators.

Commentary by Dr. Valentin Fuster

Multi-Physics Based Reliability

2013;():V001T05A001. doi:10.1115/IPACK2013-73091.

The reliability and lifetime of micro-joints on printed circuit boards (PCBs) is significantly affected by fatigue processes, including fatigue crack initiation and propagation to failure. Accordingly, the industries producing electronic devices and components strongly desire the development of a new nondestructive inspection technology, which detects micro-cracks appearing as thermal fatigue fractures in these joints. Accordingly, the authors have demonstrated that the micro-cracks in the micro-solder joints can be observed using the SP-μCT synchrotron X-ray micro tomography system. However, in order for such solder joint micro-cracks to be observable by SP-μCT, the observation object must have a diameter of less than roughly 1 mm. In this investigation, we applied a synchrotron radiation X-ray laminography system to three-dimensionally and nondestructively evaluate the fatigue crack propagation process in flip chip solder micro-joints. X-ray laminography is a technique for nondestructively observing planar objects. The optical system developed for use in X-ray laminography was constructed to provide the rotation stage with a 20° tilt from the horizontally incident X-ray beam. For this reason, X-rays were sufficiently transmitted through the planar object, in all directions. The observed specimens had a flip chip structure, in which a 10.04 mm square LSI chip is connected to a 52.55 mm (length) × 30.0 mm (width) FR-4 substrate by 120 μm diameter Sn-3.0wt%Ag-0.5wt%Cu lead-free solder bumps. A thermal cycle test was carried out, and specimens were collected at fixed cycle numbers. The same solder joints were observed successively using the synchrotron radiation X-ray laminography system at beamline BL20XU at SPring-8, the largest synchrotron radiation facility in Japan. An X-ray beam energy of 29.0 keV was selected to obtain laminography images with high contrast among component. The obtained laminography images clearly show the evolution of cracks, voids, and the Ag3Sn phase due to the thermal cyclic loading of the solder joints. In addition, the surface area of the same fatigue cracks was also measured, to quantify the crack propagation process. However, the surface area change measured by laminography differed from the crack propagation results obtained by standard SP-μCT. This difference may be due to an inability to observe some micro-cracks, due to crack closure to beneath than the detection limit of synchrotron radiation X-ray laminography. Consequently, these results demonstrate the possibility that nondestructive observation of fatigue cracks in the solder bumps on a large size electronic substrate by synchrotron radiation X-ray laminography, although its detection ability for narrow cracks may be limited, compared to SP-μCT.

Commentary by Dr. Valentin Fuster
2013;():V001T05A002. doi:10.1115/IPACK2013-73110.

This paper presents the characterization of the crack growth rate of Sn-4.0wt.%Ag-0.5wt.%Cu (SAC405) solder joints under drop impact. Several actual ChipArray® BGA (CTBGA) packages were cross-sectioned, polished and used as the test vehicles. The ball drop tests were performed using a specially-designed tester. The drop impact from the drop ball induces bending in the PCB, which damages the solder joints. The crack lengths in the solder joints were measured after every five drops using microscope imaging. Crack growth rates were calculated from the test results. Insight into the crack growth rate in solder joints under drop impact is provided. The direct cyclic approach for low-cycle fatigue analysis in ABAQUS was used to simulate the crack growth in the solder joints.

Commentary by Dr. Valentin Fuster
2013;():V001T05A003. doi:10.1115/IPACK2013-73126.

Numerical methods such as the finite element method (FEM) have been used to evaluate the reliability of electronic packages. The accuracy of the analyses should be verified by some experimental measurements. In this study, we evaluated the thermal strain of a test chip for three-dimensional stacked integrated circuits (3D SIC) with both measurement and an analysis. First, the distribution of thermal strain on the cross-section of a test chip was measured using scanning electron microscope (SEM) and the digital image correlation. Then, the distribution of strain of the test chip was also analyzed by the FEM considering the viscoelastic material properties of underfill (UF) resin measured with the stress relaxation test and the elastic-plastic material properties of components measured with the nano-indentation tests. The accuracy of the nonlinear finite element analysis was verified using the strain measurements with the SEM-DICM.

A test specimen for the 3D SIC packages was built and cut out a part of the test specimen and polished its cross-section. We took digital images using a SEM (FEI Quanta 200) to measure the strain distributions on the cross-section of a specimen by the DICM. The specimen was subjected to thermal loading in a heat chamber. The temperature in the chamber was raised from 30° C to 130°C.

The FE analyses were carried out using MSC.Marc™. We assumed the initial temperature of the analysis to be 150°C, which was the curing temperature of the UF resin, and decreased the temperature to 30°C during 100 seconds. Then, the temperature was raised up to 130°C, which is the same with the experiment. We compared the numerical result with the measurement and modified the model of the FE analyses.

Commentary by Dr. Valentin Fuster
2013;():V001T05A004. doi:10.1115/IPACK2013-73143.

In automotive power electronics packages, conventional thermal interface materials such as greases, gels, and phase change materials pose bottlenecks to heat removal and are also associated with reliability concerns. There is an industry trend towards high thermal performance bonded interfaces. However, due to coefficient of thermal expansion mismatches between materials/layers and resultant thermomechanical stresses, adhesive and cohesive fractures could occur, posing a problem from a reliability standpoint. These defects manifest themselves in increased thermal resistance in the package.

The objective of this research is to investigate and improve the thermal performance and reliability of emerging bonded interface materials for power electronics packaging applications. We present results for thermal performance and reliability of bonded interfaces based on thermoplastic (polyamide) adhesive, with embedded near-vertical aligned carbon fibers, as well as sintered silver material. The results for these two materials are compared to conventional lead-based (Sn63Pb37) bonded interfaces. These materials were bonded between 50.8-mm × 50.8-mm cross-sectional footprint silicon nitride substrates and copper base plate samples. Samples of the substrate/base plate bonded assembly underwent thermal cycling from −40°C to 150°C according to Joint Electron Devices Engineering Council standard Number 22-A104D for up to 2,000 cycles. The dwell time of the cycle was 10 minutes and the ramp rate was 5°C/minute. Damage was monitored every 100 cycles by acoustic microscopy as an indicator of an increase in thermal resistance of the interface layer. The acoustic microscopic images of the bonded interfaces after 2,000 thermal cycles showed that thermoplastics with embedded carbon fibers performed quite well with no defects, whereas interface delamination occurred in the case of sintered silver material. Both these materials showed a superior bond quality as compared to the lead-based solder interface even after 1,000 thermal cycles.

Commentary by Dr. Valentin Fuster
2013;():V001T05A005. doi:10.1115/IPACK2013-73147.

In the present study, a new material, ruthenium whose lattice mismatch against copper is about 6%, was used as the seed layer of electroplated copper thin-film interconnections for semiconductor devices. The crystallinity of the copper thin-film interconnections was evaluated through an EBSD (Electron Back-scattered Diffraction) method and it is found that the crystallinity of them is improved drastically compared with those electroplated on the copper seed. The resistance and electro migration (EM) tolerance of the copper interconnections are also improved a lot compared with the interconnections electroplated on copper seed. Based on these results, a new guideline to design highly reliable electroplated copper thin-film interconnection has been established.

Topics: Thin films , Copper
Commentary by Dr. Valentin Fuster
2013;():V001T05A006. doi:10.1115/IPACK2013-73148.

Electroplated copper thin films have started to be applied to the interconnection material in TSV structures because of its low electric resistivity and high thermal conductivity. However, the electrical resistivity of the electroplated copper thin films surrounded by SiO2 was found to vary drastically comparing with those of the conventional bulk material. This was because that the electroplated copper thin films consisted of grains with low crystallinity and grain boundaries with high defect density. Thus, in this study, both the crystallinity and electrical properties of the electroplated copper thin films embedded in the TSV structure was evaluated quantitatively by changing the electroplating conditions and thermal history after the electroplating. It was observed that many voids and hillocks appeared in the TSV structures after the high temperature annealing which was introduced for improving the crystallinity of the electroplated films. Therefore, it is very important to evaluate the crystallographic quality of the electroplated copper thin films after electroplating to assure both the mechanical and electrical properties of the films.

Topics: Thin films , Copper
Commentary by Dr. Valentin Fuster
2013;():V001T05A007. doi:10.1115/IPACK2013-73175.

RF-MEMS devices area complex systems governed by the interaction of a variety of forces, including electrostatics, solid deformation, fluid damping and contact. The performance and reliability of these devices is strongly dependent on device geometry and composition, and also on material microstructure and related properties. In this paper, we consider multiscale simulation of RF MEMS switched. At the device level, we introduce a comprehensive integrated numerical framework to simulate the major governing physics and their interactions. At the micron scale, we develop a mesoscale contact model to describe the history-dependent force-displacement relationships in terms of the surface roughness, the long-range attractive interaction between the two surfaces, and the repulsive interaction between contacting asperities (including elastic and plastic deformation). The inputs to this model are obtained from atomic level simulations and nanoscale surface topography characterization. The mesoscale contact model is integrated in the device-level simulation to predict the pull-in and pull-out behavior of these switches. The uncertainties associated with the simulation are quantified and propagated using a non-intrusive collocation method based on generalized Polynomial Chaos (gPC) expansions. With such a framework, we are able to predict the PDFs of pull-in and pull-out voltage, identify the critical factors that have the most influence on the quantities of interest, and therefore guide resource allocation and risk-informed decision-making.

Commentary by Dr. Valentin Fuster
2013;():V001T05A008. doi:10.1115/IPACK2013-73230.

The microstructure, mechanical response, and failure behavior of lead free solder joints in electronic assemblies are constantly evolving when exposed to isothermal aging and/or thermal cycling environments. Traditional finite element based predictions for solder joint reliability during thermal cycling accelerated life testing are based on solder constitutive equations (e.g. Anand viscoplastic model) and failure models (e.g. energy dissipation per cycle model) that do not evolve with material aging. Thus, there will be significant errors in the calculations with lead free SAC alloys that illustrate dramatic aging phenomena. In this research, we have developed a new reliability prediction procedure that utilizes constitutive relations and failure criteria that incorporate aging effects, and then validated the new approach through correlation with thermal cycling accelerated life testing experimental data.

As a part of this work, a revised set off Anand viscoplastic stress-strain relations for solder have been developed that included material parameters that evolve with the thermal history of the solder material. The effects of aging on the nine Anand model parameters have been determined as a function of aging temperature and aging time, and the revised Anand constitutive equations with evolving material parameters have been implemented in commercial finite element codes. In addition, new aging aware failure criteria have been developed based on fatigue data for lead free solder uniaxial specimens that were aged at elevated temperature for various durations prior to mechanical cycling. Using the measured fatigue data, mathematical expressions have been developed for the evolution of the solder fatigue failure criterion constants with aging, both for Coffin-Manson (strain-based) and Morrow-Darveaux (dissipated energy based) type fatigue criteria. Similar to the findings for mechanical/constitutive behavior, our results show that the failure data and associated fatigue models for solder joints are affected significantly by isothermal aging prior to cycling.

After development of the tools needed to include aging effects in solder joint reliability models, we have then applied these approaches to predict reliability of PBGA components attached to FR-4 printed circuit boards that were subjected to thermal cycling. Finite element modeling was performed to predict the stress-strain histories during thermal cycling of both non-aged and aged PBGA assemblies, where the aging at constant temperature occurred before the assemblies were subjected to thermal cycling. The results from the finite element calculations were then combined with the aging aware fatigue models to estimate the reliability (cycles to failure) for the aged and non-aged assemblies. As expected, the predictions show significant degradations in the solder joint life for assemblies that had been pre-aged before thermal cycling.

To validate our new reliability models, an extensive test matrix of thermal cycling reliability testing has been performed using a test vehicle incorporating several sizes of fine pitch PBGA daisy chain components. Before thermal cycling began, the assembled test boards were divided up into test groups that were subjected to several sets of aging conditions (preconditioning) including different aging temperatures (T = 25, 55, 85 and 125 C) and different aging times (no aging, and 6 and 12 months). After aging, the assemblies were subjected to thermal cycling (−40 to +125 C) until failure occurred. As with the finite element predictions, the Weibull data failure plots have demonstrated that the thermal cycling reliabilities of pre-aged assemblies were significantly less than those of non-aged assemblies. Good correlation was obtained between our new reliability modeling procedure that includes aging and the measured solder joint reliability data.

Topics: Reliability
Commentary by Dr. Valentin Fuster
2013;():V001T05A009. doi:10.1115/IPACK2013-73232.

Traditional finite element based predictions for solder joint reliability during thermal cycling accelerated life testing are based on solder constitutive equations (e.g. Anand viscoplastic model) and failure models (e.g. energy dissipation per cycle model) that do not evolve with material aging. Thus, there will be significant errors in the calculations with lead free SAC alloys that illustrate dramatic aging phenomena. In this study, we have developed a revised set of Anand viscoplastic stress-strain relations for solder that include material parameters that evolve with the thermal history of the solder material. The effects of aging on the nine Anand model parameters have been examined by performing stress-strain tests on SAC305 samples that were aged for various durations (0–6 months) at temperature of 100 C. The stress-strain data were measured at three strain rates (.001, .0001, and .00001 1/sec) and five temperatures (25, 50, 75, 100, and 125 C). The mechanical tests have been performed using both water quenched (WQ) and reflowed (RF) samples (two unique specimen microstructures). In the case of the water quenched samples, there is rapid microstructural transitioning during the brief time that occurs between placing molten solder into the glass tubes and immersing the tubes in water bath. On the other hand, the reflowed samples are first cooled by water quenching, and then sent through a reflow oven to re-melt the solder in the tubes and subject them to a desired temperature profile matching that used in PCB assembly.

As expected, the observed mechanical properties of water quenched samples were better (higher in magnitude) than the corresponding mechanical properties of the reflowed samples. Although the differences in elastic modulus between the water quenched and reflowed samples are small, significant differences are present for the yield and ultimate tensile stresses (for each aging condition). For both the water quenched and reflowed specimens, significant degradation of the mechanical properties has been observed with aging. Using the measured stress-strain and creep data, mathematical expressions have been developed for the evolution of the Anand model parameter with aging time. Our results show that 2 of the 9 constants remain essentially constant during aging, while the other 7 show large changes (30–70%) with up to 6 months of aging. The revised Anand constitutive equations for solder with aging effects have also been incorporated into commercial finite element codes (ANSYS and ABAQUS).

Commentary by Dr. Valentin Fuster
2013;():V001T05A010. doi:10.1115/IPACK2013-73233.

In this paper, we have explored the response of bipolar junction transistors (BJT) to the controlled application of mechanical stress. Mechanical strains and stresses are developed during the fabrication, assembly and packaging of the integrated circuit (IC) chips. Due to these stresses and strains, it has been observed by many researchers that changes can occur in the electrical performance of both analog and digital devices. Stress-induced device parametric shifts affect the performance of analog circuits that depend upon precise matching of bipolar and/or MOS devices, and can cause them to operate out of specifications. In the past the authors have extensively investigated the stress effects on resistors embedded on integrated chips and were successful in characterizing die stresses for various packaging architectures. We have also observed stress effects on diodes, field effect transistors (FETs), van der Pauw structures and CMOS sensor arrays. In this present work, the stress dependence of the electrical behavior of bipolar transistors has been investigated. Test structures have been utilized to characterize the stress sensitivity of vertical bipolar devices fabricated on (100) silicon wafers. In the experiments, uniaxial normal stresses were applied to silicon wafer strips using a four-point-bending fixture. An approximate theory has also been developed for stress-induced changes in the current gain of bipolar junction transistors. Both the theoretical and experimental results show similar trend for DC current gain vs. stress plots. Multi-Physics based finite element simulations (coupled electro-mechanical-thermal) have been performed to understand the device level mechanisms that cause the stress induced changes in the BJTs and also to characterize and model stress dependence of fundamental silicon material parameters such as bandgap, intrinsic carrier concentration, and electron/hole mobilities. In the future, the developed formulations can be applied to theoretically optimize transistor design, placement, orientation, and processing to minimize the impact of fabrication and packaging induced die stresses.

Topics: Stress , Transistors
Commentary by Dr. Valentin Fuster
2013;():V001T05A011. doi:10.1115/IPACK2013-73240.

Solder joints in electronic assemblies are typically subjected to thermal cycling, either in actual application or in accelerated life testing used for qualification. Mismatches in the thermal expansion coefficients of the assembly materials cause the solder joints to be subjected to cyclic (positive and negative) mechanical strains and stresses. This cyclic loading leads to thermomechanical fatigue damage that involves damage accumulation, crack initiation, crack propagation, and failure. In addition, the microstructure, mechanical response, and failure behavior of lead free solder joints in electronic assemblies are constantly evolving when exposed to isothermal aging and/or thermal cycling environments. While the effects of aging on solder constitutive behavior (stress-strain and creep) have been examined in some detail, there have been no prior studies on the effects of aging on solder failure and fatigue behavior. Aging leads to both grain and phase coarsening, and can cause recrystallization at Sn grain boundaries. Such changes are closely tied to the damage that occurs during cyclic mechanical loading.

In this investigation, we have examined the effects of aging on the cyclic stress-strain behavior and fatigue life of lead free solders. Uniaxial solder test specimens (SAC105 and SAC305) have been prepared and subjected to cyclic stress/strain loading at different aging conditions. A four-parameter hyperbolic tangent empirical model has been used to fit the entire cyclic stress-strain curve and the hysteresis loop size (area) was calculated using definite integration for a given strain limit. This area represents the energy dissipated per cycle, which is correlated to the damage accumulation in the joint. Using the recorded cyclic stress-strain curves, the evolution of the solder hysteresis loops with aging have been characterized and empirically modeled. Similar to solder stress-strain and creep behavior, there is a strong effect of aging on the hysteresis loop size (and thus the rate of damage accumulation) in the solder specimens.

Fatigue experiments were also performed, where the uniaxial specimens were subjected to cyclic loading over a particular strain range until failure. Fatigue failure in the experiments was defined to occur when there was a 50% peak load drop during mechanical cycling. Prior to testing, the specimens were aged (preconditioned) at 125 °C for various aging times, and then the samples were subjected to cyclic loading at room temperature (25 °C). It was found that aging decreased the mechanical fatigue life, and the effects of aging on the peak load drop have been studied. It has also been observed that degradations in the fatigue/failure behavior of the lead free solders with aging are highly accelerated for lower silver content alloys (e.g., SAC105). Various empirical failure criteria such as the Coffin-Manson model and the Morrow model have been used to fit the measured data, and the parameters in the models have been determined as a function of the aging conditions.

Commentary by Dr. Valentin Fuster
2013;():V001T05A012. doi:10.1115/IPACK2013-73246.

Industry migration to lead-free solders has resulted in a proliferation of a wide variety of solder alloy compositions. The most popular amongst these are the Tin-Silver-Copper (Sn-Ag-Cu or SAC) family of alloys like SAC105, SAC305 etc. Recent studies have highlighted the detrimental effects of isothermal aging on the material properties of these alloys. SAC alloys have shown up to 50% reduction in their initial elastic modulus and ultimate tensile strength within a few months of elevated temperature aging. This phenomenon has posed a severe design challenge across the industry and remains a road-block in the migration to Pb-free. Multiple compositions with additives to SAC have been proposed to minimize the effect of aging and creep while maintaining the melting temperatures, strength and cost at par with SAC. Innolot is a newly developed high-temperature, high-performance lead-free substitute by InnoRel™ targeting the automotive electronics segment. Innolot contains Nickel (Ni), Antimony (Sb) and Bismuth (Bi) in small proportions in addition to Sn, Ag and Cu. The alloy has demonstrated enhanced reliability under thermal cycling as compared to SAC alloys. In this paper, the high strain rate material properties of Innolot have been evaluated as the alloy ages at an elevated temperature of 50°C. The strain rates chosen are in the range of 1–100 per-second which are typical at second level interconnects subjected to drop-shock environments. The strain rates and elevated aging temperature have been chosen also to correspond to prior tests conducted on SAC105 and SAC305 alloys at this research center. This paper presents a comparison of material properties and their degradation in the three alloys — SAC105, SAC305 and Innolot. Full field strain measurements have been accomplished with the use of high speed imaging in conjunction with Digital Image Correlation (DIC). Ramberg-Osgood non-linear model parameters have been determined to curve-fit through the experimental data. The parameters have been implemented in Abaqus FE model to obtain full-field stresses which correlates with contours obtained experimentally by DIC.

Commentary by Dr. Valentin Fuster
2013;():V001T05A013. doi:10.1115/IPACK2013-73248.

This paper discusses a numerical model for analysing the effects of mechanical stress on semiconductor devices. In other words, drift-diffusion device simulation is conducted using a physical model incorporating the effects of mechanical stress. Then, each impact of the stress-induced physical phenomena is analysed. In our previous study, three physical phenomena that were attributed to mechanical stress have been modeled in our electron mobility model, i.e., the changes in relative population, the momentum relaxation time and the effective mass of electrons in conduction-band valleys. In addition, in this study, the stress-induced change of intrinsic carrier density is modeled. Stress-induce variations of drain current characteristics on n-type Metal Oxide Semiconductor Field Effect Transistors (nMOSFETs) are evaluated using a drift-diffusion device simulator including above mentioned physical models. It is demonstrated that the impact of stress-induced change of intrinsic carrier density is small for our evaluated nMOSFETs.

Topics: Density , Simulation , Stress
Commentary by Dr. Valentin Fuster
2013;():V001T05A014. doi:10.1115/IPACK2013-73251.

Electronics in high reliability applications may be stored for extended periods of time prior to deployment. Prior studies have shown the elastic modulus and ultimate tensile strength of the SAC leadfree alloys reduces under prolonged exposure to high temperatures [Zhang 2009]. The thermal cycle magnitudes may vary over the lifetime of the product. Long-life systems may be re-deployed several times over the use life of the product. Previously, the authors have identified damage pre-cursors for correlation of the damage progression with the microstructural evolution of damage in second level interconnects [Lall 2004a-d, 2005a-b, 2006a-f, 2007a-e, 2008a-f, 2009a-d, 2010a-j]. Leadfree assemblies with Sn3Ag0.5Cu solder have been subjected to variety of thermal aging conditions including 60°C, 85°C and 125°C for periods of time between 1-week and 2-months, thermal cycling from −55°C to 125°C, −40°C to 95°C and 3°C to 100°C. The presented methodology uses leading indicators of failure based on microstructural evolution of damage to identify accrued damage in electronic systems subjected to sequential stresses of thermal aging and thermal cycling. Damage equivalency relationships have been developed to map damage accrued in thermal aging to the reduction in thermo-mechanical cyclic life based on damage proxies. Accrued damage between different thermal cyclic magnitudes has also been mapped for from −55°C to 125°C, −40°C to 95°C and 3°C to 100°C thermal cycles. The presented method for interrogation of the accrued damage for the field deployed electronics, significantly prior to failure, may allow insight into the damage initiation and progression of the deployed system. The expected error with interrogation of system state and assessment of residual life has been quantified.

Topics: Electronics
Commentary by Dr. Valentin Fuster
2013;():V001T05A015. doi:10.1115/IPACK2013-73269.

The spatially varying magnetic field within a power electronics package contains information of the semiconductor junction temperature and the interconnect currents, temperature, displacement, and strain. The design of semiconductor interconnects for point field detector based high bandwidth current and strain sensing is investigated using finite element analysis (FEA) and verified by experimental results. High bandwidth (10MHz) current sensing was achieved by interconnect design based field shaping and concentration. A displacement sensing resolution of 0.6 μm was achieved by eddy current based high frequency field shaping. Design methodologies to achieve this multifunctional integration of sensing are the primary new contribution of this work.

Commentary by Dr. Valentin Fuster
2013;():V001T05A016. doi:10.1115/IPACK2013-73288.

Solid-state lighting (SSL) luminaires containing light emitting diodes (LEDs) have the potential of seeing excessive temperatures when being transported across country or being stored in non-climate controlled warehouses. They are also being used in outdoor applications in desert environments that see little or no humidity but will experience extremely high temperatures during the day. This makes it important to increase our understanding of what effects high temperature exposure for a prolonged period of time will have on the usability and survivability of these devices. The U.S. Department of Energy has made a long term commitment to advance the efficiency, understanding and development of solid-state lighting (SSL) and is making a strong push for the acceptance and use of SSL products to reduce overall energy consumption attributable to lighting.

Traditional light sources “burn out” at end-of-life. For an incandescent bulb, the lamp life is defined by B50 life. However, the LEDs have no filament to “burn”. The LEDs continually degrade and the light output decreases eventually below useful levels causing failure. Presently, the methods described in IES TM-21 are used to predict the L70 life of white LEDs from LM-80 test data. Several failure mechanisms may be active in a LED at a single time causing lumen depreciation. The underlying TM-21 Arrhenius Model may not capture the failure physics in presence of multiple failure mechanisms. Correlation of lumen maintenance with underlying physics of degradation at system-level is needed.

In this paper, a Kalman Filter and Extended Kalman Filters (EKF) have been used to develop a 70% Lumen Maintenance Life Prediction Model for LEDs used in SSL luminaires. This model can be used to calculate acceleration factors, evaluate failure-probability and identify ALT methodologies for reducing test time. Nine-thousand hour LM-80 test data for various LEDs have been used for model development. System state has been described in state space form using the measurement of the feature vector, velocity of the feature vector change and the acceleration of the feature vector change. System state at each future time has been computed based on the state space at preceding time step, system dynamics matrix, control vector, control matrix, measurement matrix, measured vector, process noise and measurement noise. The future state of the lumen depreciation has been estimated based on a second order Kalman Filter model and a Bayesian Framework. The measured state variable has been related to the underlying damage using physics-based models. Life prediction of L70 life for the LEDs used in SSL luminaires from KF and EKF based models have been compared with the TM-21 model predictions and experimental data.

Topics: Kalman filters
Commentary by Dr. Valentin Fuster
2013;():V001T05A017. doi:10.1115/IPACK2013-73308.

Escalation of the expense of gold has resulted in industry interest in use of copper as alternative wire bonds interconnect material. Copper wire has the advantage of lower price and comparable electrical resistance to gold wire. In this paper, 32-pin copper-aluminum wire bond chip scale packages are aged at three types of environment conditions separately. Environmental conditions included: 200°C for 10 days, 85°C and 85% RH for 8 weeks and −40°C to 125°C for 500 thermal cycles. The resistances of the wire bond are obtained every 24 hours for 200°C environment, every 7 days for 85C/85RH environment and every 5 days (50 thermal cycles) for the thermal cycling environment. A leading indicator has been developed in order to monitor the progression effect of the different thermal aging condition on the package and prognosticate remaining useful life based on the resistance spectroscopy. The Cu-Al wire bond resistance has been measured using a modified Wheatstone bridge. It has been shown previously that precise resistance spectroscopy is able to offer the failure of a leading indicator prior to the traditional definition of failure. The prognostic health management is qualified to be an efficient and accuracy tool for assessment of the remaining life of the wire bond. The ability to predict the remaining useful life of Cu-Al wire bond provides several advantages, including increasing safety by providing warning ahead of time before the failure.

Topics: Spectroscopy , Wire
Commentary by Dr. Valentin Fuster


2013;():V001T06A001. doi:10.1115/IPACK2013-73156.

A new highly sensitive strain measurement method has been developed by applying the strain-induced change of the electronic conductivity of CNTs. It is reported that most multi-walled carbon nanotubes (MWCNTs) show metallic conductivity and they are rather cheap comparing with single-walled carbon nanotubes (SWCNTs). However, it was found that the electric conductivity of MWCNTs changes drastically under uniaxial strain because of the drastic change of their band gap. Therefore, the authors have developed a highly sensitive strain sensor which can detect the local strain distribution by using MWCNTs. In order to design a new sensor using MWCNT, it is very important to control the shape of the MWCNTs under strain. Thus, a method for controlling the shape of the MWCNTs was developed by applying a chemical vapor deposition (CVD) technique. It was found that the shape of the grown MWCNT could be controlled by changing the average thickness of the catalyst and the deposition temperature of the MWCNT. The electrical resistance of the grown MWCNT changed almost linearly with the applied strain, and the maximum strain sensitivity obtained under the application of uniaxial strain was about 10%/1000-μstrain (gauge factor: 100). A two-dimensional strain sensor, which consists of area-arrayed fine bundles of MWCNTs, has been developed by applying MEMS technology. Under the application of compressive strain, the electric resistance was confirmed to increase almost linearly with the applied strain.

Commentary by Dr. Valentin Fuster
2013;():V001T06A002. doi:10.1115/IPACK2013-73222.

Wireless handheld communications has identified significant benefits of tuning that include fewer dropped calls, increased battery life and improved user experience. The tuning can be part of the antenna, power amplifier (PA), filtering, or part of a fully integrated radio front end (FE). RF MEMS tunable capacitors have been integrated with 0.18 μm RF HVCMOS to address the need for tuning in wireless communications. These integrated, MEMS tunable capacitors are hermetically encapsulated at the wafer level, but the integrity of the encapsulation must be maintained during BEOL operations. The BEOL operations include shipping and handling, passivation coat and cure, solder bumping (screen printed or electroplated), backside grinding (BSG), dicing, and pick and place.

In this paper we will describe, the flip chip packaging of the wafer level encapsulated MEMS devices including finite element analysis. The flip chip packaging of ASIC die is primarily concerned with solder bump reliability during such qualification stresses as temperature cycling and drop testing. The flip chip packaging of a wafer level encapsulated MEMS device has additional concerns that include encapsulation integrity and device package sensitivity. The die thickness, underfill, and encapsulation dimension have been varied to minimize the deflection and stress associated with the encapsulation. The primary failure mode associated with the overstress of the encapsulation is a cracked lid that will lead to the ingress of moisture and a rise in the cavity pressure from to atmospheric conditions. The failure can be detected by an increase in the MEMS switching time and frequency response or by a return to zero failure (RTZ) associated with device stiction. A low modulus and low CTE UF has been implemented for the lowest deflection and stress. The lowest deflection and stress is provided by eliminating the UF, but this is not feasible for the purpose of solder bump reliability.

In practice, the MEMS encapsulation is robust to the printed solder bumping process that includes placement and removal of the bump screen and the squeegee of solder past into the solder screen. The MEMS encapsulation is robust to the attachment and removal of BSG tape and the pressures associated with BSG. The final dicing operation has not demonstrated any detrimental impact on the MEMS encapsulation. The final demonstration of success is the assembly of the MEMS tunable capacitor die to a laminate substrate using lead-free solder and underfill.

Commentary by Dr. Valentin Fuster
2013;():V001T06A003. doi:10.1115/IPACK2013-73249.

Four-wire resistance characterization of van der Pauw stress sensors is discussed. Under the proper orientations and excitations, the output of the four-contact sensors can be shown to depend upon only the in-plane shear stress or the in-plane normal stress difference on (100) silicon. The other stress terms are cancelled out by the symmetry of the structure, and the measurements are inherently temperature compensated. In bridge-mode, each sensor requires only one measurement and produces an output voltage that is directly proportional to the shear stress or in-plane normal stress difference, and the sensitivity is 3.16 times that of the equivalent resistor sensors, just as in the normal van der Pauw mode. Experimental, theoretical, finite-difference and finite-element and simulation results are presented demonstrating the behavior of the sensor. The two sensors can be merged into one eight-contact device, or n- and p-tye sensors can be overlaid in standard IC processes. Similar results apply to sensors on (111) silicon.

Commentary by Dr. Valentin Fuster
2013;():V001T06A004. doi:10.1115/IPACK2013-73258.

This paper presents a strain transfer investigation for Surface Acoustic Wave (SAW) strain sensors. For evaluation, a SAW strain sensor is assembled with a pre-tested bond material for potentially high strain transfer on a test holder. The setup is stressed with an axially homogeneous strain up to 500 ppm. The strain transfer ratio is computed from the applied load, the reference measurements with foil strain gauge, and the measured SAW strain sensor signal. The strain transfer performance of the bond material is also investigated with respect to the temperature dependency in the range between 22 °C and 85 °C. At this elevated temperatures an average strain transfer ratio of 0.606 ± 0.7% was measured. Mechanical load cycling tests up to 1000 cycles are used for the evaluation of the elastic fatigue of the bond material. The effects of mechanical load cycling and aging of the bond layer are analyzed with the SAW strain sensor response. After 1000 mechanical load cycles the transferred strain into the SAW strain sensor is 0.582 ± 0.153%. Finally, the experimental results are compared with the results of a 3D FEM simulation which are deviating less than 10%.

Commentary by Dr. Valentin Fuster
2013;():V001T06A005. doi:10.1115/IPACK2013-73290.

A number of small electronic devices benefit from micro-scale low temperature operation. Recently we have developed micro cryogenic coolers (MCCs) using a low-pressure, mixed-refrigerant Joule-Thomson cycle. The cryocoolers utilizes a MEMS-enabled gas compressor coupled to a micro cold stage. Two cold stages have been developed: one which uses a fiber-enabled heat exchanger assembled to a micro-machined throttling valve, and another which uses a MEMS-based heat exchanger. A microcompressor has been developed which uses MEMS-based check valves coupled to a membrane, which is actuated with a mechanically amplified piezoelectric amplifier. The compressor measures a volume 15 mL, can generate a pressure ratio of 6:1 and a maximum flow-rate of 60 standard mL/min. The complete cryocooler has reached low temperatures of 177 K, although temperature instability has been an issue, due to 2-phase flow through the micro-channels. This paper will cover the development and testing of the micro cryogenic cooler, as well as an analysis of the micro channel flow. A proper understanding of the micro-channel flow allows us to design refrigerant mixtures to improve the cooling power, and modify the cooler to eliminate temperature instabilities.

Topics: Refrigerants , Coolers
Commentary by Dr. Valentin Fuster
2013;():V001T06A006. doi:10.1115/IPACK2013-73310.

This paper describes the effects of specimen size, focused ion beam (FIB) induced damage, and annealing on the mechanical properties of sub-100nm-sized silicon (Si) nanowires (NWs) that were evaluated by means of uniaxial tensile testing. Si NWs were made from silicon-on-nothing membranes that were produced by deep reactive ion etching trench fabrication and ultra-high vacuum (UHV) annealing. FIB system’s probe manipulation and film deposition functions were used to fabricate Si NWs and to directly bond them onto the sample stage of a tensile test device. The mean Young’s modulus and the mean strength of FIB-damaged NWs were 131.0 GPa and 5.6 GPa, respectively. After 700°C and 1000°C annealing in UHV, the mean Young’s modulus was increased to 168.1 GPa and 169.4 GPa, respectively, due to recrystallization by annealing. However, the mean strength was decreased to 4.1 GPa and 4.0 GPa, respectively. These experimental facts imply that the crystallinity of NWs improved, but the morphology was degraded. The surface degradation was probably related to gallium ion implantation into NWs surface during FIB fabrication.

Commentary by Dr. Valentin Fuster
2013;():V001T06A007. doi:10.1115/IPACK2013-73317.

The level of stress in silicon as a result of applying Cu-Sn SLID wafer level bonding to hermetically encapsulate a high-performance infrared bolometer device was studied. Transistors are present in the read out integrated circuit (ROIC) of the device and some are located below the bond frame. Test vehicles were assembled using Cu-Sn SLID bonding and micro-Raman spectroscopy was applied on cross sectioned samples to measure stress in the silicon near the bond frame. The test vehicles contained cavities and the bulging of the structures was studied using white light interferometry. The test vehicles were thermally stressed to study possible effects of the treatments on the level of stress in the silicon. Finite element modeling was performed to support the understanding of the various observations. The measurements indicated levels of stress in the silicon that can affect transistors in regions up to 15 μm below the bond frame. The observed levels of stress corresponded well with the performed modeling. However, no noticeable effect was found for the ROIC used in this work. The specific technology used for the fabrication of the ROIC of a MEMS device is thus decisive. The level of stress did not appear to change as a result of the imposed thermal stress. The level of stress caused by the bond frame can be expected to stay constant throughout the lifetime of a device.

Commentary by Dr. Valentin Fuster
2013;():V001T06A008. doi:10.1115/IPACK2013-73324.

This paper reports the mechanical properties of single crystal silicon surface changed with hydrogen atoms trapped by underwater boiling treatment. Nanoindentaion test using a Berkovich indenter in six different indentation loads ranging from 100 μN to 1000 μN was conducted to obtain the load-displacement curve. The energy dissipated in plastic deformation, i.e. plasticity energy, during indentation on silicon wafers with different carrier concentration (undoped, lightly and heavily boron doped silicon) were compared. After boiling treatment, increment in the plasticity energy was observed on silicon containing boron. This result suggests that hydrogen atoms trapped inside silicon enhanced dislocation mobility leading to larger plastic deformation.

Commentary by Dr. Valentin Fuster

Materials and Processes

2013;():V001T07A001. doi:10.1115/IPACK2013-73059.

Laser beam shaping techniques are important to optimize a large number of laser-material processing applications and laser-material interaction studies. The authors have developed a novel fluidic laser beam shaper (FLBS) with merits such as flexiblility, versatility and low cost. This work presents a fundamentally new approach for laser beam shaping by using FLBS. A Gaussian beam profile is transformed to a flat top beam and annular beam profile in the focal plane. The shaped laser beam is used for laser drilling to investigate the influence of the laser intensity profile in laser processing. The paper concludes with suggestions for future research and potential applications for further the work.

Topics: Lasers , Laser beams
Commentary by Dr. Valentin Fuster
2013;():V001T07A002. doi:10.1115/IPACK2013-73060.

Laser drilling of silicon carbide (SiC) wafer in air (dry ablation) and underwater by using ns pulsed infrared (1064 nm) Nd: YAG laser is investigated. In order to suggest optimal parameters of via processing in SiC wafer, the effects of pulse number, laser fluence, water film thickness, and focus position are evaluated. As compared with dry ablation vias, decreasing etching rate, increasing via diameter, and generation of cracks in high-energy regime are observed in liquid-assisted processing. However, it is found that it can create vias without debris, HAZ, cracks. Also, optimal parameter set for infrared pulse laser processing under water is found to be the laser fluence of less than 10 J/cm2 and water thickness of 1mm.

Topics: Lasers
Commentary by Dr. Valentin Fuster
2013;():V001T07A003. doi:10.1115/IPACK2013-73079.

Solder microbumps are widely applied in 3D packages using fine-pitch Cu-pillar or Through Silicon Via (TSV) technologies. Due to the small scale of these joints, the volumetric proportion of intermetallic compounds (IMCs) formed in these joints is typically very high. This renders microbump-joints much more brittle compared to traditional solder joints (flip-chip or BGA). In particular, the reliability of microbumps during a drop, which corresponds to a mixed-mode high strain rate fracture test, is of substantial concern because of the brittleness of these joints. This study reports on the fracture mechanics and mechanisms of simulated microbumps, which have similar thicknesses and IMC contents as actual microbumps, but are laterally scaled up to constitute valid fracture mechanics samples. Compact mixed mode (CMM) specimens with adhesive solder joints (Sn-3.0%Ag-0.5%Cu) between massive Cu substrates were utilized to measure the fracture properties. The fracture behavior was characterized as a function of joint thickness and proportion of IMC, the latter being controlled by adjusting the dwell time and aging time. It was found that the fracture toughness GC decreased monotonically with joint thickness (hJoint) due to increased triaxial constraint imposed by the substrates. With aging, the proportion of IMC thickness relative to the joint thickness (2hIMC/hJoint) increased, as did hJoint. This resulted in lower GC values. The associated mechanisms of fracture that led to these effects are discussed.

Commentary by Dr. Valentin Fuster
2013;():V001T07A004. doi:10.1115/IPACK2013-73113.

Recent electronic device packaging, for instance, Chip size package (CSP) has a bonded structure of IC chip and polymers, and delamination occurs frequently at the interface between IC and a resin. Furthermore, thermal stresses which are caused by a temperature variation in the bonding process of CSP and heat cycles for environment temperature will influence on the strength of interface. In the present paper, the delamination test for specimens with different bonding areas and geometries is carried out to investigate the strength of multi-layered joints. In particular, a silicon wafer is joined with a silicon-on-sapphire (SOS) plate by a resin. The SOS is composed of silicon film, SiO2 film and sapphire plate. The thicknesses of silicon film, SiO2 film and sapphire plate are 0.45μm, 0.2μm, 600μm, respectively. The joining strength in silicon, resin and SOS joints with triangular and rectangular bonding area is investigated. The triangular and rectangular shape bonding areas are 3mm2 and 12mm2, respectively. The bonded specimens are prepared under different cooling rate. Load is applied to the specimen so as to delaminate at the interfaces of SiO2 film and sapphire. From the delamination test, it is found that residual thermal stress and the geometry of bonding area affect the strength of interface. In the case of the triangular area specimen, delamination occurs at the interface between SiO2 film and sapphire plate in the silicon-resin-SOS specimen. The nominal stress for delamination is about 1.99MPa. In the case of rectangular bonding area specimen, delamination occurs at the interface between SiO2 film and sapphire plate in the silicon-resin-SOS specimen. Nominal stress for delamination is about 2.23MPa. From a comparison of the strength of joint for rapid and slow cooling conditions, it is found that the residual stress reduces the strength of joint.

Commentary by Dr. Valentin Fuster
2013;():V001T07A005. doi:10.1115/IPACK2013-73137.

During service and/or storage, Sn-Ag-Cu (SAC) solder alloys are subjected to temperatures ranging from 0.4 to 0.8 Tm (where Tm is the melting temperature of SAC alloys), making them highly prone to significant microstructural coarsening. The microstructures of these low melting point alloys continuously evolve during service. This results in evolution of creep properties of the joint over time, thereby influencing the long-term reliability of microelectronic packages. Here, we study microstructure evolution and creep behavior of two Sn-Ag-Cu (SAC) alloys, namely Sn-3.0Ag-0.5Cu and Sn-1.0Cu-0.5Cu, isothermally aged at 150°C for various lengths of time. Creep behavior of the two SAC solders after different aging durations was systematically studied using impression creep technique. The key microstructural features that evolve during aging are Ag3Sn particle size and inter-particle spacing. Creep results indicate that the creep rate increases considerably with increasing inter-particle spacing although the creep stress exponent and creep activation energy are independent of the aging history.

Commentary by Dr. Valentin Fuster
2013;():V001T07A006. doi:10.1115/IPACK2013-73149.

Electroplated copper thin films have started to be applied to not only interconnections in printed wiring boards, but also thin film interconnections and TSV (Through Silicon Via) in semiconductor devices because of its low electric resistivity and high thermal conductivity. Thus, the electrical reliability of the electroplated copper interconnections was discussed experimentally.

The relationship between the electrical properties and crystallographic quality (crystallinity) of electroplated copper thin-film interconnections was investigated. The crystallinity of the grains and grain boundaries of the interconnections was evaluated on the basis of the image quality (IQ) value obtained by electron back-scatter diffraction (EBSD) analysis. The electrical properties of the interconnections vary significantly depending on their crystallinity. The crystallinity also changed drastically as functions of electroplating conditions and the annealing temperature after electroplating.

Although the electro migration (EM) resistance of the annealed interconnection is improved, the stress-induced migration (SM) is activated by a high residual tensile stress after annealing caused by the strong constraint of the shrinkage of the film during recrystallization. To improve its electrical reliability without heat treatment after the electroplating, the effects of the seed layer under the interconnections on the crystallinity of the electroplated film was investigated. As a result, the crystallinity was improved by changing the seed layer from Cu to Ru. In addition, the decrease in current density during electroplating also improves the crystallinity. Therefore, both introducing the Ru seed layer in addition to decreasing the current density during electroplating is effective for developing highly reliable copper interconnections.

Commentary by Dr. Valentin Fuster
2013;():V001T07A007. doi:10.1115/IPACK2013-73150.

Cold-spray (CS) technique is a new coating technology that is based on the high-velocity impinging of small solid particles on a substrate. The CS technique can make a thick deposit with less heat influence. Recently, this CS technique has been applied to the formation of an electrically conductive copper layer on dielectric materials such as polymers or ceramics. Previous researches show that the deposits made by the CS technique have high strength and residual stress comparing with bulk copper. However, since the deposits show brittle fracture and cracks propagate along the interfaces of the deposited particles, the deposits can not be applied to the products for which high reliability is indispensable. Therefore, it is very important to clarify the dominant factors which change the crystallinity of the deposits comparing with that of bulk copper in order to improve the quality of the deposits. One of the important factors should be the integrity of the interfaces between the deposited fine particles. This study is to evaluate the micro-texture and physical properties of the cold-sprayed copper deposit. Electron back-scatter diffraction method was applied to the evaluation of the crystallinity of the deposits. In addition, the relationship between the crystallinity with both mechanical and electrical properties of the deposits was clarified quantitatively.

Commentary by Dr. Valentin Fuster
2013;():V001T07A008. doi:10.1115/IPACK2013-73158.

A transparent conductive electrode comprised of alternating layers of graphene grown by chemical vapor deposition (CVD) and metallic single wall nanotubes (M-SWNTs) is presented. It was found that the addition of two single-layer graphene sheets enhances the conduction pathways in the M-SWNT film, yielding up to a 75% decrease in the sheet resistance with little sacrifice in the optical transmittance. Enhancements in the electrical properties of the films were made through a heat treatment process followed by nitric acid and thionyl chloride doping, yielding a sheet resistance of 70 Ω/sq with a transmittance of 78% at 550 nm. Composite films having undergone an annealing step were found to have stable electrical properties upon exposure to atmospheric conditions while doped films demonstrated limited stability.

Commentary by Dr. Valentin Fuster
2013;():V001T07A009. doi:10.1115/IPACK2013-73164.

SnAgCu (SAC) solders undergo continuous micro structural coarsening during both storage and service. In this study, we use cross-sectioning and image processing techniques to periodically quantify the effect of isothermal aging quantitatively on phase coarsening and evolution, in SAC305 (Sn3.0Ag0.5Cu) solder. SAC305 alloy is aged for (24–1000) hours at 100°C (∼ 0.7–0.8Tmelt). The characteristic parameters monitored during isothermal aging include size, volume fraction, and inter-particle spacing of both nanoscale Ag3Sn intermetallic compounds (IMCs) and micronscale Cu6Sn5 IMCs, as well as the volume fraction of pure tin dendrites in SAC305 solder.

Effects of above microstructural evolution on secondary creep constitutive response of SAC305 interconnects were modeled using a mechanistic multiscale creep model. The mechanistic phenomena modeled include: (1) dispersion strengthening by coarsened nanoscale Ag3Sn IMCs and reinforcement strengthening by micronscale Cu6Sn5 IMCs, respectively; and (2) load sharing between pure Sn dendrites and the surrounding eutectic Sn-Ag phase.

The coarse-grained polycrystalline Sn micro structure in SAC305 solder was not captured in the above model because isothermal aging did not appear to cause any significant change in the initial grain morphology of SAC305 solder joints. The above model is shown to predict the drop in creep resistance due to the influence of isothermal aging on SAC305 solder joints.

Commentary by Dr. Valentin Fuster
2013;():V001T07A010. doi:10.1115/IPACK2013-73170.

Erosion behavior of plasma nitrided stainless steel by molten Sn was examined. To investigate the erosion behavior, the interfacial reaction was investigated at the temperature ranging from 350 to 450°C using plasma nitrided SUS304 and SUS316 stainless steel which sandwich pure Sn foil. As the results, it was found that the surface area of the nitrided layer is peeled and subsequently FeSn2 phases form in the reaction interface. FeSn2 phases grow toward molten Sn and Sn diffuses into the nitrided layer. Moreover, Ni3Sn4 phases form and grow in molten Sn. Apparent activation energies of the Sn diffusion into the nitrided layer were estimated to be 153 kJ/mol and 133 kJ/mol for plasma nitrided SUS304 and SUS316, respectively.

Commentary by Dr. Valentin Fuster
2013;():V001T07A011. doi:10.1115/IPACK2013-73171.

The aim of this study is to investigate the joint properties of Sn-58mass%Bi and Sn-57mass%Bi-0.5mass%Sb low-melting lead-free solder balls on the electroless Ni/Au and Ni/Pd/Au plated Cu electrodes fabricated with a lead-free plating solution. Compared with the conventional Ni plating solution containing lead, the soldered joints with Ni/Au and Ni/Pd/Au electrodes fabricated with the lead-free plating solution showed comparable joint properties. In the joints with Ni/Pd/Au electrodes, ball shear force increased when the Pd layer is dissolved into solder by multi reflows. In both joints with Ni/Au and Ni/Pd/Au electrodes, a part of the Ni layer was dissolved into solder and thus the (Ni,Cu)3Sn4 intermetallic compound layer formed at the joint interface. Ball shear force decreased upon aging due to the growth of the (Ni,Cu)3Sn4 layer at the joint interface.

Commentary by Dr. Valentin Fuster
2013;():V001T07A012. doi:10.1115/IPACK2013-73172.

The effect of additives in electrolyte on mechanical properties of electrolytic copper foil was investigated. Bis-(3-sulfopropyl)-disulfide disodium salt (SPS), animal protein of low molecular (PBF) and hydroxyethyl cellulose (HEC) were added in electrolyte as additives. The additive amount of SPS was changed in this study. The addition of SPS is effective to improve tensile strength and hardness of electrolytic copper foil. With increasing the additive amount of SPS, the grain of electrolytic copper became finer and thus its hardness and elastic modulus increased. On the other hand, fatigue properties improved when the additive amount of SPS decreased and the grain size of electrolytic copper became relative large.

Commentary by Dr. Valentin Fuster
2013;():V001T07A013. doi:10.1115/IPACK2013-73192.

In this study, the relationship between microstructural change and fracture in the process of low-cycle fatigue of Sn-Ag-Cu solder joint was investigated using the solder ball of 630μm and 100μm in diameter by analysis of crystallographic orientation by means of EBSD. The 630μm specimen has subgrain boundaries formed by dynamic recovery in the stress concentration region, and the subgrain boundaries become high-angle random grain boundaries by additional cycles. The fatigue crack stably propagates along the random grain boundary in the stress concentration region. In contrast, the 100μm specimen has subgrain boundaries and high-angle random grain boundaries formed across the entire joint area. Since the occurrence of grain boundary fracture across the entire joint area by the connection of high energy grain boundaries, the crack propagation life of the 100μm specimen shortens without the stable crack growth compared to the 630μm specimen.

Commentary by Dr. Valentin Fuster
2013;():V001T07A014. doi:10.1115/IPACK2013-73193.

In this study, the effects of temperature and strain rate on low cycle fatigue life of Bi-Sn eutectic alloys have been studied. The fatigue life improves with the increasing of temperature and the decreasing of strain rate. This is a reverse phenomenon from characteristics found in general metals. As temperature increases and strain rate decreases, grin boundary sliding becomes the dominant deformation mechanism and the fatigue ductility coefficient increases, resulting in an improvement of fatigue life. To the extent of this study, dependence on temperature and strain rate can be expressed by Manson-Coffin’s law modified using Z-parameters.

Commentary by Dr. Valentin Fuster
2013;():V001T07A015. doi:10.1115/IPACK2013-73234.

The mechanical properties of a lead free solder are strongly influenced by its microstructure, which is controlled by its thermal history including solidification rate and thermal aging after solidification. Due to aging phenomena, the microstructure, mechanical response, and failure behavior of lead free solder joints in electronic assemblies are constantly evolving when exposed to isothermal and/or thermal cycling environments. Through uniaxial testing of miniature bulk solder tensile specimens, we have previously demonstrated that large changes occur in the stress-strain and creep behaviors of lead free solder alloys with aging. Complementary studies by other research groups have verified aging induced degradations of SAC mechanical properties. In those investigations, mechanical testing was performed on a variety of sample geometries including lap shear specimens, Iosipescu shear specimens, and custom solder ball array shear specimens. While there are clearly aging effects in SAC solder materials, there have been limited prior mechanical loading studies on aging effects in actual solder joints extracted from area array assemblies (e.g. PBGA or flip chip). This is due to the extremely small size of the individual joints, and the difficulty in gripping them and applying controlled loadings (tension, compression, or shear).

In the current work, we have explored aging phenomena in actual solder joints by nano-mechanical testing of single SAC305 lead free solder joints extracted from PBGA assemblies. Using nanoindentation techniques, the stress-strain and creep behavior of the SAC solder materials have been explored at the joint scale for various aging conditions. Mechanical properties characterized as a function of aging include the elastic modulus, hardness, and yield stress. Using a constant force at max indentation, the creep response of the aged and non-aged solder joint materials has also been measured as a function of the applied stress level. With these approaches, aging effects in solder joints were quantified and correlated to the magnitudes of those observed in testing of miniature bulk specimens. Our results show that the aging induced degradations of the mechanical properties (modulus, hardness) of single grain SAC305 joints were similar to those seen previously by testing of larger “bulk” solder specimens. However, due to the single grain nature of the joints considered in this study, the degradations of the creep responses were significantly less in the solder joints relative to those in larger uniaxial tensile specimens. The magnitude of aging effects in multi-grain lead free solder joints remains to be quantified.

Due to the variety of crystal orientations realized during solidification, it was important to identify the grain structure and crystal orientations in the tested joints. Polarized light microscopy and Electron Back Scattered Diffraction (EBSD) techniques have been utilized for this purpose. The test results show that the elastic, plastic, and creep properties of the solder joints and their sensitivities to aging are highly dependent on the crystal orientation. In addition, an approach has been developed to predict tensile creep strain rates for low stress levels using nanoindentation creep data measured at very high compressive stress levels.

Commentary by Dr. Valentin Fuster
2013;():V001T07A016. doi:10.1115/IPACK2013-73241.

The microstructure, mechanical response, and failure behavior of lead free solder joints in electronic assemblies are constantly evolving when exposed to isothermal aging and/or thermal cycling environments. In our prior work on aging effects, we have demonstrated that large degradations occur in the material properties (stiffness and strength) and creep behavior of Sn-Ag-Cu (SAC) lead free solders during aging. These effects are universally detrimental to reliability and are exacerbated as the aging temperature and aging time increases. Conversely, changes due to aging are relatively small in conventional Sn-Pb solders.

In our current work, we are exploring several doped SAC+X alloys in an attempt to reduce the aging induced degradation of the material behavior of SAC solders. The doped materials are lead free SAC solders that have been modified by the addition of small percentages of one or more additional elements (X). Using dopants (e.g. Bi, In, Ni, La, Mg, Mn, Ce, Co, Ti, Zn, etc.) has become widespread to enhance shock/drop reliability, wetting, and other properties; and we have extended this approach to examine the ability of dopants to reduce the effects of aging and extend thermal cycling reliability. In this paper, we concentrate on presenting the results for SAC+X (X = Zn, Co, Ni). The enhancement of aging resistance for the doped lead free solders was explored. Comparisons were made to the responses of non-doped SAC lead free solder alloys.

The effects of aging on mechanical behavior have been examined by performing stress-strain and creep tests on solder samples that were aged for various durations (0–6 months) at elevated temperature (100 °C). Variations of the mechanical and creep properties (elastic modulus, yield stress, ultimate strength, creep compliance, etc.) were observed and modeled as a function of aging time and aging temperature. Our findings show that the doped SAC+X alloys illustrate reduced degradations with aging for all of the aging temperatures considered. Also, the stress-strain and creep mechanical properties of doped solders are better than those of reference solders after short durations of aging. After long term aging, doped solder alloys were found to have more stable behaviors than those of the standard SAC alloys. A parallel microstructure study has shown that less degradation and coarsening of the phases occurs in doped solder materials relative to non-doped solders after severe aging.

Commentary by Dr. Valentin Fuster
2013;():V001T07A017. doi:10.1115/IPACK2013-73242.

Polymer encapsulants exhibit evolving properties that change significantly with environmental exposures such as moisture uptake, isothermal aging and thermal cycling. In this study, the effects of moisture adsorption on the stress-strain behavior of a polymer encapsulant were evaluated experimentally. The uniaxial test specimens were exposed in an adjustable thermal and humidity chamber to combined hygrothermal exposures at 85 °C/85% RH for various durations. After moisture preconditioning, a microscale tension-torsion testing machine was used to evaluate the complete stress-strain behavior of the material at several temperatures. It was found that moisture exposure caused plasticization and strongly reduced the mechanical properties of the encapsulant including the initial elastic modulus and ultimate tensile stress. Reversibility tests were also conducted to evaluate whether the degradations in the mechanical properties were recoverable. Upon fully redrying, the polymer was found to recover most but not all of its original mechanical properties. As revealed by FTIR, some of the adsorbed water had been hydrolyzed in the organic structure of the epoxy-based adhesive, causing permanent changes to the mechanical behavior.

Commentary by Dr. Valentin Fuster
2013;():V001T07A018. doi:10.1115/IPACK2013-73278.

Electroless Nickel/Electroless Palladium/Immersion Gold (ENEPIG), which has been used in component packaging, has been gaining attention as a surface finish for printed wiring boards. The primary role of a printed wiring board surface finish is to provide a solderable surface for assembly, creating a reliable solder interconnect. With regards to reliability, the increased use of mobile electronics has resulted in the need to consider the ability of interconnects to withstand repeated mechanical shocks. This paper examines the drop reliability of both SnPb and SAC305 interconnects formed on ENEPIG finished printed wiring boards. For comparison, the drop reliability test results for similar boards with Immersion Silver (ImAg) board finish are included. Test boards include BGA and resistor packages. The boards are dropped 500 times to achieve failure across the components. Failure analysis revealed that the dominant failure mode for BGA packages on the ENEPIG finish was cracking in the solder balls at the component interface, while for the ImAg finish the dominant failure mode was cratering in the board laminate below the solder pad. For the resistor packages, cracking through the solder joint at the component interface was the dominant failure mode for both the ENEPIG and ImAg finishes. The drop results indicate that both finishes are suitable for systems that could experience mechanical shock due to drop, with components soldered onto ENEPIG with a SAC 305 solder having the highest survivability. The combination of SnPb and ImAg was found to be superior to SAC 305 and ImAg.

Commentary by Dr. Valentin Fuster
2013;():V001T07A019. doi:10.1115/IPACK2013-73287.

Wire bonding is predominant mode of interconnect in electronics packaging. Traditionally material used for wire bonding is gold. But industry is slowly replacing gold wire bond by copper-aluminum wire bond because of the lower cost and better mechanical properties than gold, such as high strength, high thermal conductivity etc. Numerous studies have been done to analyze failure mechanism of Cu-Al wire bonds. Cu-Al interface is a predominant location for failure of the wirebond interconnects. In this paper, the use of intermetallic thickness as leading indicator-of-failure for prognostication of remaining useful life for Cu-Al wire bond interconnects has been studied. For analysis, 32 pin chip scale packages were used. Packages were aged isothermally at 200°C and 250°C for 10 days. Packages were withdrawn periodically after 24 hours and its IMC thickness was measured using SEM. The parts have been prognosticated for accrued damage and remaining useful life in current or anticipated future deployment environment. The presented methodology uses evolution of the IMC thickness in conjunction with the Levenberg-Marquardt Algorithm to identify accrued damage in wire bond subjected to thermal aging. The proposed method can be used for equivalency of damage accrued in Cu-Al parts subjected to multiple thermal aging environments.

Topics: Failure
Commentary by Dr. Valentin Fuster
2013;():V001T07A020. doi:10.1115/IPACK2013-73315.

Solder joints in electronic packages and devices serve as mechanical and electrical connections as well as thermal paths for heat dissipation. Due to the miniaturization of electronic packaging, nowadays solder joints contain large volume fraction of IMCs. It has been observed that solder joint strength is controlled largely by intermetallic strength at higher strain rate. Macroscopic properties such as tensile and shear strength, creep, ductility depend on Intermetallic layer’s properties of solder joints. This study is carried out to determine elastic-plastic properties of Cu6Sn5 intermetallic in Sn-3.5Ag/Cu system with reflow soldering by nanoindentation. Elastic properties such as elastic modulus and hardness were determined from the load-depth curve. A widely used reverse analysis model described by Dao et al. [1] was considered to extract plastic properties such as yield strength and strain hardening exponent using nanoindentation results. Anisotropy of Cu6Sn5 was taken into consideration to see if that has any effect on the mechanical properties. Our study considered crystallographic grain orientation along normal to the growth axis of Cu6Sn5 IMC which was extracted using Electron backscatter diffraction (EBSD) mapping. Statistically indistinguishable properties were observed for Cu6Sn5 IMC. Average elastic-plastic properties of Cu6Sn5 were than compared with already published results in literatures.

Commentary by Dr. Valentin Fuster

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