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RF Microwave

2003;():1-5. doi:10.1115/IPACK2003-35010.

Antennas play a paramount role today’s communication centered market place. Recently the demands for miniaturization of electronic devices have increased rapidly in which a miniaturization of integrated antennas has confronted the same development. However, antennas and especially the performance parameters of antennas obey physical laws in which the electrical dimensions of an antenna have a major effect on these parameters such as voltage standing wave ratio (SWR) and radiation efficiency. Recently, a new, multidisciplinary field of study called “Electromagnetic BandGap” (EBG) structures have been developed. An EBG structure forms a lattice whose period determines its resonant frequency i.e. the range of frequencies where the stop band exists for transmission of microwave signals. Antennas physical dimensions can be made noticeably smaller applying EBG materials. These advantages of EBG structures allow us to design smaller antennas with high radiation efficiency on high-dielectric substrates such as ceramics. This paper presents how conventional microstrip antennas can be miniaturized using EBG materials with improved performance parameters. In addition, a novel flexible antenna is presented which can be rolled up during e.g. transportation.

Commentary by Dr. Valentin Fuster
2003;():7-12. doi:10.1115/IPACK2003-35155.

Coupling between interconnects in high density structures limits the broadband performance, leading to degradation in insertion loss and cross talk characteristics. This paper describes the solution space analysis of LTCC interconnects with meshed planes. The impact of metal coverage, interconnect structures and mesh geometry was evaluated through detailed 3-D FEM based simulations.

Commentary by Dr. Valentin Fuster
2003;():13-18. doi:10.1115/IPACK2003-35247.

A novel RF MEMS integration technology was developed to achieve the three-dimensional integration of microwave and millimeter-wave components and sub-circuits with improved performance using multilayer vertical interconnects. This technology, which allows planar circuits to be monolithically stacked vertically in three dimensions (3D), provides one of the major initial steps in the realization of a “system in a package.” To process high-aspect-ratio via interconnects in 3D MMIC multilayer circuitry, combination of unique microelectronic and traditional MEMS microfabrication technologies were used. Based on these techniques, a set of test structures were successfully fabricated to facilitate the vertical interconnect characterization. Experimental results revealed that at microwave frequencies, e.g. X band (8–12 GHz), the vertical interconnect discontinuities contributed significantly to the insertion loss and the phase change. With the available advanced conductor loss models, lumped-element equivalent circuit models were derived from the via module measurements. Using quarter wavelength T-junction resonator structures, polyimide was also characterized for its microwave properties over a wide frequency range. Multilayer vertically interconnected transmission line circuits were monolithically processed and used to verify the derived electrical models.

Commentary by Dr. Valentin Fuster
2003;():19-24. doi:10.1115/IPACK2003-35360.

This paper presents the development of RF System-on-Package (SOP) architectures for compact and low cost wireless radio front-end systems. A novel 3D integration approach for SOP-based solutions for wireless communication applications is proposed and utilized for the implementation of a C band Wireless LAN (WLAN) RF front-end module by means of stacking LTCC substrates using μBGA technology. LTCC designs of high-performance multilayer embedded bandpass filters and novel stacked cavity-backed patch antennas are also reported. In addition, the fabrication of very high Q-factor inductors and embedded filter in organic substrates demonstrate the satisfactory performance of multilayer organic packages. The well known full-wave numerical techniques of FDTD and MRTD are used for the modeling of adjacent lines crosstalk, of the Q-factor of embedded passives and for the accurate simulation of MEMS structures.

Commentary by Dr. Valentin Fuster

Telecommunications

2003;():25-28. doi:10.1115/IPACK2003-35043.

The heart of next generation networks is currently centered on building blocks for performing transport, switching, routing, amplification, attenuation, storage and conversion functions. One of the key elements of the network is a switch, which might perform as an optical switch (optical-electrical-optical, or OEO) or a “purely” photonic switch (optical-optical-optical or OOO). The merits and benefits of both in actual network applications are analyzed and outlined. Although both switches have their own advantages as a network element, the full judgement of their role in next generation networks requires an “overall network view”. Network functionalities such as grooming capabilities, scalability, traffic management, protection, line equalization or performance monitoring are those taken in competitive analyses in terms to understand some impacts of switch choice in the network. It is expected that both optical and photonic switches will play complementary roles in next generation networks. Combined with new communication technology advances in routing, transport, amplification and wavelength conversion, both switches will be the cornerstones of next generation solutions, each one with its specific role.

Commentary by Dr. Valentin Fuster
2003;():29-33. doi:10.1115/IPACK2003-35127.

A new package for thermally compensating a fiber Bragg grating, which requires less accuracy in positioning the fiber onto the device, is discussed. Experiments show that it can reduce the shift in reflected wavelength from 1575 pm to 78 pm for a temperature change of 120 K. The deformation of the package showed no hysteresis, and the effective thermal compensation is repeatable over many cycles. Furthermore the package also has the potential to give non-linear thermal compensation for fiber Bragg gratings.

Commentary by Dr. Valentin Fuster
2003;():35-39. doi:10.1115/IPACK2003-35338.

The cooling of boards and components in telecommunication chassis is becoming progressively more challenging as the power dissipation of the components increases. The internet market is demanding higher speeds and the internet gear makers try to accommodate the increasing demand of the consumer. Hence there are situations where the power requirement for one rack unit of the chassis is reaching 500–600 W currently and expected to reach about 800–1000 W in 1–2 years. The power dissipations on components are currently in the vicinity of approximately 60–80 W and expected to reach roughly 100–120 W in the near future. This paper presents a design effort wherein a chassis has been analyzed and designed for a cooling capacity on the order of 600 W for the board to the extent that one is able to cool about 80 W for the ASICs and other components on the board.

Commentary by Dr. Valentin Fuster

Thermal Management

2003;():41-46. doi:10.1115/IPACK2003-35002.

Graphite foams consist of a network of interconnected graphite ligaments and are beginning to be applied to thermal management of electronics. The thermal conductivity of the bulk graphite foam is similar to aluminum, but graphite foam has one-fifth the density of aluminum. This combination of high thermal conductivity and low density results in a specific thermal conductivity about five times higher than that of aluminum, allowing heat to rapidly propagate into the foam. This heat is spread out over the very large surface area within the foam, enabling large amounts of energy to be transferred with relatively low temperature difference. For the purpose of graphite foam thermosyphon design in electronics cooling, various effects such as graphite foam geometry, sub-cooling, working fluid effect, and liquid level were investigated in this study. The best thermal performance was achieved with the large graphite foam, working fluid with the lowest boiling point, a liquid level with the exact height of the graphite foam, and at the lowest sub-cooling temperature.

Commentary by Dr. Valentin Fuster
2003;():47-55. doi:10.1115/IPACK2003-35004.

At low to moderate Reynolds numbers, cast pin fin coldwalls provide the best performance and lowest unit cost for air-cooled electronics systems. Until recently, insufficient data existed to design coldwalls with moderate length pin fins for electronics systems. Empirical correlations for the Fanning friction factor, f = f(S/d, T/d, L/d, Red ), and the Colburn j-factor, j = j(S/d, T/d, L/d, Red ), were previously developed for two flow regimes with a transition Reynolds number, Retrn , separating the two regimes. Using these correlations, the effect of configuration on the design is discussed and a design procedure is proposed. Example problems are presented for (1) a system cooled by an environmental control system, and (2) a system cooled by ambient air using a fan.

Topics: Design , Electronics
Commentary by Dr. Valentin Fuster
2003;():57-61. doi:10.1115/IPACK2003-35008.

A near CSP plastic encapsulated package with a quad flat non-leaded (QFN) structure has been drawn much attention due to it small size and lightweight applications. Thermal efficiency is the major concern for adopting such type of package in place of TSSOP package. The thermal dissipation for electronics with the higher power consumption is current developing to it uppermost limitation as a wire bonded, lead-frame substrate type of QFN with various pine counts and body sizes. It is therefore an object of the present study to investigate thermal performance of QFN package optimum design attached on different layers and thickness of laminated printed circuit board (PCB), which is further related to reliability issue of this type of IC package. Numerical simulation illustrates how the thermal efficiency of the QFN package can be reached with different PCB designs and airflow conditions.

Commentary by Dr. Valentin Fuster
2003;():63-71. doi:10.1115/IPACK2003-35018.

An effective thermal analyzer for exploring the thermal performance of 3-D heat spreader having discrete heat sources integrated with heat sink has been successfully developed in the study. The thermal performances such as local temperature distributions and isotherms on heat spreader surfaces; and overall resistance of heat spreader/sink assembly are investigated. Besides, a series of parametric studies have been performed. The parameters and conditions explored include the size and heat dissipation rate of heat sources, size and material of heat spreaders and heat sinks, type of convection in heat sink, and contact conditions between heat spreader and heat sink. The superiority of the developed thermal analyzer through two sample cases having multi-discrete heat sources has finally been demonstrated.

Commentary by Dr. Valentin Fuster
2003;():73-80. doi:10.1115/IPACK2003-35020.

A series of experimental investigations with a new modified transient liquid crystal method on the studies related to the fluid flow and heat transfer characteristics in a channel installed with a heat sink have been successfully performed. The parametric studies on the local and average effective heat transfer characteristics for confined heat sinks have been explored. The influencing parameters and conditions include air preheating temperature at channel inlet, flow velocity and heat sink types. Besides, a concept of the amount of enhanced heat transfer (AEHT) is introduced and defined as the ratio of j/f. The j/f ratio is almost independent of Reynolds number for a specific confined heat sink. The j/f ratios are 0.0603 and 0.0124 for fully-confined and unconfined heat sinks, respectively.

Commentary by Dr. Valentin Fuster
2003;():81-88. doi:10.1115/IPACK2003-35021.

In the present study, the forced air convection heat transfer for unconfined and confined heat sinks by considering flow bypass effect is studied on a semi-empirical basis. The flow bypass effect for unconfined heat sinks is firstly investigated. For unconfined heat sinks with specified fin spacing and fin height, the results reveal that the value of Ui /(ε·Us ), which represents the flow bypass capability, increases from a very small Reynolds number up to a certain Reynolds number, say Rei = 60–200; and then gradually decrease with further increasing Reynolds number. At a specified Reynolds number, the Ui /(ε·Us ) will generally increase when the fin spacing decreases or the fin height increases. For heat sinks partially confined in a channel, a novel concept to estimate an imaginative flow domain, in which the flow is influenced due to the existence of heat sink in the channel, is postulated in the study. Accordingly, an effective method for predicting the flow velocity between fins, flow rate through the heat sink and the fin heat transfer coefficient in both unconfined flow and confined flow is presented. Finally, in order to explore the optimal number of fins, a performance parameter defined as the ratio of thermal conductance to the required pumping power is introduced; an optimal procedure to determine the maximum performance parameter for a heat sink partially confined in a channel is postulated. The results manifest that the optimal number of fins increases with increasing inlet flow velocity.

Topics: Heat sinks
Commentary by Dr. Valentin Fuster
2003;():89-96. doi:10.1115/IPACK2003-35029.

A parametric evaluation of elliptical pin fin heat sinks was performed using a commercially available CFD software package. The investigation involved variation of fin length, fin height, fin gap width, and air velocity while holding the heat flux and fin geometry as constants. The effect of these variables on the thermal performance and airflow impedance characteristics of the heat sink was studied and an optimum heat sink design was selected for a given set of conditions. Additionally, an often-encountered user requirement of multiple heat sinks in a row was also studied with these variables. In line and staggered elliptical fins as well as plate or extruded fins were analyzed although the main focus of the evaluation was based upon in line elliptical fins.

Commentary by Dr. Valentin Fuster
2003;():97-102. doi:10.1115/IPACK2003-35041.

Feasibility study on alternative cooling methods to air-cooling with heat sinks is provided in this paper. The study focuses on cooling of 64-bit microprocessor at 80nm technology node with projected heat dissipation of 200W. An example was presented to illustrate limitation of air-cooling for the 200W microprocessor using an all-Cu heat sink with tall fins. Three alternatives to air-cooling were studied in this work: liquid cooling, two-phase convective flow cooling and refrigeration cooling. Thermodynamic analysis was used to estimate operating conditions and fluid flow rates for each alternative. The information provides a preliminary basis for assessing capabilities and weaknesses among alternatives. Liquid and two-phase cooling simply transfer heat from high to low temperature. In contrast, refrigeration cooling operates as a heat pump, moving heat from low to high temperature. Refrigeration cooling offers capability to cool microprocessor (LSI) chip to temperatures below ambient or freezing. The drawback is more heat must be removed from the system. Liquid cooling operates at close to ambient pressure, while two-phase and refrigeration cooling operate at higher pressures. Challenges to implementation of all three alternatives include availability of low cost, miniature components (pumps or compressors, heat exchanger and condenser), designing for redundancy (or reliability) and ease of installation and field service. In terms of component availability and cost, liquid cooling is preferred choice, followed by two-phase and refrigeration cooling.

Topics: Cooling
Commentary by Dr. Valentin Fuster
2003;():103-109. doi:10.1115/IPACK2003-35048.

This paper describes an application example of thermal flow simulation to the design of a switch mode power supply (SMPS) that is natural convection air-cooled. In this analysis, the modeling of printed circuit board (PCB) and power semiconductor devices was examined using the design of experiments method. The PCB was treated as a simple plate, and average thermal conductivity was not considered. The power semiconductor devices were modeled as a simple hexahedral resistive network block. As the heat generation sources, a field effect transistor (FET) and a diode were considered in the simulation, and the calculation method of power loss is described. The difference between measured and calculated values for power semiconductor devices was found to be within approximately 10 K.

Commentary by Dr. Valentin Fuster
2003;():111-117. doi:10.1115/IPACK2003-35055.

Light Emitting Diodes (LEDs) have progressed in recent years from emitting indicator level lighting to emitting enough light for illumination applications. This has opened a new field for LED applications, resulting in significant advantages over conventional light sources and creating some application challenges unique to LEDs. Conventional lighting methods provide little guidance for LED thermal problems since these usually involve a very high temperature source, such as a filament or an arc, and radiant heat transfer dissipates the thermal energy. LED junction temperatures are limited to much lower values and hence the heat transfer system cannot depend upon radiant energy transfer. This means the cooling methods for lighting now shift from primarily radiation to conduction and natural convection, and this paradigm shift lighting designers must recognize when moving to LEDs. In this paper, the development of a LED-based spot module heat sink in a free convective cooling system is discussed. The rationale for choosing a cylindrical tube, longitudinal fin (CTLF) heat sink is shown, as is the performance of five different configurations of the heat sink in various orientations. The requirement for using heat sinks in various orientations comes from lighting applications, where the light may be installed in various directions, such as vertical up, vertical down, horizontal, or at almost any other angle. Heat sink test results are plotted for Nussult number versus standard and modified channel Rayleigh number, showing a similar correlation to the parallel plate heat sinks investigated first by Elenbaas. A different correlation for the isolated-plate limit section is proposed for CTLF heat sinks, as well as a proposed area of operation on these Nu-Ra curves for orientation-insensitive heat sinks. Finally, explanations for the different levels of sensitivities observed in different areas of the Nu-Ra curves are offered.

Commentary by Dr. Valentin Fuster
2003;():119-127. doi:10.1115/IPACK2003-35058.

Increases in microprocessor power dissipation and the resulting effect on the cost and complexity of thermal management solutions has been well documented in recent years. Accompanying this increase in overall power dissipation has been a reduction in feature size due to process improvements resulting in a steady decrease in the size of the processing core where most of the power on a die is generated. This trend is expected to continue into the near future and will likely lead to a power dense core covering a fraction of the total die surface area surrounded by areas of reduced power density cache. Evaporative spray cooling has been long identified as a technology that can be used to manage very high power densities (> 100 W/cm2 ). Limitations in the controllability of individual spray droplets, however, have generally prevented its use in applications that contain marked variation in spatial power density. Since only a relatively uniform spray pattern is possible with existing spray delivery technologies, sections of lower power density become susceptible to pool boiling and thereby place limitations on bulk flow rates, which accordingly limit thermal performance. Conversely, variations in heat transfer coefficients caused by uncontrolled pool boiling across devices can create thermal stresses. In this paper we demonstrate how thermal inkjet technology can be effectively utilized to spray cool a heat source with non-uniform power density. Experimental data is presented for a water-cooled heat source and critical heat fluxes of up to 270 W/cm2 are reported. Additionally, correlations are developed for the unique spray pattern afforded by the technology.

Topics: Cooling , Sprays , Electronics
Commentary by Dr. Valentin Fuster
2003;():129-137. doi:10.1115/IPACK2003-35059.

The data center of tomorrow is characterized as one containing a dense aggregation of commodity computing, networking and storage hardware mounted in industry standard racks. In fact, the data center is a computer. The walls of the data center are akin to the walls of the chassis in today’s computer system. The new slim rack mounted systems and blade servers enable reduction in the footprint of today’s data center by 66%. While maximizing computing per unit area, this compaction leads to extremely high power density and high cost associated with removal of the dissipated heat. Today’s approach of cooling the entire data center to a constant temperature sampled at a single location, irrespective of the distributed utilization, is too energy inefficient. We propose a smart cooling system that provides localized cooling when and where needed and works in conjunction with a compute workload allocator to distribute compute workloads in the most energy efficient state. This paper shows a vision and construction of this intelligent data center that uses a combination of modeling, metrology and control to provision the air conditioning resources and workload distribution. A variable cooling system comprising variable capacity computer room air conditioning units, variable air moving devices, adjustable vents, etc. are used to dynamically allocate air conditioning resources where and when needed. A distributed metrology layer is used to sense environment variables like temperature and pressure, and power. The data center energy manager redistributes the compute workloads based on the most energy efficient availability of cooling resources and vice versa. The distributed control layer is no longer associated with any single localized temperature measurement but based on parameters calculated from an aggregation of sensors. The compute resources not in use are put on “standby” thereby providing added savings.

Topics: Cooling , Data centers
Commentary by Dr. Valentin Fuster
2003;():139-146. doi:10.1115/IPACK2003-35060.

IBM’s has recently introduced a high performance server that utilizes multichip modules that dissipate very high heat loads. Each multichip module consists of four microprocessor chips encased by a copper cap that serves to spread the heat load over an area of roughly 113 mm × 113 mm. The module is air cooled by a single aluminum alloy bonded-fin fan sink. For applications requiring the microprocessors to operate at higher frequencies, the aluminum heat sink, with its lower thermal conductivity, cannot provide sufficient cooling; therefore, a copper heat sink must be employed. However, copper alloys have the disadvantage of a significant weight penalty (density ∼ 8.9 g/cm3 ), being 3.3 times heavier than aluminum (density ∼ 2.7 g/cm3 ), and is significantly more costly to manufacture. A novel approach for an improved heat sink has been developed using a new natural graphite-based/epoxy composite material. This material has low density (∼1.9 g/cm3 ) and anisotropic thermal conductivity (∼370 W/m-K in two directions, ∼ 7 W/m-K in the third direction). Bonded fin manufacturing methods have been developed to produce a heat sink that exploits the material’s high thermal conductivity when used in combination with a copper spreader module, such as used in the IBM server. Convective heat sink thermal performance approaching that of copper (e.g. 0.030 °C/W) has been achieved at a fraction of copper’s weight. Therefore, additional hardware required to allow the copper heat sinks to withstand shock and vibration standards, was not necessary with the lightweight graphite solution. Mechanical issues involved with using the lower strength graphite materials in a metal retrofit situation had to be resolved. Solutions included the use of aluminum end plates to provide edge protection to the heat sink with metal stiffeners inserted into the base for extra structural integrity. A variety of mechanical attachment methods was evaluated to join the graphite to the copper heat spreader. Lapping procedures were developed for the graphite heat sink to provide the required flatness necessary to minimize the temperature drop across the interface.

Commentary by Dr. Valentin Fuster
2003;():147-151. doi:10.1115/IPACK2003-35069.

This paper explores the novel technique of forced synthetic jet cooling within high-aspect ratio ducts that can be accommodated within low-profile electronic systems. A synthetic jet is an intense, small-scale turbulent jet that is synthesized directly from the fluid in the system in which it is embedded and is formed when fluid is alternately sucked and ejected from the cavity by the motion of a diaphragm bounding the cavity, so that there is no net mass addition to the system. This feature obviates the need for input piping or complex fluidic packaging and makes synthetic jets ideally suited for the low-profile geometries of portables. In the current work, a simple configuration of a 2-D synthetic jet ejector in a rectangular channel is used to ascertain the flow and thermal performance curves, overall thermal resistance and effectiveness for the synthetic jet ejector channel flow.

Topics: Cooling , Computers
Commentary by Dr. Valentin Fuster
2003;():153-157. doi:10.1115/IPACK2003-35070.

Powerful refrigeration methods are being deployed to cool electronic devices in test and in end-use application. Cooling capacity control is required to prevent over- or under-cooling. Various levels of control precision are also required. Test applications demand precise temperature control while many end-use applications will accommodate a less sophisticated approach. Important determinants of the method employed to control refrigeration capacity include target operating temperature, absolute and dynamic power dissipation of the device being cooled, control precision required, refrigeration system design and construction, as well as application-related details of the electronics assembly. A variety of capacity control methods are needed to cover the breadth of electronics cooling applications. Control free, or open loop systems meet the needs of some applications. Other systems employ thermal expansion (TX) and hot-gas by-pass valves to provide controlled cooling of very high power electronics cooling vapor compression systems. Modulation of condenser efficiency by varying fan speed provides a very simple but limited range of temperature control. A broad range of precise temperature control requires a combination of approaches to precisely meter refrigerant flow to the cold plate and, if needed, to apply parasitic heat. This paper overviews various vapor compression refrigeration control architectures as they apply to electronics cooling. Comparative cost and performance data are presented.

Commentary by Dr. Valentin Fuster
2003;():159-166. doi:10.1115/IPACK2003-35073.

The principle of measuring thermal resistance of thermal interface material (TIM) by sandwiching the material between a hot block and cold block is well known in the industry. TIM manufacturers usually use a variation of the industrial standard ASTM D5470 test method, and subsequently provide data that is difficult for the end user to effectively utilize for product development. This paper will discuss the design and construction of an automated TIM test system based on the ASTM D5470 standard. This automated test vehicle provides an independent study of various TIMs. The instrument enables standardized testing and performance documentation of interface materials from a wide array of manufacturers making it easier for end-users to compare and select the appropriate material for various applications. The automated test method is faster and easier to use than previous methods. It requires minimal operator intervention during the test and can perform preconditioning, and non-uniform heating if required. Experimental results obtained from the instrument will be discussed.

Commentary by Dr. Valentin Fuster
2003;():167-170. doi:10.1115/IPACK2003-35075.

Thermal interface materials (TIM) play a very important role in effectively dissipating unwanted heat generated in electronic devices. This requires that the TIM should have a high bulk thermal conductivity, intimate contact with the substrate surfaces, and the capability to form a thin bond line. In designing new TIMs to meet these industry needs, alkyl methyl siloxane (AMS) waxes have been studied as phase change matrices. AMS waxes are synthesized by grafting long chain alpha-olefins on siloxane polymers. The melting point range of the silicone wax is determined by the hydrocarbon chain length and the siloxane structure. When the AMS wax is mixed with thermally conductive fillers such as alumina, a phase change compound is created. The bulk thermal conductivities of the phase change material (PCM) are reduced as they go through the phase change transition from solid to liquid. By coating the PCM onto an aluminum mesh, both the mechanical strength and the thermal conductivity are drastically improved. The thermal conductivity increases from 4.5 W/mK for the PCM without aluminum support to 7.5 W/mK with the supporting mesh. The thermal resistance of the aluminum-supported sheet at a bond line thickness of 115 microns has been found to be ∼0.24 cm2 -C/W. Applying pressure at the time of application has a positive effect on the thermal performance of the PCM. Between contact pressures of 5–80 psi, the thermal resistance decreases as the pressure increases. The weak mechanical strength of the phase change material turns out to be a benefit when ease of rework and the effects of shock and vibration during shipping and handling are considered. A stud pull test of the aluminum mesh-supported PCM shows an average of 13 psi stress at the peak of the break.

Commentary by Dr. Valentin Fuster
2003;():171-181. doi:10.1115/IPACK2003-35077.

Numerical techniques have been used to evaluate various modifications to the design of a cooling system currently used for high power RF signal amplifiers. The system utilises a 300mm long × 220mm wide × 70mm high heat sink in forced turbulent air flows up to 120 litres per second. Using Computational Fluid Dynamics (CFD) software a detailed model of the heat sink, primary transistors and air flow was created. Experimental data obtained from the working system was used to validate the simulation results. The model was then modified to test the effects of various changes to the cooling system including incorporation of heat spreading techniques, elimination of bypass flow and changes to fin geometry. Reductions in transistor junction temperature of between 9°C and 12°C were predicted through the use of a copper heat spreader or full copper heat sink while the elimination of bypass flow reduced junction temperatures by up to 6°C. Strip fin and staggered fin arrangements provided little improvement, however by halving fin pitch and fin thickness (i.e doubling heat transfer area) device temperature reductions of 4°C were possible.

Topics: Design , Heat sinks
Commentary by Dr. Valentin Fuster
2003;():183-188. doi:10.1115/IPACK2003-35079.

Numerical calculation of silicon MOSFET is performed. Conjugate nature of the thermal and electrical behavior in the device is considered, and the lattice temperatures is solved as well as the electron concentration and the electron temperature. The calculated results shows the importance of considering both the electron and lattice temperatures for device modeling; the electron temperature has a significant impact on the calculated electron concentration and the lattice temperature. Submicron local hot spot is observed in the device, and its characteristics are discussed.

Commentary by Dr. Valentin Fuster
2003;():189-200. doi:10.1115/IPACK2003-35088.

The conductivity of thermal interface materials are typically determined using procedures detailed in ASTM D 5470. The disadvantages of using these existing procedures for compliant materials are discussed along with a proposed new procedure for determining thermal conductivity and Young’s modulus. The new procedure, denoted as the Bulk Resistance Method, is based on experimentally determined thermal resistance data and an analytical model for thermal resistance in joints incorporating thermal interface materials. Two versions of the model are presented, the Simple Bulk Resistance Model, based on the interface material thickness prior to loading and a more precise version denoted as the General Bulk Resistance Model, that includes additional parameters such as surface characteristics and thermophysical properties of the contacting solids. Both methods can be used to predict material in situ thickness as a function of load.

Commentary by Dr. Valentin Fuster
2003;():201-206. doi:10.1115/IPACK2003-35092.

The objective of this study is to compare different geometric models to represent thermal vias (plated though holes - PTH) in the substrate of a 196-ball FBGA package. The baseline model, which models each via individually as PTHs, was compared with models that model each via individually by solid cylinders and square cross-section prismatic blocks, and a compact model that models all vias by one prismatic block. The computational fluid dynamics (CFD) simulations were carried out using Icepak®. It was found that all simplifications led to some degree of under-prediction of the junction temperature. The results showed that the detailed models with the cylindrical cross-section and the square cross-section under-predicted the junction temperature by about 3–4% compared to the baseline model. The compact model, however, under-predicted the junction temperature by about 10% compared to the baseline model. The explanation for this error produced by the compact model is that it cannot model the constriction effect of the small individual thermal vias. The conclusion of this study is that all simplifications led to some degree of under-prediction of the junction temperature, and the popular technique to model the thermal vias by a block can lead to appreciable errors in predicting the die temperature.

Commentary by Dr. Valentin Fuster
2003;():207-210. doi:10.1115/IPACK2003-35097.

A dynamic inverse method for measuring the thermal resistance of cooling device is described. The cooling device is held on a heat capacity block and heating the block higher than environment 50°C, then the thermal resistance of cooling device is deduced from the exponential decay in the temperature difference between the heat capacity block and the environment. This technique is different from conventional measurement in two ways. First, the thermal resistance is usually measured under steady state and always required much time, thus the dynamic measuring technique is needed. Second, the power of heater is always needed to control at a certain value exactly but it isn’t in inverse method. The result reveal that the test time is reduced from several tens minutes to few minutes and made to an accuracy of about ±2%. This rapid and reliable measurement technique is possible used in-line testing of cooling devices for industrial application.

Commentary by Dr. Valentin Fuster
2003;():211-220. doi:10.1115/IPACK2003-35098.

A novel electronics cooling system that uses water heat pipes under an ambient temperature range from −30°C to 40°C has been developed. The system consists of several water heat pipes, air-cooled fins, and a metal block. The heat pipes are separated into two groups according to the thermal resistance of their fins. One set of heat pipes, which have fins with higher thermal resistance, operates under an ambient temperature range from −30°C to 40°C. The other set, which have lower resistance, operates from 0°C to 40°C. A prediction model based on the frozen-startup limitation of a single heat pipe was first devised and experimentally verified. Then, a prediction model for the whole-system was formulated according to the former model. The whole-system model was used to design a prototype cooling system, and it was confirmed that the prototype has a suitable cooling performance for an environmentally friendly electronics cooling system.

Commentary by Dr. Valentin Fuster
2003;():221-227. doi:10.1115/IPACK2003-35102.

In this work, some simple air-cooled high-effectiveness heat sinks are proposed for the cooling of electronic devices such as microprocessors for personal computers. The performance of the heat sinks are experimentally investigated. In particular the temperature of the heat sink surface in contact with the devices to be cooled is measured together with the air temperature and flow, by varying the air flow rate. The pressure drop in the air through the heat sinks is also measured. The thermal resistance of the disspators is then calculated and compared to that of commercially available heat sinks.

Commentary by Dr. Valentin Fuster
2003;():229-236. doi:10.1115/IPACK2003-35103.

This paper develops an analytical model to predict the overall thermal resistance of a parallel plate heat sink associated with a non-uniform heat source. Using constrictive ratio and apparent interface ratio to interpret equivalent heat source area and maximal heat flux on source-to-sink contacting surface, the non-uniform heat source problem can be simplified as an equivalent uniform heat source problem. Then by using the existed correlations the present model can calculate the overall thermal resistance as a function of heat sink geometry, properties, interface conditions, and airflow velocity. An experimental investigation is performed to verify the theoretical model. Prediction results show good agreement with experimental measurements over a number of testing units. A case study of optimum is also proposed to demonstrate and understand the effects of variable constrictive ratio and apparent interface resistance.

Topics: Heat , Heat sinks
Commentary by Dr. Valentin Fuster
2003;():237-244. doi:10.1115/IPACK2003-35104.

This paper presents a physics based analytical model to predict the thermal behavior of pin fin heat sinks in transverse forced flow. The key feature of the model is the recognition that unlike plate fins, streamwise conduction does not occur in pin fin heat sinks. Thus, the heat transfer from each fin depends on its local air temperature or adiabatic temperature and the local adiabatic heat transfer coefficient. Both experimental data and simplified CFD simulations are used to develop the two building blocks of the model, the thermal wake function and the adiabatic heat transfer coefficient. These building blocks are then used to include the effect of the thermal wake from upstream fins on the adiabatic temperature of downstream fins in determining the fin-by-fin heat transfer within the pin fin array. This approach captures the essential physics of the flow and heat transport within the fin array and yields an accurate model for predicting the thermal resistance of pin fin heat sinks. Model predictions are compared with existing experimental data and CFD simulations. The model is expected to provide a sound basis for a consistent performance comparison with plate fin heat sinks.

Commentary by Dr. Valentin Fuster
2003;():245-251. doi:10.1115/IPACK2003-35109.

In context of a European Commission funded project, development of a standardized multifunctional stacked 3D package was envisioned for potential applications in aviation, space and telecommunication sectors. The standardization and modularity was aimed to integrate packages from different technologies and to allow mutual slice inter-changeability. Thermal management solutions to the proposed new stacked 3D package as per the project specifications (a total of three stacked substrate slices, each slice of size 55 × 55 × 1 mm3 and total package height not exceeding 10.5 mm) are reported here. Three potential options were studied i.e. (a) module liquid cooling, (b) integration of miniature copper-water cylindrical heat pipes (OD 3.0 mm) with the 1.0 mm substrate slice and (c) development of flat plate heat pipes of 0.9 mm thickness. For options (a) and (b), initial tests have been performed taking aluminum as a representative material for AlSiC metal matrix composites which were to be employed in the final design. Further, copper based flat plate micro-structure conventional heat pipes have been developed and performance tested. Thermal interactions have been investigated with thermocouples coupled with infrared thermography. For safe operation up to 30W heating power (10W/slice), while thermal diffusion through the bare metallic substrate is sufficient for heat transfer from chip to the substrate, micro heat pipes should be employed to cool the substrate and transfer heat from it to an external cold plate. Flat plate heat pipes are advantageous for higher power levels per slice. Interlayer thermal interactions also affect the response of stacked 3D packages.

Topics: Heat pipes
Commentary by Dr. Valentin Fuster
2003;():253-261. doi:10.1115/IPACK2003-35113.

Expanded flexible graphite sheet materials have become attractive as Thermal Interface Materials (TIM’s). Flexible graphite sheet materials were originally developed as gaskets for fluid sealing applications. Properties that make flexible graphite sheets of interest as TIM’s include their relatively high thermal conductivities and their ability to conform well to surfaces. Specific grades of flexible graphite have been developed for TIM applications. Because flexible graphite sheets are porous, with open interconnected pores, it is possible to impregnate these sheets with various materials to improve properties. In particular, various polymers, such as mineral oils, synthetic oils, etc can be added to flexible graphite to improve its performance in thermal interface applications. This paper will review the thermal properties of TIM’s made by adding two different polymeric materials to a grade of flexible graphite specifically developed as a thermal interface material.

Topics: Graphite
Commentary by Dr. Valentin Fuster
2003;():263-270. doi:10.1115/IPACK2003-35114.

In the present study fluid flow and heat transfer characteristics of a microchannel heat sink subject to an impinging jet are experimentally investigated. In order to evaluate the cooling performance of a microchannel heat sink subject to an impinging jet under the fixed pumping power condition, the pressure drop across a microchannel heat sink and temperature distributions at the base of it are measured. Especially, a micro-thermal sensor array is manufactured with simple and convenient microfabrication processes to measure temperature distributions at the base of the heat sink accurately. Based on these experimental results, we suggest a correlation for the pressure drop across a microchannel heat sink subject to an impinging jet as well as a correlation for the thermal resistance of that. In addition, we show that the cooling performance of a microchannel heat sink subject to an impinging jet is superior to that of the microchannel heat sink subject to a parallel flow.

Commentary by Dr. Valentin Fuster
2003;():271-278. doi:10.1115/IPACK2003-35116.

Heat transfer and fluid flow characteristics in a micro heat pipe with curved triangular grooves are investigated using numerical and experimental methods. In the numerical part, a one-dimensional mathematical model for micro heat pipe with curved triangular grooves is developed and solved to obtain the maximum heat transport rate, the capillary radius distribution, the liquid and the vapor pressure distributions along the axial direction of the micro heat pipe under the steady-state condition. In particular, the modified Shah method is applied to calculate the pressure drop induced by the liquid-vapor interfacial shear stress. Experiments are conducted to validate the numerical model. In the experiments, the micro heat pipe with 0.56 mm in hydraulic diameter and 50 mm in length is tested. The experimental results for the maximum heat transport rate agree well with those of the numerical investigations. Finally, thermal optimization of the micro heat pipe with curved triangular grooves is performed using the numerical model.

Commentary by Dr. Valentin Fuster
2003;():279-284. doi:10.1115/IPACK2003-35121.

To seek the fan operating point on a cooling system with fans, it is very important to determine the system impedance curve and it has been usually examined with the fan tester based on ASHRAE standard and AMCA standard. This leads to a large investment in time and cost, because it could not be executed until the system is made actually. Therefore it is necessary to predict the system impedance curve through numerical analysis so that we could reduce the measurement time and effort. This paper presents how the system impedance curve (pressure drop curve) is computed by CFD in substitute for experiment. In reverse order to the experimental principle of the fan tester, pressure difference was adopted first as inlet and outlet boundary conditions of the system and then flow rate was calculated. After determining the system impedance curve, it was compared with experimental results. Also the computational domain of the system was investigated to minimize computational time.

Commentary by Dr. Valentin Fuster
2003;():285-292. doi:10.1115/IPACK2003-35129.

The present investigation concluded that the thermal behavior of the laser diode can be numerically modeled using the parabolic transient conduction equation. In addition, the current study compared the thermal performance of the continuous wave pump lasers versus the modulated wave pump lasers. This comparison revealed that the temperature of the modulated wave pump laser can approach the temperature of the continuous wave pump laser with the same average power dissipation when the frequency approaches infinity. Finally, the resulting thermal behavior was correlated and expressed in an empirical form, which physically described the thermal performance of the modulating pump laser.

Topics: Lasers , Pumps
Commentary by Dr. Valentin Fuster
2003;():293-302. doi:10.1115/IPACK2003-35131.

The thermal wave propagation behavior within a two-layered anisotropic substrate is investigated in this study using a two-dimensional hyperbolic heat conduction model. The governing equations are solved by a flux splitting algorithm based on the Godunov numerical scheme. Special attention is given to the nature of heat propagation and reflection within the composite substrate after an instantaneous release of energy. The influences of the thermal lagging behavior, anisotropic thermal conductivity, and material interfacial effect on temperature distributions are investigated. Comparisons are made between results obtained by the thermal diffusion and wave models.

Commentary by Dr. Valentin Fuster
2003;():303-307. doi:10.1115/IPACK2003-35133.

A numerical heat transfer solution is compared with an analytical solution for a microchannel flow. The analytical derivation is based upon the porous material assumption as put forth by various investigators. While extensive work exists for the rectangular microchannel cross sectional area, other cross sections have not received the same attention. It is the intent of this paper to investigate the applicability of the porous material assumption to a triangular “saw tooth” cross section microchannel with respect to heat transfer and fluid flow characteristics. The results are presented in nondimensionalized form applicable to any fluid and geometric aspect ratio combination presented herein.

Commentary by Dr. Valentin Fuster
2003;():309-315. doi:10.1115/IPACK2003-35140.

Utilizing refrigeration is one alternative to improve the operating performance of microelectronic devices. Unless large-scale refrigeration systems are acceptable, it is likely that miniature, or mesoscale, refrigerators will be required that can be directly incorporated into electronic packaging. The present study builds on the authors’ previous investigation of mesoscale refrigerators, which emphasized how only thermoelectric coolers (TEC’s) are capable of being miniaturized in the near future. Many other refrigeration systems, however, are being examined for their potential to be miniaturized, including the vapor-compression, Stirling, and pulse-tube cycles. Here a simple analysis is presented that shows the feasibility of utilizing these systems in electronics packaging. One finding is that, provided a suitable mesoscale compressor can be constructed, a vapor-compression refrigerator may yield the best performance of the investigated systems.

Commentary by Dr. Valentin Fuster
2003;():317-321. doi:10.1115/IPACK2003-35141.

To meet the insatiable demand for data bandwidth in VSR (very short reach up to 300m) applications including server and routers, parallel optical interconnection offers a promising solution in terms of performance and cost effectiveness. A 12-channel pluggable paralle optical transmitter module has been developed to achieve a data rate of 2.5 Gb/s per channel. To maintain the robustness of the optical signal integrity under different environmental conditions, the thermal management is crucial. In this paper the thermal performance evaluation of the optical module was carried out through both numerical simulation and experimental verification. The optical module mainly consists of a VCSEL (vertical cavity surface emitting laser) array, a driver IC and a heat sink. Three types of heat sinks were integrated into the transmitter module separately. The thermal environments used for this evaluation include the normal and high ambient temperature, and both still-air and forced-air conditions. The ambient temperature and the wind speed were controlled by using a Wind Tunnel. The simulation was performed by using a CFD (computational fluid dynamics) program. In all the three modules, the simulation and experimental results of the junction temperature have shown good agreements. For Module 1 under the high ambient temperature, a forced-air condition was required to keep the junction temperature below 70°C. For Module 2 and Module 3, the junction temperature can be controlled below 70°C even under the high ambient temperature without using a fan.

Commentary by Dr. Valentin Fuster
2003;():323-330. doi:10.1115/IPACK2003-35142.

This paper reviews the design of a flip chip thermal test vehicle. Design requirements for different applications such as thermal characterization, assembly process optimization, and product burn-in simulation are outlined. The design processes of different thermal test chip structures including the temperature sensor and passive heaters are described in detail. In addition, the design of fireball heater, a novel test chip structure used for evaluating the effectiveness of heat spreading of advanced thermal solutions, is also illustrated. The design considerations and processes of the package substrate and printed circuit board with special emphasis on the physical routing of the thermal test chip structures are described. These design processes are supported with thermal data from various finite-element analyses (FEA) carried out to evaluate the capability and limitations of thermal test vehicle design. Design optimization as the outcome of these analyses is also elaborated. Lastly, the validation and calibration procedures of the thermal test vehicle are presented in this paper.

Commentary by Dr. Valentin Fuster
2003;():331-336. doi:10.1115/IPACK2003-35144.

This paper reports on the numerical simulation of conjugate heat transfer from multiple electronic module packages (45 × 45 × 2.4 mm) on a printed circuit board placed in a duct. The dimensions of the modules are the same as a single module package previously studied. In the series arrangement, two module packages are installed on the center of the printed circuit board along the airflow direction. In the parallel arrangement, two and/or four module packages are installed normal to the airflow direction. In the numerical simulations, the interval between the module packages was varied and three values were considered (45, 22.5 and 9 mm). The variation of the printed circuit board thermal conductivity was also considered and 0.3, 3 and 20 W/m/K were used with the mean velocity in the duct also at three different values (0.33, 0.67 and 1 m/s). In order to derive a non-dimensional correlation from the numerical results, the concept of the effective heat transfer area previously used for a single module package was used for the multiple module packages. For the series arrangement, the effects of the interval on the effective heat transfer area are relatively low, and the numerical results can be summarized with the same correlation obtained from the single module package. On the other hand, the effective heat transfer area for the parallel arrangement is strongly affected by the parallel interval and the thermal conductivity of printed circuit board. When the interval increases, the temperature of the module packages greatly reduces as the thermal conductivity of the printed circuit board increases.

Commentary by Dr. Valentin Fuster
2003;():337-342. doi:10.1115/IPACK2003-35148.

This paper reports on indirect cooling of high-power IC chips of notebook computers using a two phase closed thermosyphon loop with Fluorinert (FC-72) as the working fluid. The experimental set-up consists of an evaporator and a condenser connected by flexible tubing. The evaporator corresponds to a high-power IC chip, and the condenser represents a cooling plate located behind the display of notebook computer. The evaporator and the condenser have the outer dimensions of 50mm × 50mm × 20mm and 150mm × 200mm × 20mm, respectively. The effects of the heat input Q and the charged volume of Fluorinert liquid F on the heat transfer characteristics of the cooling system were studied experimentally. Further, the experiment for the evaporator with plate fin to enhance the boiling in the evaporator was carried out. It has been confirmed that the heater surface temperature for the evaporator with plate fin reduces about 10% in comparison with those for the evaporator without fin. It is found that enhancing the boiling in the evaporator is very effective to reduce the surface temperature of heater. In the case of the evaporator with the plate fin, the temperature difference between the heater surface and ambient is kept around 60K for the highest heat input Q = 30W in the present experiments.

Topics: Cooling
Commentary by Dr. Valentin Fuster
2003;():343-350. doi:10.1115/IPACK2003-35151.

In modern electronic components power densities are being increased continuously while the size and weight decrease. The effective dissipating of the heat produced by these components has now become a major design problem. Ordinary heat sinks often used to dissipate this heat, can in many instances no longer be used. Heat sinks therefore need to be designed and optimized for specific applications. The design of these heat sinks requires a difficult trade-off between conflicting parameters, e.g. mass or material cost, maximum temperature and pressure drop. Since these parameters influence one another, optimum designs require the use of mathematical optimization techniques. In the case of heat sinks, the thermal engineer would typically like to optimize the design simultaneously for three design parameters. The parameters are maximum heat sink temperature, mass and pressure drop. In the formulation of such an optimization problem, where more than one design criterion is important, the engineer currently has to assign the relative importance of each design criteria before starting the optimization. A better approach is to perform a range of optimization problems where the relative importance of the design criteria is varied systematically to obtain a trade-off surface of optimum heat sinks. This surface can then be used to investigate the influence of the different design criteria on each other and to select the optimum heat sink for a specific application. In this study such a trade-off surface is created for an extruded heat sink exposed to forced convection. The constructing of this surface is obtained by combining a semi-empirical simulation program, QFin 3.0 with the DYNAMIC-Q optimization method.

Commentary by Dr. Valentin Fuster
2003;():351-356. doi:10.1115/IPACK2003-35156.

Thermal design and packaging strategy of a prototype dual-loop vapor compression refrigeration cooling system, developed as a pilot model for thermal management of high performance CMOS based MCMs, is introduced in this paper. The cooling system was comprised of two separated refrigeration units providing low temperature cooling via a dual-path cooling module (evaporator) mounted on a CPU-MCM package. Cooling capacity for each refrigeration unit was controlled ranging from 250W to 2500W with a refrigerant evaporating temperature at −25 degree centigrade. The CPU-MCM mounted with the refrigeration cooling module was packaged on a system board assembly, together with other electronic devices. The assembly was accommodated into a dew-point control box where two dewpoint control units were operating in a redundancy to remove moisture and keep a dew temperature inside the box below −30 degree centigrade for completely preventing from condensation. Cooling redundancy was provided by both the refrigeration units and dual-path cooling module. The cooling module was redundant in that two sets of refrigerant passages were staggered within a thin copper plate, where each set was connected to a separated refrigeration unit. Apart from the robust system and steady operation, the configuration and operation mode also provided the cooling system a high power efficiency and much shortened starting time. Numerical simulations were also performed for investigating airflow and thermal characteristics, in a system board level inside the dew-point control box. Detailed predictions of airflow and temperature distributions were significantly helpful for improving and verifying practical system designs.

Commentary by Dr. Valentin Fuster
2003;():357-362. doi:10.1115/IPACK2003-35161.

The development of hardware needs cost reduction by shortening a development period and reducing experimental man-hour. In order to satisfy these demands, thermal fluid analysis with higher accuracy in short time is indispensable for product development. At present, thermal fluid analyses are conducted using different software tools. Each software tool requires model building and meshing for simulations using its own format. That leads to a large investment in time, and therefore cost. VPS/Simulation-Hub software Fujitsu developed is able to convert data from various CADs. It has the features to create a data fitting to numerical analysis software, create an accurate analysis model, and delete unnecessary components. With these main features, VPS/Simulation-Hub greatly contributes to the man-hour reduction for model building and the improvement of analytical accuracy. In this paper, VPS/Simulation-Hub is introduced with the detail explanation of the above 3 main features.

Commentary by Dr. Valentin Fuster
2003;():363-374. doi:10.1115/IPACK2003-35169.

A transient thermal analysis is performed to investigate thermal control of power semiconductors using phase change materials, and to compare the performance of this approach to that of copper heat sinks. Both the melting of the phase change material under a transient power spike input, as well as the resolidification process, are considered. Phase change materials of different kinds (paraffin waxes and metallic alloys) are considered, with and without the use of thermal conductivity enhancers. Simple expressions for the melt depth, melting time and temperature distribution are presented in terms of the dimensions of the heat sink and the thermophysical properties of the phase change material, to aid in the design of passive thermal control systems. The simplified analytical expressions are verified against more complex numerical simulations, and are shown to be excellent tools for design calculations. The suppression of junction temperatures achieved by the use of phase change materials when compared to the performance with copper heat sinks is illustrated. Merits of employing phase change materials for pulsed power electronics cooling applications are discussed.

Commentary by Dr. Valentin Fuster
2003;():375-380. doi:10.1115/IPACK2003-35175.

An insulated metal substrate (IMS) is a circuit board comprising an insulating layer on a metal base plate. The insulating layer is made from epoxy resin incorporating dense inorganic fillers with high thermal conductivity. Because the substrates have high thermal conductivity, they are used in applications where electric parts generate intense heat, such as inverters, amplifiers, motor drivers and so on. It is expected that the insulating layer has higher thermal conductivity as the use of an IMS is expanded. Therefore, the influence of percolation on the equivalent thermal conductivity of an insulating layer is considered. The effect of the volume fraction of inorganic filler on the equivalent thermal conductivity of insulating layer in IMS is experimentally investigated. The equivalent thermal conductivity of insulating layer as a function of volume fraction of filler is estimated by FEM and Monte Carlo technique together. The acquired value of percolation threshold volume fraction is the same grade as the previous reported value. Based on these experimental and numerical results, an effective thermal conductivity of a filler which contains surrounding interfacial region is evaluated. The effective thermal conductivity of an irregular filler is presumed smaller than that of a spherical filler. It is noted that the control of filler size and shape is important for the formation of high thermal conductivity of an insulating layer. In addition, an improved equation for the equivalent thermal conductivity of insulating layer in IMS is proposed. The predictive values from the equation for insulating layer in an improved IMS agree with experimental results.

Commentary by Dr. Valentin Fuster
2003;():381-387. doi:10.1115/IPACK2003-35183.

The unsteady laminar flow and heat transfer characteristics for a pair of confined impinging air jets centered in a channel were studied numerically. The time-averaged heat transfer coefficient for a pair of heat sources centered in the channel and aligned with the jets was determined as well as the oscillating jet frequency for the unsteady cases. The present study continues the authors’ previous investigation, which emphasized how single confined jets will remain steady at Reynolds numbers that make side-by-side jets highly unsteady. The nature of this unsteadiness depends on the proximity of the jet inlets, the channel dimensions and the jet Reynolds number. The jet unsteadiness causes the stagnation point locations to sweep back and forth over the impingement region, and the jets “wash” a larger surface area on the target wall. The results indicate that the dual jets become unsteady between a Reynolds number of 200 and 300. Also, in the range of Reynolds numbers studied, a fixed stagnation “bubble” was formed on the target wall between the two jets, which reduced the heat transfer removal from that region, leading in fact to a quasi-independence of the local heat transfer on flow conditions. The stagnant region contains slow moving warm air that forces the cool impinging air jets to flow to the sides of this target wall area. The oscillating frequency of the flow increases with Reynolds number for the unsteady cases. Also, the time-averaged heat transfer coefficient on the heat sources rises as the Reynolds number increases for the steady cases but there is a slight decrease when it transitions to unsteady flow, indicating again that the stagnation “bubble” occurring between the two heat sources affects the local heat transfer.

Commentary by Dr. Valentin Fuster
2003;():389-394. doi:10.1115/IPACK2003-35186.

The power of semiconductor chips, especially the CPU chip used in the notebook computer, is increasing nowadays while the size of the computer box is decreasing. To cope with this ever-increasing heat load within the notebook computer, many design engineers tend to use bigger heat sinks and fans. However, these approaches add weight, acoustic noise, and power consumption to the computer, none of which is desirable. A method of transferring heat from a CPU chip to the backside of the liquid-crystal display (LCD) and letting heat dissipate into the surroundings has been explored before. This is sometimes called the thermal hinge method since heat is transferred across the hinge of a notebook computer. In this paper, the structure of a new thermal hinge and its thermal performance will be revealed. This new thermal hinge has two main parts: one is the base, which is stationary and which has a heat pipe connected to a metal plate on top of a CPU chip, and the other is the rotational part, which is mounted on the LCD cover with a heat pipe connected to a heat spreader. The base is supported by a set of springs to ensure that the base is always in good thermal contact with the rotational part of the hinge. This spring-loaded thermal hinge using an aluminum heat spreader on a plastic LCD cover was built and tested and the results were compared with a numerical model that was constructed using a commercially available CFD code. The results from the experiments and numerical modeling agree reasonably well. Because of this, the numerical model has been used to optimize the hinge structure. The effects of the size, thickness, and materials of the heat spreader as well as the materials of the LCD cover on the hinge thermal performance have been studied and will be discussed.

Commentary by Dr. Valentin Fuster
2003;():395-400. doi:10.1115/IPACK2003-35187.

This program, addresses the need for thermal management of increasingly powerful and densely packaged electronic devices. Open-celled foams and lattice structures offer the promise of much improved heat transfer between the coolant and the solid structure of the lattice compared to traditional finned heat exchangers. The focus of this program is to evaluate integration of foam and lattice materials as heat exchanger cores and as electronic racks. The potential benefits of this approach include reduction in the volume and weight of the heat exchanger core and/or device junction temperature as well as direct attach cooling of high power electronics. To begin we have selected two major applications, a liquid cooling system heat exchanger, and avionics rack cooling. There is little data on foam metal heat transfer in the regime we anticipate for aircraft applications. Our approach begins with the measurement of heat transfer characteristics of compressed foam metals under conditions suitable for aircraft applications. Basic heat transfer data is being obtained for heat removal from a heated surface by “foam metal fins” with air flowing through the foam. Effective heat transfer coefficient and airflow resistance have been measured. The test method and apparatus are briefly described. Results of heat transfer measurements to date are presented. A theoretical model of “foam metal fins” has been developed and is applied for scaling foam metal fins within our test matrix. Using the model we determine the heat transfer coefficient between the air and foam ligaments. These heat transfer coefficients are compared with cylinders in cross flow. We applied our measured heat transfer characteristics to the design, fabrication and verification test of a highly efficient heat exchanger core. A laboratory scale thermal performance demonstration core was sized based on our test results. Initial tests of a single air / liquid heat exchanger core leg validates our core sizing. Our results can also be applied to cooling of individual electronic components as well as cold plates for electronics.

Commentary by Dr. Valentin Fuster
2003;():401-409. doi:10.1115/IPACK2003-35190.

The effect of boundary conditions on heat transfer in rectangular microchannels is investigated. Of primary interest in this study is the influence of the boundary conditions on the temperature gradients in such geometries. The top of the microchannel under consideration is exposed to a uniform heat flux, which simulates the energy dissipated from electronic chips. Cooling fluid is allowed to flow through channels underneath the heat source. The physical configuration is subjected to various boundary conditions (e.g., first, second, and third kinds) and any combination of convection and radiation energy exchanges between the exposed surfaces and the external environment. The current configuration covers typical situations as found in most electronic cooling systems. The influences of the heat source strength, the external environment, and the aspect ratio are studied. The effects of varying these factors in a range typical of electronics thermal management applications are investigated. Temperature gradients along the fluid flow direction and their effect on the fluid resistance are presented.

Commentary by Dr. Valentin Fuster
2003;():411-416. doi:10.1115/IPACK2003-35196.

A methodology for automatically generating compact thermal network models of increasing complexity, for use in numerical simulations of general semiconductor integrated circuit (IC) packages is presented. The method is based on the multi-grid agglomeration of the underlying mesh used in the finite volume discretization of the energy conservation equation of the package. The method is applied to a 196-pin fine pitch ball grid array (FBGA) package. Various network topologies and the corresponding network conductances were automatically extracted for this package. These networks were then used in computational fluid dynamics (CFD) simulations for a range of boundary conditions corresponding to single-phase natural and forced convective cooling. Results show good agreement with the detailed package simulations.

Commentary by Dr. Valentin Fuster
2003;():417-421. doi:10.1115/IPACK2003-35198.

In a laboratory environment, flexible, accurate and reliable thermal management is critical to successful analysis and testing of a single package IC device under test (DUT). As next generation electronic components approach a heat flux of 200W/cm2 , the control aspects of the thermal management system become even more critical. Utilizing advanced vapor-compression refrigeration technology in conjunction with PID control algorithms, accurate thermal management of a DUT is achieved. In order to accurately control the temperature, the control system monitors case (TC ), evaporator (TE ), or internal junction (TJ ) temperature and employs real time pulse width modulation control of refrigerant flow to achieve accurate control to less than ±3°C. The system also includes the capability to monitor the actual power supplied to the DUT and is capable of control up to a thermal load of 200W. This paper presents the requirements for and the design of the thermal control system utilized in a high heat-flux, laboratory-based thermal management system.

Commentary by Dr. Valentin Fuster
2003;():423-428. doi:10.1115/IPACK2003-35201.

The heat conduction equation and its boundary conditions were used to show that the planar and normal thermal conductivities of an orthotropic model of a printed circuit board were functions of source to board size ratio, top and bottom side boundary conditions, and thickness and thermal conductivity of each layer. Numerical solutions of the heat conduction equation were used to quantify the dependence on source to board size ratio and top and bottom boundary conditions. It was shown that the thermal conductivities were stronger functions of the source to board size ratio for smaller values of this ratio. This dependence was more pronounced for boards with stronger convection heat transfer on their top side, and for boards with thicker component side copper layer. The thermal conductivities were less sensitive to the variation of the convection heat transfer on the bottom side of the board.

Commentary by Dr. Valentin Fuster
2003;():429-434. doi:10.1115/IPACK2003-35210.

The airflow management for multi-board rack-mount equipment has to meet certain requirements including a minimum air velocity over the boards, uniform air velocity from board to board and from front to rear, and fan redundancy. These requirements have to be met within certain size, noise level and reliability constrains. Several configurations are usually considered: “push” or pressurized system, “pull” or vacuum system, and “push-pull” system. The purpose of this article is to demonstrate the airflow management design process for the three system configurations mentioned above, and to compare their optimum designs with each other given a set of geometrical constraints such as the overall dimensions of the equipment chassis, the card cage, and the type and thickness of the air filter. The design process is explained as a case study involving a typical multi-board rack mounted telecommunication chassis.

Topics: Air flow
Commentary by Dr. Valentin Fuster
2003;():435-442. doi:10.1115/IPACK2003-35213.

The increasing trend in power levels and densities leads to the need of design thermal optimization, at either module or system level. A numerical study using finite-volume software was conducted to model the transient thermal behavior of a system including a package dissipating large amounts of power over short time durations. The system is evaluated by choosing the appropriate heat sink for the efficient operation of the device under 100W of constant powering, also to enhance the thermal performance of the enclosure/box containing the test stack-up. The intent of the study is to provide a meaningful understanding and prediction of the high transient powering scenarios. The study focuses on several powering and system design scenarios, identifying the main issues encountered during a normal device operation. The power source dissipates 100W for 2 seconds then is cooled for another 2 seconds. This thermal cycle is likely to occur several times during a normal test-up, and it is the main concern of the manufacturers not to exceed a limit temperature during the device testing operation. The transient trend is further extrapolated analytically to extract the steady state peak temperature values, in order to maintain the device peak temperatures below 120°C. The benefit of the study is related to the possibility to extract the maximum/minimum temperatures for a real test involving a large number of heating-cooling cycles, yet maintaining the initial and peak temperatures within a certain range, for the optimal operation of the device. The flow and heat transfer fields are thoroughly investigated. By using a combination of numerical and analytical study, the thermal performance of the device undergoing infinity of periodic thermal cycles is further predicted.

Commentary by Dr. Valentin Fuster
2003;():443-450. doi:10.1115/IPACK2003-35216.

Increased functionality of microelectronic packages for commercial applications leads to the necessity of identifying packaging solutions with high standards for thermal performance, during its functioning lifetime as well as during various test conditions. A detailed numerical analysis examines the thermal characteristics of a power amplifier module for time division multiple access (TDMA), using commercially available software. The increasing trend in power levels and densities leads to the need of design thermal optimization, either at module level or system level. Under specific test conditions, the thermal performance of the module degrades gradually; therefore, alternative test designs are investigated for thermal performance optimization. Initial study focuses on assessing the thermal performance of a baseline design. The peak temperature reaches 144°C, about 60°C temperature increase over the reference temperature. The peak temperature value is below the limit of 150°C. Further investigation focuses on several systems level designs, by incorporating individual test contactors between the DUT and load board or with conductive elastomers or pedestal solid ground slug for thermal performance enhancement. The peak temperatures are calculated in this case for the system being exposed to the ambient at 85°C. The results indicate that the test design with solid ground slug provides the best thermal performance, ∼ 5% better than the other designs. The small difference between the first two designs (with individual contactors and separate solid ground slug with conductive elastomer) resides in the fact that the elastomer has a small thickness (0.25mm), thus a low thermal resistance (based on thermal conductivity greater than 1W/mK), with minimal impact on the overall thermal performance of the TDMA under current test conditions. The temperature difference between the top section of the contactor designs with the CBC pin/copper block/pedestal is small; in spite of this, the high temperature reached by the individual CBC pins induces possible failures in the elastomer. The designs with pedestal and solid ground slugs have a notable advantage over the design with individual contactors, due to no moving parts within the elastomer, being more robust. The peak temperature reached by the module under the best/worst testing scenarios varies by ∼ 4–5%.

Topics: Optimization
Commentary by Dr. Valentin Fuster
2003;():451-454. doi:10.1115/IPACK2003-35217.

A failure analysis on microelectronic packages subjected to temperature cycling between liquid baths required the need for realistic boundary conditions in the thermal analysis portion of the overall thermal stress analysis. Prior arts found in literature for thermal film coefficients in immersion cooling focused only on metallurgical quenching. The results indicated that these data are highly dependant on temperature, thus not applicable since they were derived for quenching of steel at higher initial temperatures. An alternative technique was developed here by assuming that the package could be modeled as a semi-infinite solid for the time interval of interest, and that the fluid is quiescent for the time interval. The effects on the film coefficient of the motion of the package into the liquid bath are neglected. These assumptions enable the use of the available analytical solution for bringing two semi-infinite solids in contact. By being able to model the fluid as a semi-infinite solid, we can then differentiate the solution for transient heat flow in a semi-infinite body subject to a step change in surface temperature to obtain the heat flux from the surface of the package. The temperature difference between the package surface and the bulk fluid temperature then cancel out of the equation for the film coefficient leaving a closed form solution for the effective calculation of a time dependent film coefficient, which can then be applied as a boundary condition in a numerical thermal analysis. The expression for the film coefficient was found to be proportional to the fluid effusivity divided by the square root of the elapsed time.

Commentary by Dr. Valentin Fuster
2003;():455-460. doi:10.1115/IPACK2003-35227.

With the power levels of computers constantly rising, the cooling of the die is becoming more challenging. One method of heat removal that can handle high heat fluxes and is still compact in size is Spray Evaporative Cooling (SEC). SEC, in this instance, uses arrays of nozzles to deliver a fluorinert cooling fluid, FC-72, to the die surface, and in the right conditions, a thin liquid film will form. This thin film allows for very high heat removal. Saturating the FC-72 with nitrogen enhances the effect. The characteristics of the spray greatly affect the behavior of the film. The critical heat flux (CHF), heat transfer coefficient of the system, and the variation in temperature on the die surface are important characteristics of an SEC system that must be considered. This study presents results of experiments performed to determine the effect of the number of spray nozzles on these quantities.

Commentary by Dr. Valentin Fuster
2003;():461-466. doi:10.1115/IPACK2003-35231.

The density of packaging in electronic enclosures is increasing rapidly and the real estate available for packaging high power ASICs and processors is decreasing very rapidly as well. This work presents a study where packages are mounted below the board and the ASICs are cooled using the sheet metal tray as the heat spreader. The heat is transferred from the processor or the chip to the sheet metal tray through metallic blocks or heat spreaders by conduction and then the sheet metal tray is cooled convectively by airflow between two successive boards. There are various issues to be encountered when we do such a design for reverse mount packages like the maximum stress exerted on the ASIC, the kind of interface material that should be used to minimize the stress induced on the ASIC and also keeping in mind the thermal impedance of the interface material. The study presents simulation and experimental results that illustrate the concept of using the sheet metal tray as a heat spreader and also discuss potential applications of this concept. Considerations and precautions to be taken while executing this concept are also addressed.

Commentary by Dr. Valentin Fuster
2003;():467-472. doi:10.1115/IPACK2003-35233.

Liquid cooling is used for thermal management of electronics in defense, power, medical, and computer applications due to the increasing power density and the desire for compact packaging. The objectives in the design of these systems are to create a sufficient amount of total flow and to appropriately distribute the flow so as to maintain the electronic component temperatures at the desired level. The technique of Flow Network Modeling (FNM) is ideally suited for the analysis of flow distribution and heat transfer in liquid-cooling systems. The FNM technique uses overall flow and thermal characteristics to represent the behavior of individual components. Therefore, solution of conservation equations over the network enables efficient prediction of the flow rates, pressures, and temperatures in a complete liquid-cooling system. This article describes the technical basis of the FNM technique and illustrates its application in the design of a distributed-flow cold plate and of a complete water-cooled system. The study demonstrates the utility of the FNM technique for rapid and accurate evaluation of different design options and the ensuing productivity benefits in the design of liquid cooling systems.

Commentary by Dr. Valentin Fuster
2003;():473-479. doi:10.1115/IPACK2003-35237.

Large pressure drops, and the associated pumping requirements, are often considered the most critical factor hindering widespread commercial use of microchannel heat sinks. Analytical methods are used in the present work to arrive at the pumping requirements for any given microchannel heat sink. A graphical method to check the suitability of a pump to a microchannel heat sink application has been devised. The size of the microchannels is also optimized so that for a specified heat removal rate, the pumping requirements are minimized. A number of commercially available pumps as well as several micropumps presented in the literature are compared based on their flow rate, pressure head and physical size to assess their suitability for a specific representative cooling application.

Commentary by Dr. Valentin Fuster
2003;():481-493. doi:10.1115/IPACK2003-35240.

This paper focuses on the effect on inlet rack air temperatures when adjacent racks are removed. Only the above floor (raised floor) flow and temperature distributions were analyzed for various air flowrates exhausting from the perforated tiles and the rack. A Computational Fluid Dynamic (CFD) model was generated for the room with electronic equipment installed on a raised floor with particular focus on the effects on rack inlet temperatures of these high powered racks. The baseline case was with forty racks of data processing (DP) equipment arranged in rows in a data center cooled by chilled air exhausting from perforated floor tiles. The chilled air was provided by four A/C units placed inside a room 12.1 m wide × 13.4 m long. Since the arrangement of the racks in the data center was symmetric only one-half of the data center was modeled. To see the effect of missing racks adjacent to high powered racks various configurations were analyzed. The numerical modeling was performed using a commercially available finite control volume computer code called Flotherm (Trademark of Flomerics, Inc.). The flow was modeled using the k-e turbulence model. Results are displayed to provide some guidance on the design and layout of a data center.

Commentary by Dr. Valentin Fuster
2003;():495-508. doi:10.1115/IPACK2003-35241.

This paper focuses on the effect on inlet rack air temperatures when rack flowrates are reduced. Reduced flowrates for the same heat loads results in higher air temperature differences across the rack and thereby higher air temperatures exiting the rack. The effect of the higher rack exhaust temperatures on the inlet rack air temperatures is the focus of this investigation. Only the above floor (raised floor) flow and temperature distributions were analyzed for a range of rack flowrates and with various flowrates exhausting from the perforated tiles. A Computational Fluid Dynamic (CFD) model was generated for the room with electronic equipment installed on a raised floor with particular focus on the effects on rack inlet temperatures of these high powered racks. Fourty racks of data processing (DP) equipment were arranged in rows in a data center cooled by chilled air exhausting from perforated floor tiles. The chilled air was provided by four A/C units placed inside a room 12.1 m wide × 13.4 m long. Since the arrangement of the racks in the data center was symmetric only one-half of the data center was modeled. The numerical modeling was performed using a commercially available finite control volume computer code called Flotherm (Trademark of Flomerics, Inc.). The flow was modeled using the k-e turbulence model. Results are displayed to provide some guidance on the design and layout of a data center.

Commentary by Dr. Valentin Fuster
2003;():509-516. doi:10.1115/IPACK2003-35242.

A compact, energy efficient heat sink design methodology is presented for shrouded, parallel plate fins in laminar flow. The analytic model accounts for the sensible temperature rise of the air flowing between fins, convective heat transfer to the flowing stream, and conduction in the fins. To evaluate the efficiency of the air cooling system, consideration is also given to the determination of the fan pumping power. This paper focuses on the optimization of the heat sink-fan combination for energy efficiency, subject to volumetric constraints. The design optimum is found by matching the most efficient operating point of the fan with the corresponding optimum fin geometry. A series of parametric studies was completed to identify the sensitivity of the cooling solution to parametric variations. This numerically validated model has been used to visualize the parametric impact of dealing with “real world” manufacturing limitation in the development of thermal packaging solutions for notebook computers and other electronic products.

Commentary by Dr. Valentin Fuster
2003;():517-525. doi:10.1115/IPACK2003-35245.

Thermal management of modern electronics has become a problem of significant interest due to the demand for power and reduction in packaging size. Requirements of next-generation microprocessors in terms of power dissipation and heat flux will certainly outgrow the capability of today’s thermal control technology. LHPs, like conventional heat pipes, are capillary pumped heat transport devices. They contain no mechanical moving part to wear out or require electrical power to operate. But unlike heat pipes, LHPs possess much higher heat transport capabilities enabling them to transport large amounts of heat over long distances in small flexible lines for heat rejection. In fact, a miniature ammonia LHP developed for a NASA space program is capable of transporting 60W over a distance of 1 meter in 1/16”O.D. stainless steel tubing. Therefore, miniature LHPs using water as the working fluid are excellent candidates to replace heat pipes as heat transports in electronic cooling systems. However, a number of operational issues regarding system performance, cost, and integration/packaging must be resolved before water LHPs can become a viable option for commercial electronics.

Commentary by Dr. Valentin Fuster
2003;():527-535. doi:10.1115/IPACK2003-35251.

Gas or liquid flow in multiple, parallel micro-channels is of interest for Micro-Electro-Mechanical Systems (MEMS) cooling applications. The published data for friction in 10-to-400μm hydraulic diameter, single micro-channels show good agreement with the conventional equations in the laminar and turbulent regimes. However, investigators of flow in multiple, parallel micro-channels in the same range of channel sizes report significantly different results. They report significant disagreement with the conventional equations and argue that transition occurs at Reynolds numbers as small as 200, dependent on the channel shape. This paper proposes that the apparent discrepancies of friction in multiple micro-channels can be attributed to flow mal-distribution. Flow mal-distribution is expected in multi-channels, because of manufacturing tolerances and poor manifold design. It can be minimized by proper header design and better manufacturing tolerances.

Commentary by Dr. Valentin Fuster
2003;():537-543. doi:10.1115/IPACK2003-35253.

This paper provides an update on work at Penn State University on advanced thermal interface material (TIM) and attachment technology. The TIM concept consists of a “Low Melting Temperature Alloy” (LMTA) bonded to a thin copper substrate. The present work includes analytical modeling to separate the interface resistance (Rint ) into “material” and “contact” resistance. Modeling indicates that contact resistance accounts for 1/3 of the interface resistance (Rint ). Additional alloys have been identified that have thermal conductivity approximately three-times those identified in the previous 2002 publication. Thermal degradation of the LMTA TIM was also observed in the present work after extended thermal cycling above the melting point of the alloy. Possible mechanisms for this degradation are oxidation and contamination of the alloy layer rather than the inter-metallic diffusion. Use of the high thermal conductivity alloys, and soldered contact surfaces will provide very low Rint as well as minimizing the thermal degradation. It appears that Rint as small as, or less than, 0.005 cm2 -K/W may be possible. Description of the modified Penn State TIM tester is provided, which will allow measurement of Rint = 0.01 cm2 -K/W with less than 30% error.

Commentary by Dr. Valentin Fuster
2003;():545-550. doi:10.1115/IPACK2003-35256.

Advances in RF power generation capability at the device level will soon force a change in phased array radar thermal management. The efficiency in converting electrical power into transmitted power is not increasing as rapidly which means that higher RF power generating devices also dissipate more heat. Removing this waste heat creates several thermal challenges including the topic of this paper, namely thermal issues at the die and package level. A comparison of the temperature differences between the junction and ambient shows that even at present heat dissipation levels, the temperature difference at the integrated circuit level is already a significant fraction of the total rise. Further increases in the device level heat dissipation will increase the temperature difference at the integrated circuit level to nearly unmanageable levels unless device-level design changes are made. Maintaining acceptable junction temperature levels will require lower device mounting surface temperatures or some thermally better method of die attachment and heat removal. Dividing the thermal management of a phased array radar into two portions (integrated circuit level and everything else) reveals that while thermal improvements at the system and packaging level are useful for near-future radar designs, thermal design and management at the device and package levels are crucial.

Commentary by Dr. Valentin Fuster
2003;():551-556. doi:10.1115/IPACK2003-35259.

Thermal interface materials are crucial to improving the overall performance of an active device and the design/selection of a thermal management system. In most practical thermal management protocols, interface materials are used to enhance heat transfer by reducing thermal resistance across contact surfaces. This improves surface contact by forming a continuous path of heat across an interface. This paper focuses on characterizing a thermal control unit (TCU) and employing the thermo-electric technology (TEC) in a liquid cooling system, using selected interface materials mounted on the TEC surfaces. Qualification tests performed on several common interface materials within the TCU are presented in this paper, with results compared to surface-to-surface contact. Tests included the measurement of minimum achievable device case temperature and the minimum TCU thermal resistance as a function of the net heat using selected interface materials. In addition, package minimum case temperature was measured as a function of pressure exhibited on the interface material to determine the TEC optimum contact pressure. Based on results, graphite base interface material was selected as an optimum interface material between TEC assembly and the TCU internal components.

Commentary by Dr. Valentin Fuster
2003;():557-565. doi:10.1115/IPACK2003-35260.

A number of modeling approaches of increasing levels of complexity for the analysis of convective heat transfer in microchannels are presented and compared. A detailed computational fluid dynamics (CFD) model is used to obtain baseline results against which the different approximate approaches are compared. These include a 1-D resistance model, a fin approach, two fin-liquid coupled models, and a porous medium approach, all of which are amenable to closed-form solutions for the temperature field. The good agreement between the exact and approximate methods indicates that with carefully chosen assumptions, these analytical results can lead to adequate descriptions of the thermal performance, while allowing easier manipulation of microchannel geometries for the purpose of optimization. Practical optimization procedures are developed to minimize the overall thermal resistance of microchannel heat sinks, using each of the five approaches.

Commentary by Dr. Valentin Fuster
2003;():567-573. doi:10.1115/IPACK2003-35264.

A new method for determining effective thermal conductivity and Young’s modulus in thermal interface materials is demonstrated. The method denoted as the Bulk Resistance Method (BRM) uses empircal thermal resistance data and analytical modeling to accurately predict thermophysical properties that account for insitu changes in material thickness due to external loading and thermal expansion. The BRM is demonstrated using commercially available sheets of Grafoil GTA. Tests were performed on thermal joints consisting of two Al 2024 machined surfaces with layers of Grafoil GTA in the interface. Test conditions included a vacuum environment, 0.2–6.5 MPa contact pressure, a nominal 50°C mean interface temperature and a continuous loading and unloading cycle. Test results indicated that the BRM consistently predicted thermal conductivity independent of the number of layers tested and that the predicted results were significantly lower than values reported using conventional ASTM test procedures.

Commentary by Dr. Valentin Fuster
2003;():575-585. doi:10.1115/IPACK2003-35267.

Pool boiling from a surface featuring micro-pyramidal re-entrant cavities (mouth size 40 μm) etched in silicon, on a glass substrate, was studied. All experiments were conducted in the dielectric fluid FC-72 at one atmosphere. The heat sink is designed to eliminate spreading through the substrate, and back heat loss. Experimentation showed that the critical heat flux was 12.8 W/cm2 . A high speed camera (400fps) was used to record and quantify the effect of heat flux on departure diameter and bubble emission frequency. Both departure diameter and frequency showed an increasing trend with heat flux. Comparison with existing literature are also presented.

Commentary by Dr. Valentin Fuster
2003;():587-596. doi:10.1115/IPACK2003-35268.

Extensive experiments were performed aimed at obtaining physical insight into the behavior of in-line pin fin heat sinks with pins of square cross-section. Detailed pressure measurements were made inside an array of square pins in order to isolate the inlet, developing, fully developed, and exit static pressure distributions as a function of row number. With this as background data, overall pressure drop was measured for a self-consistent set of aluminum heat sinks in side inlet side exit flow, with top clearance only. Pin heights of 12.5 mm, 17.5 mm, and 22.5 mm, pin pitch of 3.4 mm to 6.33 mm, and pin thickness of 1.5 mm, 2 mm and 2.5mm were evaluated. Base dimensions were kept fixed at 25 × 25 mm. In total, 20 aluminum heat sinks were evaluated. A “two-branch by-pass model” was developed, by allowing inviscid acceleration of the flow in the bypass section, and using pressure loss coefficients obtained under no bypass conditions in the heat sink section. The experimental data compared well to the proposed hydraulic models. Measurements in the array of pins showed that full development of the flow occurs after nine rows, thus indicating that none of the heat sinks tested could be characterized as fully-developed.

Commentary by Dr. Valentin Fuster
2003;():597-604. doi:10.1115/IPACK2003-35270.

The thermal resistance of in-line square-pin fin heat sinks was experimentally investigated. In a companion paper [1], extensive results for the hydraulic behavior of such heat sinks with and without top-bypass were reported. It was shown that the top-bypass, as well as pin pitch, strongly influence the fin flow available for cooling. Systematic measurements of the overall thermal resistance with a uniformly heated base were performed for the same set of twenty aluminum heat sinks. Pin height was varied from 12.5 mm to 22.5 mm, pin pitch was varied from 3.4 mm to 6.33 mm, and base dimensions were kept fixed at 25 × 25 mm. The overall base to ambient thermal resistance was measured as a function of heat sink geometry, approach velocity and by-pass height. Experimental results were compared with predictions based on a simple one-dimensional “two-branch bypass model”. It was found that the overall heat transfer is governed by the fin flow, hence, empirical data for the zero bypass case can be used to predict the decrease of heat sink performance with flow bypass.

Commentary by Dr. Valentin Fuster
2003;():605-612. doi:10.1115/IPACK2003-35273.

Today’s data centers are designed for handling heat densities of 1000W/m2 at the room level. Trends indicate that these heat densities will exceed 3000W/m2 in the near future. As a result, cooling of data centers has emerged as an area of increasing importance in electronics thermal management. With these high heat loads, data center layout and design cannot rely on intuitive design of air distribution and requires analytical tools to provide the necessary insight to the problem. These tools can also be used to optimize the layout of the room to improve energy efficiency in the data center. In this paper, first an under floor analysis is done to find an optimized layout based on flow distribution through perforated tiles, then a complete Computational Fluid Dynamics (CFD) model of the data center facility is done to check for desired cooling and air flow distribution throughout the room. A robust methodology is proposed which helps for fast, easy, efficient modeling and analysis of data center design. Results are displayed to provide some guidance on the layout and design of data center. The resulting design approach is very simple and well suited for the energy efficient design of complex data centers and server farms.

Commentary by Dr. Valentin Fuster
2003;():613-619. doi:10.1115/IPACK2003-35278.

The combination of increased power dissipation and increased packaging density has led to substantial increases in chip and module heat flux in high-end computers. The challenge has been to limit the rise in chip temperature. In the past virtually all-commercial computers were designed to operate at temperatures above the ambient. However researchers have identified the advantages of operating electronics at low temperatures. The current research focuses on IBM’s mainframe, which uses a conventional refrigeration system to maintain chip temperatures below that of comparable air-cooled systems, but well above cryogenic temperatures. An experimental bench was built to study the effect of variation of evaporator outlet superheat on system performance. Three different types of thermostatic expansion valves were tested in order to verify that the bulb size and bulb location have significant effect on the transient behavior of the system. Bulbs of each of the three thermostatic expansion valves were mounted at five different locations on the suction line. It was observed that the overall system stability increases as we move closer to the evaporator exit. It was also observed that there exists a region in the suction line at which the superheat variation is the least and placing the bulb at this region gives maximum stable operation of the system. This region can be defined as the minimum stable superheat point. Tests were conducted at five different load conditions 1000W, 750W, 500W, 250W and no load condition. It was observed that the system was the most stable at full load condition for all three types of valves and system stability consistently decreased as the load was decreased.

Commentary by Dr. Valentin Fuster
2003;():621-628. doi:10.1115/IPACK2003-35282.

In raised-floor data centers, the airflow rates through the perforated tiles must meet the cooling requirements of the computer servers placed next to the tiles. The data centers house a wide range of equipment, and the heat load pattern on the floor can be quite arbitrary and changes as the data center evolves. To achieve optimum utilization of the floor space and the flexibility for rearrangement and retrofitting, the designers and managers of data centers must be able to modify the airflow rates through the perforated tiles. The airflow rates through the perforated tiles are governed primarily by the pressure distribution under the raised floor. Thus, the key to modifying the flow rates is to influence the flow field in the plenum. This paper discusses a number of techniques that can be used for controlling airflow distribution. These techniques involve changing the plenum height and open area of perforated tiles, and installing thin (solid and perforated) partitions in the plenum. A number of case studies, using a mathematical model, are presented to demonstrate the effectiveness of these techniques.

Commentary by Dr. Valentin Fuster
2003;():629-634. doi:10.1115/IPACK2003-35294.

Processor powers of 30–60W are becoming very common in electronic industry. With constraints such as available heat sink space and the cost of the thermal solution, heat sink optimization has become one of the major concerns in the final design process. In this work two (new) strategies are proposed along with the traditional heat sink optimization process (i.e. fin/base thickness and fin spacing optimization). First, heat pipes are embedded into the aluminum base extruded heat sink to reduce spreading resistance. The resulting heat sink is more efficient and even cheaper when compared to the bounded-fin technology on a copper base. Second, the angled base modification is introduced to reduce the spreading resistance in the flow direction. It is observed that up to 5 degrees angle in the base can reduce the thermal resistance of an active heat sink by 8–10%.

Commentary by Dr. Valentin Fuster
2003;():635-640. doi:10.1115/IPACK2003-35299.

This paper describes a new gravity-independent version of a two-phase cooling, closed heat transfer cell, similar to a thermosyphon. The cooling method is based upon a Vibration-Induced Droplet Atomization, or VIDA, process that can generate small liquid droplets inside a closed cell and propel them onto a heated surface. The VIDA technique involves the violent break-up of a liquid film into a shower of droplets by vibrating a piezoelectric actuator and accelerating the liquid film at resonant conditions. A piezoelectric diaphragm pump is used to supply a constant stream of liquid to the VIDA atomizer enabling gravity-independent operation. The atomized secondary droplets continually coat the heated surface with a thin liquid film that evaporates. The resulting vapor is condensed on internal surfaces of the heat transfer cell as well as the liquid working fluid. The condensed liquid is collected and returned to the atomizing driver by the piezoelectric diaphragm pump. A small-scale gravity independent VIDA atomizer generating spherical droplets of relatively uniform diameter and having sufficient momentum to reach the remotely located heated source has been constructed. Initial test data described in this study include the operating characteristics of the VIDA spray and heat transfer capabilities. Heat dissipation levels as high as 195 W have been measured from an evaporation surface held below 120°C at atmospheric pressure.

Commentary by Dr. Valentin Fuster
2003;():641-645. doi:10.1115/IPACK2003-35304.

For high-power electronic packages, it is generally accepted that the package-sink interface materials used in the thermal solution influence hot-spot temperature(s) and junction-to-ambient thermal resistance. In this article we show how these package-exterior materials can noticeably influence across-die temperature gradients also. The numerical results reveal that the across-die thermal gradient can nearly double over a narrow range of conductivities typical of commercially available package-sink interface materials. Results show that the chip hot-spot temperature can be reduced 4 to 7 C by increasing the thermal interface material conductivity from 1 to 3 W/mk. This improvement can reduce the total thermal resistance from chip to ambient.

Commentary by Dr. Valentin Fuster
2003;():647-652. doi:10.1115/IPACK2003-35305.

It is well established that the power dissipation for electronic components is increasing. At the same time, high performance portable equipment with volume, weight, and power limitations are gaining widespread acceptance in the marketplace. The combination of the above conditions requires thermal solutions that are high performance and yet small, light, and power efficient. This paper explores the possibility of using thermoelectric (TE) refrigeration as an integrated solution for portable electronic equipment accounting for heat sink and interface material thermal resistances. The current study shows that TE refrigeration can indeed have a benefit over using just a heat sink. Performance maps illustrating where TE refrigeration offers an advantage over an air-cooled heat sink are created for a parametric range of CPU heat flows, heat sink thermal resistances, and TE material properties. During the course of the study, it was found that setting the TE operating current based on minimizing the CPU temperature (Tj ), as opposed to maximizing the amount of heat pumping, significantly reduces Tj . For the baseline case studied, a reduction of 20–30°C was demonstrated over a range of CPU heat dissipation. The parametric studies also illustrate that management of the heat sink thermal resistance appears to be more critical than the CPU/TE interfacial thermal resistance. However, setting the TE current based on a minimum Tj as opposed to maximum heat pumping reduces the system sensitivity to the heat sink thermal resistance.

Commentary by Dr. Valentin Fuster
2003;():653-657. doi:10.1115/IPACK2003-35307.

The effect of solar shield on the maximum temperature of an active plate was investigated. The focus of this analysis was to determine conditions under which it was advantageous to have a solar shield around a heated plate. Heat transfer correlations for free convection around a vertical plate were used with some corrections for channel flow effects. Results obtained from these correlations were validated using CFD simulations. The results presented in this paper include the effects of some key parameters on the maximum temperature of the active plate, including the effects of heat fluxes from the active plate and solar shield, surface emissivity and sky temperature. The results suggest that there is a limit on the ratio of heat flux from the active plate to the solar heat flux beyond which it is not advantageous to have a solar shield. The results also show that the advantage of having a solar shield diminishes as the effective sky temperature decreases. Furthermore, the emissivity is an important factor and its value can determine whether a solar shield is necessary or not.

Topics: Solar energy
Commentary by Dr. Valentin Fuster
2003;():659-664. doi:10.1115/IPACK2003-35309.

Effective cooling of electronic chips is crucial for reliability and performance of electronic devices. Steadily increasing power dissipation in both devices and interconnects motivate the investigation of chip-centric thermal management as opposed to traditional package-centric solutions. In this work, we explore the fundamental limits for heat removal from a model chip for various configurations. Temperature rise when the chip is embedded in an infinite solid is computed for different thermal conductivities of the medium to pin down the best that can be achieved with conduction based thermal management. Next, a chip attached to a spreader plate with convection boundary condition on top was considered. A brief review of interface thermal resistances and partitioning of overall thermal resistance is presented for current generation microprocessors. Based upon the analysis it is concluded that far-term cooling solutions might necessitate integration with chip/interconnect-stack to meet the challenges. In addition, this would require concurrent thermal and electrical design/fabrication of future high-performance microprocessors.

Commentary by Dr. Valentin Fuster
2003;():665-674. doi:10.1115/IPACK2003-35310.

When comparing two electronic packages identical in all respects except die plan dimensions and power, wherein the package with the smaller die is associated with a lower power, it is often hypothesized that the lower-powered package would have a lower junction-case thermal resistance. This hypothesis is generally based on the questionable argument that because the smaller package has lower power, its internal temperatures should be lower and hence a lower junction-case resistance should be ‘intuitively’ expected. In this article we show that drawing inferences about trends in junction-case resistance based merely on power trends, as outlined above, can be incorrect. In order to address this issue and provide better ‘indicators’ for comparing thermal performance across packages, we introduce the concept of the Power Density Distribution (PDD) and show how it relates with the junction-case thermal resistance. To illustrate its use in comparing thermal performance of packages we consider examples of several ICs with different die size/power combinations. Additionally, we also note the correlation between peaks in the spatial distribution of the power density and those of the die temperature distribution; in effect, this furnishes a simple way to identify candidate hot-spot locations on the die without resorting to extensive numerical thermal simulation/testing. We illustrate this intuitively anticipated concept for a variety of power distribution scenarios in some of our example IC packages.

Commentary by Dr. Valentin Fuster
2003;():675-680. doi:10.1115/IPACK2003-35316.

Pool boiling heat transfer of water and FC-72 on thin blocks, 3 mm, of metal and mesophase graphite foams bonded on a high flux heat source is studied experimentally. Two blocks of 80 ppi (90% porosity) and 30 ppi (95% porosity) copper foams, and a block of graphite foam (75% porosity) were tested. Experimental results on foam structures are compared with those of plain surface. Significant enhancement was achieved in boiling of water on the 30 ppi copper foam, while no enhancement was observed on the 80 ppi copper and the graphite foams. In the case of FC-72 boiling, however, a substantial enhancement was achieved on all foams. Results of the experiment and enhancement in different boiling regimes are discussed.

Commentary by Dr. Valentin Fuster
2003;():681-686. doi:10.1115/IPACK2003-35320.

An advanced heat sinking technology is described in which heat is dissipated by flowing the liquid coolant through a matrix of well-bonded metallic particles. This porous metal heat sink has the capability to dissipate heat flux of 500W/cm2 or more with a unit area thermal resistance of 0.1°C·cm2 /W. The construction of one incarnation of this class of heat sink developed for cooling of a high-power stack of laser diode arrays is described. Tradeoffs between pressure drop and thermal resistance are identified with regard to particle size and other geometric parameters. The patented manifolding geometry allows the cooling area to be scaled up without significantly increasing the overall pressure drop. Experimental data showing thermal resistance and pressure drop at a variety of different water flow rates is also presented. Applications for this technology can include cooling of laser diode arrays and high power electronic components such as CPUs.

Commentary by Dr. Valentin Fuster
2003;():687-694. doi:10.1115/IPACK2003-35324.

Thermal Interface Materials (TIMs) are used as thermally conducting media to carry away the heat dissipated by an energy source (e.g. active circuitry on a silicon die). Thermal properties of these interface materials, specified on vendor datasheets, are obtained under conditions that rarely, if at all, represent real life environment. As such, they do not accurately portray the material thermal performance during a field operation. Furthermore, a thermal engineer has no a priori knowledge of how large, in addition to the bulk thermal resistance, the interface contact resistances are, and, hence, how much each influences the cooling strategy. In view of these issues, there exists a need for these materials/interfaces to be characterized experimentally through a series of controlled tests before starting on a thermal design. In this study we present one such characterization for a candidate thermal interface material used in an electronic cooling application. In a controlled test environment, package junction-to-case, Rjc, resistance measurements were obtained for various bondline thicknesses (BLTs) of an interface material over a range of die sizes. These measurements were then curve-fitted to obtain numerical models for the measured thermal resistance for a given die size. Based on the BLT and the associated thermal resistance, the bulk thermal conductivity of the TIM and the interface contact resistance were determined, using the approach described in the paper. The results of this study permit sensitivity analyses of BLT and its effect on thermal performance for future applications, and provide the ability to extrapolate the results obtained for the given die size to a different die size. The suggested methodology presents a readily adaptable approach for the characterization of TIMs and interface/contact resistances in the industry.

Commentary by Dr. Valentin Fuster
2003;():695-698. doi:10.1115/IPACK2003-35348.

An Optical Network Unit (ONU) used in Fiber-to-the-Curb (FTTC) system is one of the last mile equipment in telecommunications industry. The ONU usually operates in an outdoor environment like many other telecommunications cabinets. The ONU, in this study, is placed inside a CAT12 pedestal. The pedestal provides the housing for the termination block, the cable harness, the gas tube protection, etc. besides the ONU. Due to the proximity to residential areas and the reliability requirement for the operation, most of ONUs uses the passive cooling instead of the active cooling. It is very critical to ensure that all electronics including the optics operate within their thermal specifications. From the thermal perspective, most of the outdoor equipment for telecommunications industry follows the guidelines of GR-487-CORE, Issue 2. The CFD model analysis as well as engineering mockup tests provide the effective tools to meet the thermal requirements in this study. With the baseline model working, it is found that it would be very efficient to predict the thermal trends in different design conditions performing CFD simulations using readily available analysis tool Icepak.

Topics: Simulation , Networks
Commentary by Dr. Valentin Fuster
2003;():699-704. doi:10.1115/IPACK2003-35354.

Prediction of pressure drop for duct flow through heat sinks involves calculation of inlet and exit losses. These predictions are typically done using Kc and Ke for “parallel plate channels” from the Kays and London book, Compact Heat Exchangers. However, these equations assume fully developed flow at the exit and thus include the effect of full velocity profile development. Electronic heat sinks operate in the “developing flow” region. So, use of the published Kc and Ke from the Kays and London book will result in over-estimate of the actual Kc and Ke values. The authors have performed analysis that allows accurate calculation of Kc and Ke values with parallel plate channels for operation in the “developing flow” region. The results are presented in graphical form as a function of contraction ratio and x+ (= x/Dh Re). These results will allow accurate estimate of Kc and Ke values for developing flow. Entrance and exit losses can account for as much as 30% of the total pressure drop in electronic heat sinks having short flow lengths. However, the error associated with evaluation of Kc and Ke based on fully developed flow for parallel plates is small.

Commentary by Dr. Valentin Fuster
2003;():705-711. doi:10.1115/IPACK2003-35362.

This paper will discuss air-cooled compact heat exchanger design using published data. Kays & London’s “Compact Heat Exchangers” [1] contains measured heat transfer and pressure drop data on a variety of circular and rectangular passages including circular tubes, tube banks, straight fins, louvered fins, strip or lanced offset fins, wavy fins and pin fins. While “Compact Heat Exchangers” is the benchmark for air cooled heat exchanger test data it makes no attempt to summarize the results or steer the thermal designer to an optimized design based on the different factors or combination of heat transfer, pressure drop, size, weight, or even cost. Using this reduced data and the analytical solutions provided highly efficient compact heat exchangers could be designed. This paper will guide a thermal engineer toward this optimized design without having to run trade studies on every possible heat exchanger design configuration. Typical applications of published fin data in the aerospace and military electronics include electronics cold plates, card rack walls and air-to-air heat exchangers using fan driven and ECS driven air. Airborne electronics often require extremely dense packaging techniques to fit all the required functions into the available volume. While leaving little room for cooling hardware this also drives power densities up to levels (20 W/sq-cm) that require highly efficient heat transfer techniques. Several design issues are discussed including pressure drop, heat transfer, compactness, axial conduction, flow distribution and passage irregularities (bosses). Comparisons between fin performance are made and conclusions are drawn about the applicability of each type of fin to avionics thermal management.

Commentary by Dr. Valentin Fuster

Embedded Passives

2003;():713-718. doi:10.1115/IPACK2003-35090.

Combining thick-film and printed wiring board processes allows thick-film ceramic resistors and capacitors to be embedded in printed wiring boards (PWB). The resistor materials are based on lanthanum boride and cover the range of 10 ohm/square to 10 Kohm/square resistivities. The capacitor material is based on doped barium titanate. Both systems are designed to be “thick-film” printed on copper foil in the locations desired in the circuit and the foil is then fired in nitrogen at 900°C to form the ceramic component on the copper foil. The foil is then laminated, component face down, to FR4 using standard prepreg. The inner layer is then etched to reveal the components in a FR4 matrix. The resistors can be trimmed to tight tolerance at this stage and the components tested. The inner layer can then be laminated into a multilayer PWB. The process is described and the influence of board design, PWB processing and materials are presented and discussed. Examples of circuits using embedded thick-film passives are shown and results of reliability studies are presented.

Commentary by Dr. Valentin Fuster
2003;():719-725. doi:10.1115/IPACK2003-35149.

Embedded capacitor technology is one of the effective packaging technologies for further miniaturization and higher performance of electronic package systems. High dielectric constant epoxy/ceramic composites have been of great interest as embedded capacitor materials, because they have good process compatibility with multilayer organic substrates applications such as printed circuit boards (PCBs). In this work, it was demonstrated that low (less than ±5%) tolerance epoxy/BaTiO3 composite capacitors were successfully fabricated on PCBs using newly developed embedded capacitor films (ECFs), which were composed of specially formulated epoxy resin, latent curing agent, and BaTiO3 powders. And some properties of the capacitors were characterized. Compared with the dielectric layer formation method by spin coating using epoxy/BaTiO3 suspension, ECFs have excellent advantages such as lower (<5%) capacitance tolerance over large area, no waste of materials, good film formation capability, and processability, long shelf life, and good thermo-mechanical stability after final epoxy cure. Dielectric constant about 93 was obtained using two different size BaTiO3 powders mixture. Epoxy resin formulation, curing agent, solvents, and dispersant were optimized to produce good film formation capability, fast curing characteristics at 180°C within 5 minutes, good BaTiO3 powder dispersion control, and excellent shelf life for handling. And the effects of BaTiO3 particle size and BaTiO3 powder content on dielectric constant and adhesion strength were investigated. These capacitor films can be embedded on selective areas of PCBs during build-up processes or other substrates such as Si wafers and ceramic substrates.

Commentary by Dr. Valentin Fuster
2003;():727-733. doi:10.1115/IPACK2003-35221.

This paper describes a design optimization of power distribution networks using embedded passive technology. A frequency-domain methodology was used to study the impedance characteristics of printed circuit board power planes with embedded decoupling capacitors, and also the interaction with discrete capacitors, package structures and on-chip capacitors. Two different thin-core materials were analyzed. Key aspects of power distribution networks including plane spreading inductance, plane pair via inductance and transfer impedance were also analyzed. Utilizing broadband PDN models, extracted with full-wave EM techniques to account for frequency-dependent behaviour, frequency-domain SPICE simulations were carried out to determine the system impedance characteristics at multiple port locations up to 2 GHz. The frequency-domain analysis shows that in bare boards, significant SSN interaction between different port locations within the printed circuit board is present. It is concluded that the proper use of high-K distributed capacitors at optimal locations on the printed circuit board helps to alleviate SSN interaction between different port locations. Several multi-layer test vehicles have been fabricated and characterized, with good correlation between simulation results and measured values.

Commentary by Dr. Valentin Fuster
2003;():735-739. doi:10.1115/IPACK2003-35223.

A solution space design methodology is presented for optimization of off-chip inductors. The analysis has been performed for an advanced wafer level redistribution manufacturing process. Electromagnetic simulations were performed to extract the characteristics of different inductor designs. It was observed that the design optimization should be tuned to the operating frequency.

Commentary by Dr. Valentin Fuster
2003;():741-745. doi:10.1115/IPACK2003-35230.

As CPUs increase in performance, the number of passive components on the surface of the boards are increasing dramatically. To reduce the number of components, as well as improve the electrical performance (i.e. reduce inductance), designers are increasingly embedding capacitive layers in the PCB. The majority of the products in use today utilize reinforced epoxy laminates. These products are relatively easy to handle, but the thickness and Dk limit the effectiveness of the layer to perform as a capacitor. Other materials are being developed that are thinner (and thus increase capacitance), but either have problems with dielectric breakdown strength, handling or only marginal improvement over the existing material. This paper will describe new non-reinforced substrates for use as embedded capacitance layers that address these issues. The material selection process, substrate processing and electrical performance will be reviewed.

Commentary by Dr. Valentin Fuster
2003;():747-755. doi:10.1115/IPACK2003-35244.

This paper is an in depth presentation of a novel approach for design and manufacturing processes to embed ceramic thick film resistors and discrete capacitors into circuit board substrates. These robust materials are available in a wide range of values. Embedded passives, i.e., resistors and capacitors built right into the printed circuit board substrate will be the next pivotal technology for the PCB industry, preceded by the plated thru hole in the 50s, and microvias in the 90s. Key drivers are performance, miniaturization, and cost. The average cell phone has 445 SMT passive components at a 25:1 ratio to ICs. Embedding many of these will improve performance, enable more functionality and reduce cost per function. Embedded passives are not limited to cell phones, many other applications will benefit from improved performance. Several materials are commercially available today and many new materials are in development.

Topics: Ceramics , Thick films
Commentary by Dr. Valentin Fuster
2003;():757-762. doi:10.1115/IPACK2003-35339.

This paper provides an overview of the economic issues and cost models associated with the conversion of discrete passives to embedded passives in printed circuit boards. Three attributes of economic analysis are included herein: fabrication and manufacturing cost analyses, embedded resistor trim and rework economics, and non-manufacturing life cycle costs that are impacted by the conversion of discrete passives to embedded passives. In addition, a complete set of references to existing work on the economics of embedded passives is provided.

Topics: Economics
Commentary by Dr. Valentin Fuster

Airborne, Space and Defense Electronic Systems

2003;():763-766. doi:10.1115/IPACK2003-35056.

Many defense programs have vibration requirements for electronics which are often specified as random vibration input. Often, this input is based on measurements taken at the locations of interest for the spectrum of vehicle operating environments. The resulting specification is typically several power spectral density, or PSD, curves with associated durations. The root mean square acceleration, or Grms , can be readily calculated for each PSD curve. Grms values are sometimes used to compare different PSD curves for severity. However, this can be misleading. The impacts of two different random vibration inputs, with the same Grms value, can be very different. By calculating fatigue damage values for various components on a circuit card assembly subjected to these inputs, it can be shown that equal Grms values do not result in equal damage. In fact, there can be two orders of magnitude difference in component damage values. This means that Grms values are very poor indicators of random vibration effect, and should not be used for comparison purposes.

Commentary by Dr. Valentin Fuster
2003;():767-777. doi:10.1115/IPACK2003-35057.

An important aspect of environmental control is the protection of equipment from the harmful effects of humidity. It is often desirable to desiccate a sealed volume in order that it satisfy a dryness requirement over the duration of its service life. Desiccant sizing, along with proper sealing, become important design elements in ensuring that such a requirement is achieved. To this end, Raytheon has developed a simulation tool to analyze and predict the humidity within sealed volumes. The pertinent physical principles that are modeled are permeation of water vapor by diffusion, pneumatic leakage, the hygroscopic properties of sealed materials, desiccant characteristics, and the kinetic model of ideal gas mixtures. The simulation has the capability of imposing any external environmental condition, consisting of diurnal cycles of temperature and humidity. The physical principles which underlie the simulation are described. An example of simulation results, design decisions and lessons-learned are presented.

Commentary by Dr. Valentin Fuster
2003;():779-782. doi:10.1115/IPACK2003-35235.

Jet Propulsion Laboratory (JPL) has developed, for the first time, a matchbox-size compact grayscale optical correlator (GOC). In this paper, we will report the recent development of a prototype 512 × 512 GOC utilizing a new miniature ferroelectric liquid crystal spatial light modulator (FLCSLM) with a 7-micron pixel pitch. We will discuss recent progress in the design and packaging technology to achieve a rugged portable GOC module to enable the real-time onboard applications of this miniature GOC. Experimental demonstration of ATR applications using this new GOC will be presented.

Commentary by Dr. Valentin Fuster
2003;():783-788. doi:10.1115/IPACK2003-35248.

As with the commercial market, Military/Aerospace electronic packaging has similar needs to develop smaller/lighter/ higher performance electronics. This need has required the use of High Density Interconnect (HDI) circuit boards and Grid Array components (ball and column) in rugged environment applications such as military and space. This discussion will cover the technology study program conducted by Honeywell Defense and Space Electronics Systems on the mechanical durability of HDI (High Density Interconnect) and Grid Array component packaging and its application into “Hi Rel” aerospace programs.

Commentary by Dr. Valentin Fuster
2003;():789-795. doi:10.1115/IPACK2003-35249.

As spacecraft designs converge toward miniaturization, and with the volumetric and mass challenges placed on avionics, programs will continue to advance the “state of the art” in spacecraft system development with new challenges to reduce power, mass and volume. Traditionally, the trend is to focus on high-density component packaging technologies. Industry has made significant progress in these technologies, and other related internal and external interconnection schemes. Although new technologies have improved packaging densities, a system packaging architecture is required that not only reduces spacecraft volume and mass budgets, but increase integration efficiencies, provide modularity and flexibility to accommodate multiple missions while maintaining a low recurring cost. With these challenges in mind, a novel system packaging approach incorporates solutions that provide broader environmental applications, more flexible system interconnectivity, scalability, and simplified assembly test and integration schemes. The Integrated Avionics System (IAS) provides for a low-mass, modular distributed or centralized packaging architecture which combines ridged-flex technologies, high-density COTS hardware and a new 3-D mechanical packaging approach, Horizontal Mounted Cube (HMC). This paper will describe the fundamental elements of the IAS, HMC hardware design, system integration and environmental test results.

Commentary by Dr. Valentin Fuster
2003;():797-800. doi:10.1115/IPACK2003-35347.

Miniaturization of electronic packages will play a key role in future space avionics systems. Smaller avionics packages will reduce payloads while providing greater functionality for information processing and mission instrumentation. Current surface mount technology discrete passive devices not only take up significant space but also add weight. To that end, the use of embedded passive devices, such as capacitors, inductors and resistors will be instrumental in allowing electronics to be made smaller and lighter. Embedded passive devices fabricated on silicon or like substrates using thin film technology, promise great savings in circuit volume, as well as potentially improving electrical performance by decreasing parasitic losses. These devices exhibit a low physical profile and allow the circuit footprint to be reduced by stacking passive elements within a substrate. Thin film technologies used to deposit embedded passive devices are improving and costs associated with the process are decreasing. There are still many challenges with regard to this approach that must be overcome. In order to become a viable approach these devices need to work in conjunction with other active devices such as bumped die (flip chip) that share the same substrate area. This dictates that the embedded passive devices are resistant to the subsequent assembly processes associated with die attach (temperature, pressure). Bare die will need to be mounted directly on top of one or more layers of embedded passive devices. Currently there is not an abundant amount of information available on the reliability of these devices when subjected to the high temperatures of die attach or environmental thermal cycling for space environments. Device performance must be consistent over time and temperature with minimal parasitic loss. Pretested and assembled silicon substrates with layers of embedded capacitors made with two different dielectric materials, Ta2 O5 (Tantalum Oxide) and benzocyclobutene (BCB), were subjected to the die attach process and tested for performance in an ambient environment. These assemblies were subjected to environmental thermal cycling from −55°C to 100°C. Preliminary results indicate embedded passive capacitors and resistors can fulfill the performance and reliability requirements of space flight on future missions. Testing results are encouraging for continued development of integrating embedded passive devices to replace conventional electronic packaging methods.

Commentary by Dr. Valentin Fuster
2003;():801-808. doi:10.1115/IPACK2003-35351.

Commercial-off-the-shelf (COTS) plastic encapsulated microcircuits (PEM) are candidate-packaging technologies for spacecraft due to their enhanced performance, lower weight and lower cost. Much of the electronics used in space applications would be considered obsolete by everyday standards. This is primarily due the cost and time required for full space qualification. In order to gain the performance available in today’s electronics, COTS PEMs offer a viable path. PEMs can weigh half as much as their counter part ceramic packages. A lighter package results in a smaller overall payload for the same board functionality, a concern of critical importance for space missions because the payload mass dictates the launch vehicle requirements. Costs can be potentially reduced by using screening, accelerated testing or partial qualification techniques to complement the existing commercial qualification as well as by the reduced package materials costs. Assessing the risk associated with potentially lower reliability devices, engineers within the commercial and aerospace industries are using trade-off and risk analysis to aid in reducing spacecraft system cost while increasing performance and maintaining high reliability. In this paper we will outline the issues facing the use of COTS PEMs for spaceflight hardware from the aspect of both the electronic active devices as well as their packages. Finally, we will provide some guidelines for their use.

Commentary by Dr. Valentin Fuster

Packaging Technology

2003;():809-812. doi:10.1115/IPACK2003-35001.

Laser Welding Induced Alignment Distortion (WIAD) during pigtailing of pump lasers has been numerically modeled and studied experimentally. The results demonstrate that the WIAD can be minimized by properly controlling the laser beam energy delivery. A 3D finite element model has been developed for effectively predicting the WIAD.

Commentary by Dr. Valentin Fuster
2003;():813-818. doi:10.1115/IPACK2003-35052.

In order to enhance the wafer level package (WLP, Figure 1) reliability for larger chip size, many different kinds of WLP have been adopted, all have a compliant layer under the pads have to relieve the thermal stress of the solder joint. Usually, the solder joint reliability is enhanced with the increase of the thickness of the compliant layer. However, the fabrication processes of the WLP restrict the thickness of the compliant layer. With that in mind this research proposed a novel WLP package with bubble-like buffer layer (Figure 2) which is composed of a bubble-like plate and a buffer layer between the chip and the solder joint. The main goal of this research was to study the effects of the geometric dimensions and material properties of the bubble-like layer on the reliability of the WLP. For the parametric analysis purpose, a 2-D nonlinear finite element analysis for the proposed WLP was conducted. The results revealed that both the bubble-like plate and the buffer layer provide excellent compliant effects. However, the buffer layer has a more significant effect on enhancing the solder joint reliability. Also, for a WLP with buffer structure, the effect of the chip thickness on the reliability could be significantly reduced. In addition, the difference between the filled and non-filled buffer layers also affected the reliability of the solder joint. The results revealed that the WLP with the buffer layer and the no-fill bubble-like plate had the better reliability.

Commentary by Dr. Valentin Fuster
2003;():819-826. doi:10.1115/IPACK2003-35066.

We have developed a high-density packaging technology by using a thin IC and a thin substrate and bonding it by new flip chip technology. Numerical analysis with the finite element method (FEM) as well experiments clearly showed that deflection of the IC and reliability were affected by the IC thickness. Consequently, reliability could be improved by reducing IC thickness. The dependency of the life in single-sided CSP and both-sided CSP on the thickness of IC and substrate could be expressed using a normal stress in the thickness direction and shear stress in the vertical cross section, respectively. Moreover, a both-sided flip chip approach solved the problem of warpage. A high-capacity memory card of 512 MB was put to practical use by applying these results. This increased the Si density by four times over that of a conventional chip-size package (CSP).

Commentary by Dr. Valentin Fuster
2003;():827-831. doi:10.1115/IPACK2003-35134.

Low Temperature Co-fired Ceramic (LTCC) materials are widely used in ceramic packaging and interconnect applications, such as RF receiving modules for next generation handsets and T/R modules for satellite communications. The application frequency spans from low GHz to 100+ GHz. A variety of techniques must be used to characterize dielectric properties (loss tangent and dielectric constant) of LTCC in the wide frequency range. These techniques include the parallel plate capacitor method from DC to several MHz, cavity methods in x-band, and open resonator techniques for frequencies up to 100+ GHz. LTCC is a multi-layer ceramic technology, which offers capability for low cost manufacturing, realizing 3D structures, and embedding passive components. Both strip line and microstrip types of transmission line structures can be conveniently manufactured using LTCC material systems. As an important performance parameter, microstrip loss can be characterized using the ring resonator technique. Both LTCC and metal conductors contribute to the microstrip loss. At microwave and mm-wave frequencies, metal losses become significant, although low resistance silver conductor can be used. The metal loss may be divided into two categories: one is the resistive loss and other is surface roughness loss. A photo imaging technique has been introduced which patterns the microstrip, reducing the surface loss. In this paper, the techniques for measuring both dielectric properties of A6 LTCC and microstrip properties of A6 LTCC with conductor systems will be reviewed. Characterization results of the dielectric constant and loss tangent of A6 from near DC to 100 GHz will be presented. Microstrip losses, measured for A6 LTCC with both gold and silver metallization up to 40 GHz, are compared to those computed using the closed form equations and experimentally determined dielectric and conductor properties. The calculated effective microstrip permitivity and attenuation compare well to those from measurements.

Commentary by Dr. Valentin Fuster
2003;():839-843. doi:10.1115/IPACK2003-35153.

In recent years, the most explosive technologies in electronic systems have demanded ever-higher functionality, ever-faster circuit speeds, and always increasing interconnection density. Electrolytic and electroless nickel/gold (Ni/Au) deposition process are used commonly to provide flat, solderable pad surface finish on area array (BGA or CSP) packages and printed wiring boards (PWB). The electroless nickel/immersion gold (ENIG) process is widely used which do not requires plating lines for electrolytic plating, better meets the fine pitch wiring requirements. However, ENIG deposition process may cause or contribute to catastrophic, brittle, interfacial solder joint fractures. ENIG plating has previously shown lower reliability at solder joints. This is because Phosphorous segregation at the interface Sn-Ni intermetallic and Ni layer caused poor adhesion at that interface, especially high phosphorous content (10∼15%) of the electroless Ni. There have been many studies verified that Ni3 P formation is a major factor, which causes weaker joint strength and flat fracture surface. Owing to sodium hypophosphite (NaH2 PO2 ) was used to provide electron and return Ni ion to deposit on Cu pad for ENIG plating, it is not dodge that phosphorous element exist at the Ni layer. Hence, ph value, temperature and loading factor (plating area/ plating tank volume) in the plating path are controlled to reduce phosphorous content (less than 10%) to avoid Ni3 P formation. Furthermore, ENIG has a potential risk of black pad, because Porous Au plating layer caused the oxidation of Ni layer underneath the Au plating to occur solder joint failure and low shear forces after assembly. In order to overcome foregoing problem, a flip chip ball grid array (FCBGA) test vehicle is used to compare three kinds surface finish electroless Ni/Au, direct gold and solder on Cu pad in this study 63Sn/37Pb solder bump is reflowed onto these substrates. High temperature storage test (HTS) is used to evaluate thickness and structure of IMC to affect solder joint attachment reliability. Ball shear test is used to measurement joint strength at various HTS time. Optical microscopy (OM) and scanning electron mcroscopy (SEM) are used to observe failure modes after ball shear.

Topics: Finishes
Commentary by Dr. Valentin Fuster
2003;():845-852. doi:10.1115/IPACK2003-35162.

Since electric products need more effective features in terms of being compact, small, thin and highly performant, a new concept to create the advanced JISSO is required. We have invented the film module manufacturing process, in which the semiconductor is embedded into the thermo-elastic film and wired directly to exposed bumps. In this device, the fundamental process which is the embedded semiconductor into the thermoplastic film PETG, has been developed. This process is essential for the embedded active components film. This technique can be applied to packaging, memory cards, smart cards, flexible multi layer film and so on. The embedding process has the following problems; 1) Stud bumps on the IC may not appear on the surface of the film, 2) Voids may appear in the film during a high temperature press, 3) ICs may crack under high pressure. Subsequently, we solved the thermoplastic film’s flow process during the heat compression process using the rigid-plastic FEM (Finite Element method) analysis. We solved the resin temperature and load during the heat pressing process. It was discovered that ICs (0.18mm) could embed into the PETG film (0.2mm) within 13s. Finally, we applied this embedding process with the contactless IC card, which achieved a distance of calls of 100mm.

Commentary by Dr. Valentin Fuster
2003;():853-858. doi:10.1115/IPACK2003-35194.

A new process for making high-density memory stacks which are completely compatible with typical electronic assembly techniques is presented. The process uses PECVD-SiO2 passivation, laser direct-writing, electrodeposited photoresist, and metal electroplating to form a reroute pattern extending from the input/output (I/O) pads on top of the chip directly onto the chip sidewalls. With the I/O available for interconnection on the side of the chip, four memory chips are stacked together with one silicon reroute chip. A high-temperature compatible anisotropically conductive adhesive is used to connect a flex circuit to the sidewall I/O pads of the memory chips and the reroute die. The reroute die’s sidewall pads connect to a pattern on the die surface which redistributes the I/O for connection to a leadframe. The lead frame is epoxied to the reroute die, and wirebonded to complete the electrical connection. The leadframe/stack assembly is then encapsulated with an epoxy potting compound, and the leads are formed and trimmed, creating a chip stack which is indistinguishable from a standard IC package.

Commentary by Dr. Valentin Fuster
2003;():859-866. doi:10.1115/IPACK2003-35263.

Hermetic housings are required for the vast majority of electronics used in RF microwave electronics to protect the gallium arsenide and silicon devices from the environment. A common housing style includes a metal ring frame that is brazed onto a metal or ceramic base. The housing is populated with electronic devices and circuits and then hermetically sealed with a thin metal lid. For high volume manufacturing, lids are often attached by a resistance weld using a seam seal process. The interior hermitic volume is sealed at or near one atmosphere internal pressure. Since the housing may be subjected to a substantial number of pressure cycles that can yield the lid material, a low cycle fatigue evaluation is required to establish the long-term reliability of the hermetic housing. Kovar is a common lid and housing material because of a good coefficient of thermal expansion match with glass, ceramic and other materials used in RF circuitry. Unfortunately only high cycle fatigue data is available for kovar. A method is proposed to generate an estimate of high cycle end of the low cycle fatigue response from the high cycle fatigue data. The proposed method is verified by comparing a predicted fatigue life with experimental results from hermetic housings subjected to pressure cycling.

Commentary by Dr. Valentin Fuster
2003;():867-873. doi:10.1115/IPACK2003-35279.

A detail model of 54 lead Thin Small Outline Package (TSOP) was created in Flotherm and validated against experimental data for natural convection and forced convection environments. Next, a compact two-resistor (2R) model was created in Flotherm using compact smart parts. Values of junction-to-case and junction-to-board resistances were taken from experiments. Both the detailed model and the compact model were mounted on a 4-layered standard JEDEC board for natural convection in a standard JEDEC enclosure. With a nominal power of 0.75W applied at the junction, the detailed model and the 2R compact model showed a very good agreement. The results also compared well with experimental data. Next, two models were developed; a detailed model and a corresponding equivalent 2R compact model were mounted on a 4-layered standard JEDEC board and simulated for forced convection with an air velocity of 1 m/s. With a nominal power of 0.75 W applied at the junction, maximum junction temperatures were computed and once again showed very good agreement. Experimental data for forced convection indicated that the maximum junction temperature was in good agreement to the compact model. The study was further extended to do a board level analysis where the detailed TSOP models were mounted on a 6-layered standard DIMM board. In the single sided board arrangement nine such compact models were mounted on one side of the board and maximum junction temperature was noted. Then, the detailed models were replaced by compact models and simulated for forced convection with an air velocity of 1 m/s. Good agreement between detailed model and compact model was seen for the board level analysis. Further the compact models were simulated for a double-sided arrangement in which eighteen such compact models were mounted nine on each sided of the board. The assembly was simulated for forced convection with an air velocity of 1 m/s. Nominal power applied at junction for each of the eighteen modules was 0.3 W. Maximum temperature for the double sided arrangement of DIMM board was thus computed.

Commentary by Dr. Valentin Fuster
2003;():875-886. doi:10.1115/IPACK2003-35342.

Microsystem packages continue to demand lower cost, higher reliability, better performance and smaller size. Compliant wafer-level interconnects show great potential for next-generation packaging. G-Helix, an electroplated compliant wafer-level chip-to-substrate interconnect can facilitate wafer-level probing as well as wafer-level packaging without the need for an underfill. The fabrication of the G-Helix interconnect is similar to conventional IC fabrication process and is based on electroplating and photolithography. G-Helix interconnect has good mechanical compliance in the three orthogonal directions and can accommodate the differential displacement induced by the coefficient of thermal expansion (CTE) mismatch between the silicon die and the organic substrate. In this paper, we report the wafer-level fabrication of an area-arrayed G-Helix interconnects. The geometry effect on the mechanical compliance and electrical parasitics of G-Helix interconnects have been studied. Thinner and narrower arcuate beams with larger radius and taller post are found to have better mechanical compliance. However, it is also found that structures with excellent mechanical compliance may not have good electrical performance. Therefore, a trade off is needed. Using response surface methodology (RSM), an optimization has been done, and the optimal compliant G-Helix interconnect will have a total standoff height of 64 μm, radius of 36 μm and cross-section area of 93 μm2 .

Commentary by Dr. Valentin Fuster

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