Electronic and Photonic Packaging

2006;():3-7. doi:10.1115/IMECE2006-13104.

The package design for microfluidic sensors is discussed. The MicroElectroMechanical Systems (MEMS) device covered in this paper requires a fluidic and electrical interface as well as vacuum packaging of the sensing element. By using a by-pass package design the limitations of low flow rate and high pressure drop often encountered with microfluidic products can be avoided. The MEMS device utilizes a resonating silicon microtube that is electrostatically driven and capacitively sensed. A platinum RTD is also integrated into the MEMS chip. To improve the Q of the resonator a thin-film getter has been integrated to lower the microcavity pressure. The microfluidic packaging technology lends itself to producing densitometers, chemical concentration meters and Coriolis mass flow sensors. The device has been applied to fuel cell concentration sensors for embedded Direct Methanol Fuel Cell (DMFC) systems. The DMFC systems require a methanol sensor to minimize crossover and hence optimize the water/methanol concentration over temperature and the life of the product. Other high flow rate applications include ethanol/gasoline concentration sensors for E85 vehicles and dialysis fluid monitoring. A microfluidic Coriolis mass flow sensor has been developed and applied to drug delivery to monitor the drug dose, total volume infused, drug type and concentration. Chemical and temperature compatibility of the MEMS chip and packaging materials must be considered when dealing with this wide range of applications and will be discussed in the paper.

Commentary by Dr. Valentin Fuster
2006;():9-18. doi:10.1115/IMECE2006-13592.

A piezoresistive transducer (PRT) pressure sensor would be able to sense a magnetic field and provide an adequate Hall effect output. In this study, two different types of boron-doped transducers, X-ducer and picture-frame transducer (also called micro Wheatstone-bridge transducer) were tested for the Hall effect. It is found that the currently used fabrication process and packaging for PRT pressure sensors do not need to be altered for Hall sensors. However, a slight mask modification is necessary to use an X-ducer instead of a picture-frame transducer for the Hall effect sensing because the X-ducer is at least 50 times more sensitive than the picture-frame transducer. The sensitivity calculated using the Hall theory and estimated hole mobility velocity is in reasonably good agreement with experimental results.

Commentary by Dr. Valentin Fuster
2006;():19-27. doi:10.1115/IMECE2006-14208.

The silicon-based pressure sensor is one of the major applications in the MEMS device. Nowadays, the silicon piezoresistive pressure sensor is a mature technology in industry and its measurement accuracy is more rigorous in many advanced applications. In order to operate the piezoresistive pressure sensor in harsh environment, the silicone get is usually used to protect the die surface and wire bond while allowing the pressure signal to be transmitted to the silicon diaphragm. The major factor affecting the high performance applications of the piezoresistive pressure sensor is the temperature dependence of its pressure characteristics. Therefore, the thermal and packaging effects caused by the silicone gel behaviors should be taken into consideration to obtain better sensor accuracy and sensitivity. For this reason, a finite element method (FEM) is adopted for the sensor performance evaluation, and the thermal and pressure loading is applied on the sensor to study the output signal sensitivity as well as the packaging-induced signal variation, thermal/packaging effect reduction, and output signal prediction for the pressure sensors. The design parameters include silicon die size, silicone gel geometry and its material properties. The simulation results show that the smaller die size and the thicker die thickness can reduce the packaging-induced thermal effect. Furthermore, the different geometry of silicone gel also influences the sensitivity of pressure sensor.

Commentary by Dr. Valentin Fuster
2006;():29-34. doi:10.1115/IMECE2006-14540.

We report the first use of a bimetallic buckling disk as a thermal conduction switch. The disk is used to passively alter the thermal resistance of the package of a chip scale atomic clock. A vertical-cavity surface-emitting laser (VCSEL) and a cesium vapor cell, contained in the clock, must be maintained at 70±0.1°C even under an ambient temperature variation of -40°C to 50°C. A thermal test vehicle has been developed to characterize a sample package with a thermal conduction switch and has been modeled using Finite Element Analysis (FEA). Three cases are presented for the temperature control of the test vehicle under different load placements and environmental conditions: 1) the center resistor in a vacuum package; 2) the center resistor packaged in air; and 3) the side resistor in a vacuum package. At 38°C, the switch snaps upward to reduce the thermal resistance. As a result, the heating power needed to maintain the same temperature is increased from 118 to 200 mW for Case 1. Such a significant change of the thermal resistance demonstrates the effectiveness of the novel thermal switch. However, the switch becomes less effective with air filling the gap, as in Case 2. More interestingly, the switch is not effective at all if the side resistor's temperature is to be controlled as in Case 3.

Commentary by Dr. Valentin Fuster
2006;():35-42. doi:10.1115/IMECE2006-15517.

Development of effective packages for microelectronics, MEMS, as well as for other microsystems and advanced modern devices, is usually based on minimization of thermomechanical effects and maximization of the useful life of a package. Such extremization-analysis depends on the effects that coefficients of thermal expansion (CTEs) have on the design of packages. This paper examines thermomechanics of a package and evaluates the effects that matching (or not) of CTEs may have on a package and its life. This examination is illustrated with representative examples.

Commentary by Dr. Valentin Fuster
2006;():43-52. doi:10.1115/IMECE2006-16062.

The viscoelastic material properties of SU-8 and carbon nanotube-reinforced SU-8 composite material are characterized by tensile testing. Dogbone samples of 0.1mm thickness are prepared by micro-fabrication process, which is composed of spin coat, soft bake, expose, and post exposure bake. To fabricate CNT polymer composite, carbon nano-tube of 0.2wt% is mixed with SU-8. To observe the effect of applied strain rate and temperature on Young's modulus and Poisson's ratio, strain rate is varied from 5×10-5 to 2.5×10-4 (/sec) at elevated temperatures in the range of 25 to 200°C. Since the viscoelastic material properties are important in polymer, creep, stress relaxation and dynamic mechanical analyses are performed at elevated temperatures. The viscoelastic material properties of SU-8 and CNT-reinforced SU-8 composite are compared, and the mechanical reliability of these polymers in MEMS applications is discussed.

Commentary by Dr. Valentin Fuster
2006;():53-57. doi:10.1115/IMECE2006-13119.

The study of thermomigration on Sn-Ag-Cu solder sphere subjected to a high thermal gradient of 1100°C/cm is presented. After 286 hours, the hot end showed a thin and flat intermetallic compound (IMC) while the cold side showed a scallop-like Cu6 Sn5 IMC. Small voids can be seen within the Cu6 Sn5 IMC after 712 hours on the cold side, while the IMC on the opposite side showed no observable changes.

Commentary by Dr. Valentin Fuster
2006;():59-65. doi:10.1115/IMECE2006-13376.

Lead-free (Pb-free) solder has seen increasing use in interconnect systems for electronic packages due to legislative and marketing pressures. The NEMI selected eutectic Sn3.9Ag0.6Cu alloy (or a close variation near eutectic Sn3.5Ag1.0Cu used in this study) is a leading Pb-free substitute for the Sn/Pb solder candidate. The reliability of this Pb-free solder alloy under accelerated thermal cycling and thermal shock testing as a function of testing parameters such as dwell time and ramp rate is critical in qualifying the performance of these Pb-free alternatives with the traditionally used Sn37Pb solder This paper presents the reliability of Pb-free solder joints in wafer level chip scale packages (WLCSPs), which are extensions of flip-chip packaging technology to standard surface mount technology, with external dimensions equal to that of the silicon device [1]. The reliability of these packages under both liquid-to-liquid thermal shock (LLTS) testing and accelerated air-to-air thermal cycling (AATC) conditions, as a function of dwell times and ramp rates is evaluated using extensive experimental testing in combination with finite element analysis. Besides, two asymmetric cycles in which the cold and hot dwell times differ at two temperature extremes were studied. Along with the Pb-free solder, some test vehicles were built using eutectic Sn-Pb solder and evaluated for comparison purposes. Experimental results show that an increase in ramp rate does not adversely affect the solder joint reliability in the case of Pb-free solder. The reliability of lead-free WLCSPs was highly dependent upon the dwell time at the temperature extremes, with this dependency being considerably greater for the lead-free allow than for Sn/Pb at 0°C and 100°C. Accelerated test results show that increasing the dwell time from 280 to 900 seconds reduced the N63.2 of the Sn/Pb samples by 12% and the Pb-free samples by 65%. Reliability during asymmetric cycles resulted in a trend that is similar in two cases studied. A predictive equation was developed to evaluate the characteristic life of the package with respect to the dwell time. Non-linear, finite element (FE) modeling was conducted using temperature dependent creep constitutive relations for the Pb-free solder to understand the experimental trends observed. The FE results predicted the same trend of the package reliability as observed experimentally, with respect to the changing dwell and ramp times. The finite element predictions demonstrated reasonable correlation with the experimental observations.

Commentary by Dr. Valentin Fuster
2006;():67-72. doi:10.1115/IMECE2006-13420.

Flip chip packaging is one of the fastest growing segments in electronics packaging technology. The semiconductor packaging industry is continuing to migrate towards Pb-free electronics assembly. Therefore, the development of compatible materials for Pb-free flip chip packaging is critical to this transition [1]. Flip chip devices are commonly underfilled to compensate for the mismatch in the Coefficient of Thermal Expansion (CTE) between the die and the chip carrier. The No Flow Underfill (NFU) process is a type that can increase the throughput of the flip chip assembly process and reduce manufacturing costs. Significant research has been performed to develop NFUs for eutectic applications. However, further research is required for the development of NFUs that are compatible with the Pb-free solders and the high temperature reflow process associated with these solders. In this paper, the challenges associated with the development of 'filled' underfill formulations for assembly with the 95.5Sn/3.8Ag/0.7Cu bumped flip chip devices are discussed. The effects of process variables that affect voiding in the underfill layer have been presented. The impact on voiding due to stencil printing of the underfill has been discussed. The impact on assembly reliability due to the underfill material properties has also been reported.

Commentary by Dr. Valentin Fuster
2006;():73-80. doi:10.1115/IMECE2006-13555.

In this paper, the vibration durability of SnAgCu (SAC) solders is compared to that of SnPb solder, using selected surface mount technology (SMT) interconnects. A time-domain approach, reported in the literature [1], was adopted for this study. Vibration durability tests under random excitation (between 10 Hz & 500 Hz) were conducted for both SAC and SnPb SMT boards. The test assembly consists of daisy-chained components, to facilitate real-time failure monitoring. Step-stress tests were conducted by increasing the RMS excitation levels from 7G to 14G in out of plane direction. The test was continued until most of the components on the board failed. In general, the SAC solders were found to have lower fatigue durability than the SnPb solder, under the vibration excitation levels applied in this study. This result is consistent with results in the literature from mechanical cycling studies, repetitive mechanical shock studies [2] and vibration studies [3] [4]. Destructive failure analysis (cross-sectioning, polishing and microscopy) was used to confirm that the failure was by solder fatigue. Durability model constants were estimated for a generalized Coffin-Manson strain-life fatigue model [5], for both SnPb and SAC solders

Commentary by Dr. Valentin Fuster
2006;():81-89. doi:10.1115/IMECE2006-13556.

The electronics manufacturing industry is gradually migrating towards to a lead-free environment. During this transition, there will be a period where lead-free materials will need to coexist with those containing lead on the same assembly. The use of tin-lead solder with lead-free parts and lead-free solder with components containing lead can hardly be avoided. If it can be shown that lead-free Ball Grid Arrays (BGAs) can be successfully assembled with tin-lead solder while concurrently obtaining more than adequate solder joint reliability, then the Original Equipment Manufacturers (OEMs) will accept lead-free components regardless of the attachment process or material used. Consequently, the Electronics Manufacturing Service (EMS) providers need not carry both the leaded and the unleaded version of a component. Solder voids are the holes and recesses that occur in the joints. Some say the presence of voids is expected to affect the mechanical properties of a joint and reduce strength, ductility, creep, and fatigue life. Some believe that it may slow down crack propagation by forcing a re-initiation of the crack. Consequently, it has the ability to stop a crack. The primary objective of this research effort is to develop a robust process for mixed alloy assemblies such that the occurrence of voids is minimized. Since there is no recipe currently available for mixed alloy assemblies, this research will study and 'optimize' each assembly process step. The difference between the melting points of lead-free (217°C) and tin-lead (183°C) solder alloys is the most important constraint in a mixed alloy assembly. The effect of voids on solder joint reliability in tin-lead assembly is well documented. However, its effect on lead-free and mixed alloy assemblies has not received due attention. The secondary objective of this endeavor is to determine the percentage of voids observed in mixed alloy assemblies and compare the results to both tin-lead and lead-free assemblies. The effect of surface finish, solder volume, reflow profile parameters, and component pitch on the formation of voids is studied across different assemblies. A designed experiments approach is followed to develop a robust process window for mixed alloy assemblies. Reliability studies are also conducted to understand the effect of voids on solder joint failures when subjected to accelerated testing conditions.

Topics: Alloys
Commentary by Dr. Valentin Fuster
2006;():91-99. doi:10.1115/IMECE2006-13745.

In this paper is reported the mechanical and thermomechanical aspect of SnAgCu solder alloys that have been tested for their deformation behavior. Commercially available Sn3.8Ag0.7Cu was considered as base alloy. The constant stress and strain-rate tests were performed in tensile and shear configuration. Mechanical deformations were measured using bulk solder tensile specimens and grooved lap shear specimens which enabled a stress-state of nearly pure shear in the solder joint. The strain rate range was between 0.1/sec and 10-6 /sec, and test temperatures were 25°C, 75°C and 125°C. Both as-prepared and thermally aged samples were tested. The aging condition was 24hrs at 125°C. The measured tensile stress-strain data were utilized to determine the constants for the visco-plastic Anand's constitutive model. Thermo-mechanical properties like coefficient of thermal expansion (CTE) for those SnAgCu lead free alloys were measured in the temperature range of - 40 to 160°C using thermo-mechanical analyzer (TMA). The tensile and shear properties of 95.5Sn3.8Ag0.7Cu solder and solder joint specimens are highly dependent on test temperature and strain rate. The mechanical strength of SAC bulk solder and solder joint decreases with increase in temperature and increases with increase in strain rate. CTE for the SAC lead-free alloys were relatively lower compared with tin-lead solder. The steady-state creep test data for 95.53.8Ag0.7Cu solder was curve-fitted to a hyperbolic-sine creep model. The material constitutive parameters developed are in line with similar studies.

Topics: Deformation , Alloys , Solders
Commentary by Dr. Valentin Fuster
2006;():101-108. doi:10.1115/IMECE2006-13927.

The transition to lead-free assembly will have a significant effect on wave soldering operations. Since the wetting ability of lead-free solder is usually less than that of tin-lead solder, it can result in unacceptable hole fills and inconsistent top side wetting - especially in the case of thick Printed Circuit Boards (PCBs). Presently, there is very little data available on lead-free wave soldering with tin-silver-copper (SnAgCu or SAC) alloy and no-clean flux chemistry. Although some researchers and consortia recommend tin-copper (SnCu) for lead-free wave soldering, demonstrating the feasibility of using the SAC alloy for wave soldering operation can aid manufacturers to use the same alloy for both reflow and wave soldering operations. In this study, SAC 305 alloy and no-clean flux were evaluated in terms of percentage of hole fill and solderability on a 93 mil thick test vehicle with Immersion Silver (ImmAg) surface finish. The evaluation was performed on a nitrogen equipped wave soldering equipment. It has 4 preheating zones (3 convection bottom heaters and 1 infrared top heater) that provides good control to develop the required preheat profile. A partial factorial experiment was conducted to study the main effects of solder pot temperature, topside preheat temperature and conveyor speed on wave soldering performance. Wave soldering was performed after two reflow cycles. A 100% visual inspection was done for all the through hole components using a 10X microscope to determine top side wetting, percentage of hole fill, bridging, flux residue and solder balling. Thickness of the hole fill was also measured using digital X-Ray equipment. The data generated from this experiment was used to determine the 'optimum' lead-free process parameters for wave soldering using a SAC 305 alloy with a no-clean flux chemistry. The 'optimized' process parameters were then used to evaluate boards with Organic Solderability Protective (OSP) and Electroless Nickel Immersion Gold (ENIG) surface finishes. The designed experiments approach adopted to determine the optimum process settings and the research findings are explained in detail.

Topics: Wave soldering
Commentary by Dr. Valentin Fuster
2006;():109-116. doi:10.1115/IMECE2006-13963.

This paper presents a systematic approach to study the effect of manufacturing variables on the creation of defects and the effect of those defects on the durability of lead free solder joints. An experiment was designed to systematically vary the reflow and printing process variables in order to fabricate error-seeded test assemblies. The error-seeded samples were then inspected visually and with x-rays, to identify different types of defects, and tested for electrical performance. The specimens were put under accelerated thermal cycling test to characterize the durability of specimens and to study the effect of each manufacturing variable on the durability of solder joints. Thus, the response variable for the design of experiments is the thermal cycling durability of the solder joints. Pre-test micro-structural analysis shows that specimens produced under inadequate reflow profiles suffer from insufficient wetting and insufficient intermetallic formation. Statistical analysis of the response variable shows that waiting time, heating ramp, peak temperature and cooling rate have non-linear effects on the response variable. Two variables, in particular (the heating ramp time and the waiting time), appear to have optimum values within the ranges investigated.

Commentary by Dr. Valentin Fuster
2006;():117-123. doi:10.1115/IMECE2006-14221.

Tin whisker outbreaks can pose problems on FFC/FPC (flat flex cable/flexible printed circuit) connectors in electronics components. Several mechanical loading tests for investigating whisker formation have been performed, however, the mechanical implications of the results remain unclear. The purpose of this study was to clarify whether the whisker formation mechanism on connectors is due to contact force. Using the creep properties collected from nanoindentaion tests, the stress evolution in plating is extracted. The behavior of the stress evolution was investigated by finite element analysis. During the test, the axial compressive stresses increase, although stress relaxation also occurs. The effect of substrate shape is also investigated and whiskering behavior due to stress was confirmed.

Topics: Force , Plating
Commentary by Dr. Valentin Fuster
2006;():125-131. doi:10.1115/IMECE2006-14658.

Soldering has become an indispensable joining process in the electronic packaging industry. The industry is aiming for the use of environment friendly lead-free solders. All the lead-free solders are high tin-containing alloys. During the soldering process, an intense interaction of metallization on PCB and tin from the solder occurs at the metallization/solder interface. Intermetallic compound (IMC) is formed at the interface and subsequently PCB bond-metal (substrate) is dissolved into the molten solder. In the present study the terms bond-metal and substrate will be used interchangeably and the term 'substrate' refers to the top layer of the PCB which comes in contact with the molten solder during soldering reaction. Thickness of the intermetallic phase formed at the joint interface and amount of substrate lost is critical in achieving reliable solder joints. During the wet phase of soldering process, the IMC does not grow as layered structure; rather it takes the shape of scallops. The growth of scalloped IMC during the solder/substrate interaction entails complicated physics. Understanding of the actual kinetics involved in the formation of IMC phase is important in controlling the process to achieve desired results. This paper presents theoretical analysis of the kinetics involved in the formation of the scalloped intermetallic phase. The intermetallic phase growth is experimentally investigated to support the underlying kinetics of the process. Numerical model has been suggested to translate the physics of the process. The model is based on the basic mass diffusion equations and can predict the substrate dissolution and IMC thickness as a function of soldering time.

Topics: Metals , Soldering , Modeling
Commentary by Dr. Valentin Fuster
2006;():133-137. doi:10.1115/IMECE2006-15485.

In order to take advantage of the global economy, manufacturing companies have developed a complex and an extended supply chain which includes manufacturing components or parts in LCCs (low-cost countries) and shipping them to factories near to their consumer market for final assembly, customization and distribution. These activities involve several different organizations that follow widely different approaches in logistical management. In order to sustain the long shipment distances in different geographic regions, (i.e. China-Mexico-US-Europe), handling & environmental conditions & shipping modes (Air vs Ground vs Sea); suitable, flexible and economical packaging solutions are required. This flow of semi-finished goods usually requires packaging materials such as carriers (i.e. wooden pallets) and moisture inhibitors (i.e. desiccants) to protect the goods. Competitive pressures, environmental consciousness, customer awareness and legislative requirements have driven manufacturers to review business practices and redesign solutions that are environmentally friendly, as well as help reduce costs in the long run. The author of this paper will present an experience where "non-traditional" packaging is used as an economical and environmental friendly solution to globally transport goods between multiple facilities.

Topics: Packaging , Logistics
Commentary by Dr. Valentin Fuster
2006;():139-143. doi:10.1115/IMECE2006-15561.

Accelerated thermal cycling tests are used to ascertain the reliability of solder interconnects in electronics assemblies. These tests typically last a few months and therefore, are highly resource intensive. Thermal shock tests on the other hand are faster but have been found to be ineffective in accelerating thermal cycling failures for eutectic tin lead solder. In this paper, thermal shock testing is proposed as an alternative to conventional thermal cycling testing for lead-free solder interconnects using Sn, Ag and Cu (SAC) solder. Results from the thermal shock and thermal cycling testing of Ball-Grid-Array (BGA) components are presented. Failure analyses of the solder joints reveal the failure mode for thermal shock in comparison to thermal cycling testing. Numerical modeling results for the thermal cycling and thermal shock testing for lead free and eutectic lead solder are then presented and discussed. The simulation results agree with the experiments and theory is proposed to account for the similar trends between thermal cycling and thermal shock testing for lead free solder.

Commentary by Dr. Valentin Fuster
2006;():145-154. doi:10.1115/IMECE2006-15759.

Lead free electronics soldering is driven by a combination of health and environmental concerns, international legislation and marketing pressure by lead free electronics manufacturing competitors. Since July 1, 2006 companies that do not comply with the European Union legislation are not able to sell circuit assemblies with lead solder in the European Union. China has developed its own regulations, based on the European Union documents with a compliance date of March 1, 2007. Lead free soldering requires an increase in reflow peak temperatures which will further aggravate component moisture sensitivity risks and thereby decrease assembly yield. Prior research has revealed a counterintuitive enhanced solder spreading phenomena at lower peak temperature and shorter time above liquidus with 63Sn/37Pb solder. This present study investigated solder wetting reactions in 96.5Sn/3.0Ag/.5Cu (WT%) (SAC305) using materials and manufacturing systems that are relevant to the electronics manufacturing industry. The objective was to advance the knowledge base of metal wetting such that solder joints can be effectively produced while avoiding heating the assembly any hotter then necessary for effective soldering, which would increase the risk of component damage due to rapid moisture outgassing and associated popcorn delamination. A classical design of experiments (DOE) approach was used with wetted area as the response variable. Additional sample characterization will be conducted outside of the DOE. The samples will be analyzed for correlation of reflow peak temperature, reflow time above liquidus, and wetted area. The expected results are 1) improved understanding of SAC lead free solder wetting reactions, 2) reduced SAC reflow peak temperatures, and thereby reduced risk of moisture sensitivity damage to components.

Topics: Alloys , Solders , Wetting
Commentary by Dr. Valentin Fuster
2006;():155-159. doi:10.1115/IMECE2006-16271.

The purpose of this paper is to investigate the indium joint strength with known indium oxide thickness. The indium joint strength was assessed by measuring the maximum load of indium solder with the comparison of the wetting angle. The oxide thickness was already grown in different ambient conditions, and provided for the joint strength measurement. The indium joint strength with different oxide thicknesses was tested at a fixed strain rate by tensile loading. This investigation will be very useful to characterize the indium solderability in different environment in terms of the quantitative joint strength.

Topics: Thickness
Commentary by Dr. Valentin Fuster
2006;():161-164. doi:10.1115/IMECE2006-13241.

In this study, Sn-Ag-Cu based nanocomposites with multi-walled carbon nanotubes (MWCNTs) as reinforcements were successfully synthesized using the powder metallurgy technique. Varying weight percentages of MWCNTs were blended together with micron size lead-free solder particles. The blended powder mixtures were then compacted, sintered and finally extruded at room temperature. The extruded materials were then used to characterize the melting point and to prepare lap-shear samples for creep tests. Miniature creep samples were created using a specially designed fixture and static loading creep tests were carried out on the solder joint samples at room temperature at 24N and 36N loads. Creep results showed improved creep resistance with the addition of MWCNTs. An attempt is made in the present study to correlate the variation in weight percentages of reinforcement with the creep properties of the resultant nanocomposite materials.

Commentary by Dr. Valentin Fuster
2006;():165-169. doi:10.1115/IMECE2006-13242.

Au/Sn eutectic solder alloy is particularly attractive for high-power electronics and optoelectronics packaging as hermetic sealing and die attachment material. The robustness and reliability of solder joint are essential to meet the global demand for longer operating lifetime in their applications. The mechanical response of Au/Sn solder alloy is studied using nanoindentation (Nano-Test 600). Miniature creep samples were created using a specially designed fixture and static loading creep tests were carried out on these solder samples at temperatures of 25°C, 75°C and 125°C using tensile testing machine (Micro-Testing System). The Young's Modulus and hardness of 80Au/20Sn solder alloy increase with an increase in load rate or a decrease in temperature. The microstructure and creep rupture fractography of 80Au/20Sn solder alloy have been observed and analysed.

Topics: Creep , Alloys , Solders
Commentary by Dr. Valentin Fuster
2006;():171-175. doi:10.1115/IMECE2006-13504.

Characterization of interfacial fracture parameters for nano-scale thin films continues to be challenging due to the difficulties associated with preparing samples, fixturing and loading the samples, and extracting and analyzing the experimental data. In this paper, we propose a stress-engineered superlayer test method that can be used to measure the interfacial fracture parameters of nano-scale (as well as micro-scale) thin films without the need for loading fixtures. The proposed test employs the residual stress in sputter-deposited metals to provide the energy for interfacial crack propagation. The innovative aspect of the test is the use of an etchable release layer that is deposited between the two interfacial materials of interest. The release layer is designed such that the available energy for interfacial crack propagation will continue to decrease as the crack propagates, and at the location where the crack ceases to propagate, the available energy for crack propagation will be the critical energy for crack propagation or the interfacial fracture toughness. The proposed test method has been successfully used to characterize Ti thin film on Si substrate.

Commentary by Dr. Valentin Fuster
2006;():177-181. doi:10.1115/IMECE2006-13615.

Accelerated Thermal Cycling (ATC) is traditionally used for assessing solder joint reliability. ATC typically takes as long as three to four months to complete. This paper proposes a new method to determine the fatigue life of solder joints using laser moiré technique. The developed method takes about a week to complete and gives us the detailed deformation behavior of each solder ball in the package at various temperatures. The developed method has been demonstrated for a high I/O organic BGA package. To illustrate the efficacy of the method, the results have been validated using experimental thermal cycling data.

Commentary by Dr. Valentin Fuster
2006;():183-187. doi:10.1115/IMECE2006-13750.

Gold nanowires were patterned with e-beam lithography and fabricated with a gold film deposited by e-beam evaporation. Carbon and oxygen contaminants were found to be present mostly on the gold surface with x-ray photoelectron spectroscopy. Slight carbon contamination was indicated through the film thickness. Dimensions of the nanowires were measured with scanning electron microscopy, and the resistance of the wires was measured with a 2-probe stage at a low vacuum. Non-linear current-voltage curves were obtained, which was attributed to Joule heating. Further analysis, by restricting the bias voltage in a small range and negligible Joule heating, suggests that surface contamination can significantly affect the resistivity measurements of gold nanowires.

Commentary by Dr. Valentin Fuster
2006;():189-199. doi:10.1115/IMECE2006-14383.

Thermal management of microprocessors has become an increasing challenge in recent years because of localized high flux hotspots which can not be effectively removed by conventional cooling techniques. This paper describes the novel use of the silicon chip itself as thermoelectric microcooler to suppress the hotspot temperature. A three-dimensional analytical thermal model of the silicon chip, including localized silicon thermoelectric cooling, thermoelectric heating, Joule heating, hotspot heating, background heating, and conductive/convective cooling on the back of the silicon chip, is developed and used to predict the on-chip hotspot cooling performance. The effects of chip thickness, microcooler size, doping concentration and parasitic Joule heating from the electric contact resistance on hotspot cooling are investigated in details.

Topics: Cooling , Modeling , Silicon
Commentary by Dr. Valentin Fuster
2006;():201-206. doi:10.1115/IMECE2006-15038.

A novel high resolution OFET (organic field effect transistor) fabrication process has been developed to realize low cost, large area electronics at low processing temperature without use of expensive, high temperature lithography process in vacuum. A drop-on-demand (DOD) ink-jetting system was used to print gold nano-particles suspended in Alpha-Terpineol solvent. Continuous Argon ion laser was irradiated locally to evaporate carrier solvent as well as sinter gold nano-particles in order to fabricate metal source and drain electrodes with high resolution and minimal thermal damage to the substrate. PVP (poly-4-vinylphenol) in Hexanol solvent and air-stable semiconductor polymer (Carboxulate - functionalized Polythiophenes) in 1,2-dichlorobenzene (o-DCB) solvent were spin-coated to form thin film of dielectric layer and semiconducting active layer. All of the processes were carried out in plastic-compatible low temperature, ambient air and atmospheric pressure environment. The OFETs showed good accumulation mode p-channel transistor behavior with carrier mobility of 0.01cm2 /V·s and Ion /Ioff ratio of ranging from 103 to 104 .

Commentary by Dr. Valentin Fuster
2006;():207-208. doi:10.1115/IMECE2006-15096.

We demonstrated the application of the atomic force microscope (AFM) in generation of controllable nano-gaps on single wall carbon nano-tubes (SWCNTs). Tapping mode AFM combined with interleave mode was used to image and manipulate the CNTs. By precise control of the loading force and the scan rate, we were able to generate desired gaps on CNT nanowires ranging from 10.6 nm to 58.8 nm. The gap size dependence on loading force and scan rate was discussed. Such a structure can be applied in fabrication of capacitancebased nano-device toward sensor applications.

Commentary by Dr. Valentin Fuster
2006;():209-214. doi:10.1115/IMECE2006-15581.

Micro and nano Au/Cr and Al thin film devices have been fabricated using DC sputtering and e-beam evaporation in combination with e-beam and photo lithography. These devices can be coated with specific reagents to detect and measure the presence of particular antigens and/or complementary DNA sequences with a smaller sample size and at much earlier stages of disease progression compared to current medical diagnostic technologies. Using the device material stack (Au/Cr/Si), we have assessed the binding affinity of Au, Cr, and Si with Protein G, and antibodies for Prostate Specific Antigen (PSA) and Cancer Antigen 125 (CA125), an ovarian cancer-associated antigen. Based on our experiments, we see that the thin gold layer of the Au/Cr/Si samples, provides increased bio-material binding affinity, and the chromium layer has a similar, if not less, binding affinity compared to the silicon chip alone.

Commentary by Dr. Valentin Fuster
2006;():215-222. doi:10.1115/IMECE2006-16014.

Demand for off-chip bandwidth has continued to increase. It is projected by the Semiconductor Industry Association in their International Technology Roadmap for Semiconductors (ITRS) that by the year 2015, the chip-to-substrate area-array input-output interconnects will require a pitch of 70 μm. Compliant off-chip interconnects show great potential to address these needs. G-Helix is a lithography-based electroplated compliant interconnect that can be fabricated at the wafer level. G-Helix interconnects exhibit excellent compliance in all three orthogonal directions, and can accommodate the CTE mismatch between the silicon die and the organic substrate without requiring an underfill. Also, these compliant interconnect are less likely to crack or delaminate the low-K dielectric material in current and future ICs. The interconnects are also potentially cost effective as they can be fabricated using conventional wafer fabrication infrastructure. In this paper we present an integrative approach which uses interconnects with varying compliance and thus varying electrical preformance from the center to the edge of the die. Using such a varying geometry from the center to the edge of the die, the system performance can be tailored by balancing electrical requirements against thermo-mechanical reliability concerns. We also discuss the reliability assessment results of helix interconnects assembled on an organic substrate. Results from mechanical characterization experiments are also presented.

Commentary by Dr. Valentin Fuster
2006;():223-228. doi:10.1115/IMECE2006-13014.

Stacked Chip Scale Package (SCSP) becomes popular recently because it increases package density and offers flexible component design at low cost. However, package reliability issues need to be carefully addressed because of the complex package geometry and structure. As one of the common failure modes, delamination is often encountered due to pre-existing defect and external loadings, such as thermal stress caused by different CTE of materials, hydro-swelling stress and vapor pressure caused by moisture desorption during reflow soldering. In SCSP, delamination often occurs along the interface of two dissimilar materials, primarily due to the weak interface bonding. Therefore, proper material selection and optimization of package structure are critical to reduce the risk of delamination in the design stage. Material selection is mainly based on the measurement of the interfacial fracture toughness or some quick-turn test to determine interface strength. Usually, the interfaces between die attach/die, die attach/substrate, mold/substrate and mold/die are evaluated. On the other hand, structural optimization is mainly carried out through numerical modeling to investigate the delamination sensitivity to stress, flaw size and position. Design parameters, such as die overhang, die thickness and bonding layer thickness are considered to have impact on the local stress distribution, which can lead to different delamination performance. Fracture mechanics based modeling, which can deal with pre-exist cracks, is adopted for this study. A typical multi-die stack chip scale package (CSP) is modeled by finite element to study the relationship between design parameters (die overhang, die thickness and bonding layer thickness) and stress intensity factor (SIF) for a delamination along die to mold compound interface. The effect of bonding layer (paste or adhesive film) CTE is also included in the present research as practically it can be changed by choosing different DA (die attach) materials. Optimized design parameters and considerations in package design can be proposed based on the modeling results.

Topics: Design , Delamination
Commentary by Dr. Valentin Fuster
2006;():229-233. doi:10.1115/IMECE2006-13016.

Low-cycle fatigue is a common failure mechanism in solder joints of a BGA in electronics packaging industry. Cyclic thermal loading leads to stress reversals and the accumulation of inelastic strain in the joints. In this paper the direct cyclic technique implemented in ABAQUS [1] has been used to predict the stabilized response of a BGA model subjected to cyclic thermal loading and cyclic bending loading respectively. The results are compared with the classical incremental simulation. Significant performance gains with very good accuracy of the direct cyclic approach are clearly demonstrated.

Commentary by Dr. Valentin Fuster
2006;():235-239. doi:10.1115/IMECE2006-13046.

Many factors such as high intensity current, thermal load, shock load, vibration load and etc., can induce the failure in electronic equipment. It is common for electronic equipment to be subjected to a combination of the loads mentioned above simultaneously. In this paper, qualitative finite element simulations of thermomigration induced strain fields in lead free solders are conducted using a fully coupled displacement-diffusion model [1] with nonlinear mechanical material properties. The solutions are discussed and compared to experimental data as well as theoretical developments from literature.

Commentary by Dr. Valentin Fuster
2006;():241-247. doi:10.1115/IMECE2006-13049.

A thermal fatigue life prediction model of a ceramic column grid array (CCGA) solder joint assembly has been developed when the 90Pb/10Sn solder columns of the CCGA package are soldered onto the printed circuit board with either tin-lead or lead-free solder paste. This model was evolved from an empirically derived formula by correlating the solder nonelastic strain energy density increment to the fatigue life test data. To develop the solder joint fatigue life prediction model, a nonlinear finite element analysis (FEA) was conducted using the ABAQUS computer code. A thermal fatigue life prediction model was then established. The test results, obtained from various sources in which tin-lead and lead-free solder pastes on PCB were used, combined with the FEA derived nonelastic strain energy density per temperature cycle, ΔW, were used to calibrate the proposed life prediction model. In the analysis, 3-D finite element global- and sub-modeling techniques were used to determine the ΔW of the CCGA solder joints when subjected to temperature cycling. The analysis results show that: 1) solder joint would typically fail across solder column instead of along solder pad interfaces; and 2) higher nonelastic strain energy densities of solder occur at the solder columns at the package corners and these solder joints would fail first. These analysis predictions are consistent with the test observations. In the model calibration process, the 625- and 1657-pin CCGA test results, which were cycled between 20°C/90°C, 0°C/100°C, -55°C/110°C, or -55°C/125°C, were reasonably well correlated to the predicted values of ΔW. Therefore, the developed life prediction model could be used and is recommended to serve as an effective tool to determine the integrity of the CCGA solder joints during temperature cycling. In addition, the following future work is recommended: 1) selecting more study cases with various solder joint configurations, package sizes, environmental profiles, etc. to further calibrate this life prediction model; 2) using this model to conduct parametric studies to identify critical factors impacting solder joint fatigue life and then seek an optimum design; and 3) developing a simplified method instead of the FEA approach to make preliminary thermal fatigue life estimates of the CCGA solder joints.

Topics: Fatigue life
Commentary by Dr. Valentin Fuster
2006;():249-256. doi:10.1115/IMECE2006-13298.

The work focuses on the thermally induced out of plane displacement of Flip Chip Ball Grid Arrays (FCBGA). Analytical expressions for substrate displacements are derived based on the Plate Theory and Suhir's solution for stresses in tri-material assembly. The validity of the model is established by comparing the analytical solution to the finite element results as well as to the experimental data. The benefits of the model are twofold: 1) it provides a tool for fundamental understanding of the parameters that influence warpage, and 2) has a predictive capability. With respect to 1) an analysis is presented on the nature and degree of influence that different geometric and material parameters have on the FCBGA warpage. With respect to 2) the "Warpage Contour Plot" is proposed as a tool for warpage prediction that can be easily utilized in the early stages of the design process.

Commentary by Dr. Valentin Fuster
2006;():257-263. doi:10.1115/IMECE2006-13328.

The present study is aimed at investigating the effect of solder mask thickness on the solder ball shear test. Compared to the ball pull test, less brittle failures were found in the ball shear test. This is most likely caused by the support of solder mask. So far there is not publication reporting the effect of solder mask in detail. In this paper, specimens with various thicknesses of solder mask were fabricated and a series of ball shear tests were conducted. Cold ball pull (CBP) tests were performed as well for parallel studies. The attachment strength of solder balls under multiple reflows was evaluated as an index for comparison. The test results indicate that, in ball shear tests, brittle failures can be identified more easily in specimens with thinner solder mask after multiple reflows, especially for tests with higher shear speed and more reflows. No obvious effect of solder mask thickness on the ball pull test was found, regardless of different pulling speeds and multiple reflows.

Commentary by Dr. Valentin Fuster
2006;():265-269. doi:10.1115/IMECE2006-13583.

This paper characterizes the fatigue failure envelopes for solder damage in Printed Wiring Assemblies (PWAs) subjected to dynamic loading. An empirical, rate-dependent, power-law durability model, motivated by mechanistic considerations, is used to characterize the failure envelopes in terms of PWA flexural strain and strain rate. Explicit nonlinear finite element analysis (FEA) is used to make the damage constants independent of the specimen geometry and characterize the durability in terms of the ratio of solder plastic strain to its failure strain. A case study, using a simple PWA specimen containing a single area array component, is presented to demonstrate the proposed approach.

Commentary by Dr. Valentin Fuster
2006;():271-280. doi:10.1115/IMECE2006-13584.

A global-local approach is used to qualitatively understand the dependence of intermetallic failure on specimen geometry, interconnect material property and interfacial morphology. The structure of interest is an area array package that is subjected to flexural loading. The interconnect is modeled as a thin continuous layer, sandwiched between the component and the board. The global model uses a closed-form low-order analytical solution to estimate the shear and peeling stresses in the interconnect. A parametric analysis is conducted to characterize the variation of the stresses with specimen geometry and material properties. The local model uses fracture mechanics to relate the strain energy release rate at the interface to the morphology of the intermetallic layer. It is shown that for a given Printed Wiring Assembly (PWA) and loading condition, the strain energy release rate at the interface increases with decreasing interfacial roughness. This could explain why one observes failure site transition from the solder to the intermetallic layer during flexural loading of aged specimens.

Commentary by Dr. Valentin Fuster
2006;():281-288. doi:10.1115/IMECE2006-13605.

This paper presents a damage mechanics-based methodology for the progressive damage and virtual qualification of advanced electronic packages such as BGAs, DCAs, CSPs, and Flip-chips. The key technique is to implement the material nonlinearity into commercially available software tools. A unified viscoplastic constitutive framework with the damage evolution and failure criteria has been successfully implemented into the ABAQUS® code to model time-rate-temperature dependent material properties. The framework has been successfully applied to solder alloys, polymer films, and underfill encapsulants. The mathematical structure and numerical algorithm development of the unified constitutive framework as well as the key implementation techniques for commercial FEA codes have been summarized in this paper. Both crack initiation and propagation of a solder joint with damage evolution under mechanical cyclic loading have been demonstrated. Virtual simulations of TSOP component failure under mechanical cyclic loading and BGA package under thermal cyclic loading have also been presented.

Commentary by Dr. Valentin Fuster
2006;():289-303. doi:10.1115/IMECE2006-13800.

In order to improve electronics packaging design, it is important to evaluate cooling performance and reliability of the electronics packaging structure. To that end, it is necessary to predict the temperature, deformation, and stress distribution of the package under field conditions. In the case of a packaging structure comprising a flip-chip ball grid array (FC-BGA) package, a heat spreader, thermal grease, a cooling structure, solder joints, and a motherboard, an increase in the contact thermal resistance may occur, depending on the interface contact condition between the cooling structure and the heat-spreader due to the thermal deformation of the package. Contact thermal resistance problems involve the interactive relationship of the thermal and stress distribution. A coupled thermal-stress analysis, with consideration of the time-space variation of contact thermal resistance, was conducted to duplicate the behavior of temperature, deformation, and stress distributions of a FC-BGA package under field conditions. It was found (1) that the average contact thermal resistance across the interface between the heat-spreader and the plate fin, which was predicted by the coupled thermal-stress analysis, increased compared to that in the case of uniform contact pressure, and (2) that the contact thermal resistance will vary depending on the deformation mode, such as convex upward and downward, due to heat dissipation during field conditions. In addition, a reliability prediction method for thermal fatigue failure of solder bumps based on coupled thermal-stress analysis and statistical and probabilistic methods was proposed in order to select a suitable packaging solution at an early stage of design.

Commentary by Dr. Valentin Fuster
2006;():305-309. doi:10.1115/IMECE2006-13819.

This paper provides a method and algorithm for fast design of BGA bump/solder joints, quick analysis of solder defect root cause and design improvement in a cost saving manner. The method uses a general and explicit form to incorporate the cause and effect relationship of design and process parameters into BGA solder interconnect designs, provides a design for reducing or eliminating voids in BGA solder joints. The design method for BGA bump, dummy bump, solder interconnect and pad stack designs enables rapid design evaluation for BGA solderability. Typically, it provides 1) fast design for BGA bump and solder joint with respect to high solderability; and 2) a quantitative guideline on how to improve BGA designs for an optimal solderability.

Commentary by Dr. Valentin Fuster
2006;():311-319. doi:10.1115/IMECE2006-14371.

The reliability of portable electronic devices is of critical importance due to the consumer boom in mobile telephony in recent years. Impact is a key driver of failure in portable electronics and, in current design practice, extensive testing is used in conjunction with finite element simulations to ensure product reliability under impact stimuli. Testing is time-consuming and expensive – both free-drop and constrained drop tests are usually applied – and simulation techniques are very computationally intensive. The response of portable electronic devices to impact is currently not well understood, and there is clear need for investigation into the range of acceleration levels experienced by a representative model of a portable electronic device on impact. In this paper, free-drop testing was carried out on test vehicles representative of a typical mobile phone in order to acquire acceleration data from impact events. Drop test vehicles from Nylon and aluminium were used to provide a means of comparison for diverse material properties. The primary conclusion was that the dynamics of each drop event were highly sensitive to the initial conditions of the drop test, which was evident from wide variances in the acceleration data.

Commentary by Dr. Valentin Fuster
2006;():321-327. doi:10.1115/IMECE2006-14706.

An LGA (Land Grid Array) laminate-based epoxy-molded RF SiP (system-in-package) containing four wirebonded and three flip-chip dice is qualified using a PoF (Physics-of-Failure) approach. The process includes design and execution of accelerated stress testing. The test results are extrapolated to field environments using acceleration factors derived from virtual qualification (VQ) and virtual testing (VT). In the VQ step, life-cycle loading experienced by the specimen is simulated, potential failure sites are identified, and reliability assessment models for each failure mode are applied for damage analysis. The virtual testing (VT) step is similar to VQ, except that the accelerated loading developed for the experimentation phase is used. The output of the process is a lifetime assessment, based on the accelerated test results and the acceleration factors derived from PoF considerations.

Commentary by Dr. Valentin Fuster
2006;():329-334. doi:10.1115/IMECE2006-14745.

This paper presents a numerical DOE to investigate the sensitivity of the mechanical performance of LGA contacts, e.g. contact working range, wiping distance and force, to four key design parameters: contact free height, contact thickness, contact material yield strength and the coefficient between the contact and its landing pad. Multiple cases were analyzed and the normalized response surfaces of the performance are presented. By keeping the linear terms of the response surfaces, the performance variances relative to the nominal can be estimated. The methodology using the estimated variances to define LGA contact design specification is also presented.

Topics: Design
Commentary by Dr. Valentin Fuster
2006;():335-339. doi:10.1115/IMECE2006-14791.

This study describes a wafer bonding technique using CYTOP™ inking method for the high volume packaging of micro-electro mechanical system (MEMS) devices. CYTOP™ is a class of perfluoro (alkenyl vinyl ether) polymer which is obtained by cyclopolymerization of perfluoro. The CYTOP™ adhesive bonding requires much lower temperature (150 to 200° C) compared to other bonding techniques such as soldering (> 250° C) or anodic (~350° C) bonding. The lower temperatures involved in the process reduce the risk of thermal damage to temperature sensitive devices during packaging. The described bonding process consists of a wet inking technique in which wet CYTOP™ ink is applied on soft cured CYTOP™ before bonding. In this study, CYTOP™ is characterized for its bonding strength and quality. The experiments are performed on silicon and glass wafer substrates. The bonded samples are pull-tested and tensile stress values are recorded at the instance of bond failure. About 90% of the samples failed at the bonding interface which indicates that the recorded stress values are the bond strength of CYTOP™. The bond strength of CYTOP™ depends upon the curing temperature and the curing time. The highest bond strength of 16. 46 MPa is recorded at 200° C and 45 min. of curing. The CYTOP™ bond strength at 200° C is comparable with bond strength of BCB at 250° C.

Commentary by Dr. Valentin Fuster
2006;():341-344. doi:10.1115/IMECE2006-14997.

In this paper the selective patterning of poly [2-methoxy-5-(2'-ethylhexyloxy)-1, 4-phenylenevinylene] (MEH-PPV) and poly (3, 4-ethylenedioxythiophene) poly (styrenesulfonate) (PEDOT: PSS) based on reactive ion etching for device fabrication is examined. These polymers were anisotropically etched using RIE in a helium plasma. Results show clearly that RIE using helium gas is effective at etching the polymers from the selected areas without physical damage to the working device. Further results show the electroluminescence spectra of etched and unetched devices have almost identical emission spectra, when these devices are operated as an LED. The external quantum efficiency (EQE) for these photodetectors was calculated and EQE peak values reached at 580nm are consistent between etched devices and unetched controls. Test devices show no decrease in EQE performance from RIE.

Topics: Polymers , Etching
Commentary by Dr. Valentin Fuster
2006;():345-350. doi:10.1115/IMECE2006-15432.

With the trend of electronic consumer product toward more functionality, high performance and miniaturization, IC chip is required to deliver more I/Os signals and better electrical characteristics under same package form factor. Thus, Flip Chip BGA (FCBGA) package was developed to meet those requirements offering better electrical performance, more I/O pins accommodation and high transmission speed. For high-speed application, the low dielectric constant (low-k) material that can effectively reduce the signal delays is extensively used in IC chips. However, the low-k material possesses fragile mechanical property and high coefficient of thermal expansion (CTE) compared with silicon chip, which raises the reliability concerns of low-k material integrated into IC chip. The typical reliability failure modes are low-k layer delamination and bump crack under temperature loading during assembly and reliability test. Delamination is occurred in the interface between low-k dielectric layers and underfill material at chip corner. Bump crack is at Under Bump Metallization (UBM) corner. Thus, the adequate underfill material selection becomes very important for both solder bump and low-k chips [1]. This paper mainly characterized FCBGA underfill materials to guide the adequate candidates to prevent failures on low-k chip and solder bump. Firstly, test vehicle was a FCBGA package with heat spreader and was investigated the thermal stress by finite element models. In order to analyze localized low-k structures, sub-modeling technique is used for underfill characterizations. Then, the proper underfill candidates picked from modeling results were experimentally validated by reliability tests. Finally, various low-k FCBGA package structures were also studied with same finite element technique.

Commentary by Dr. Valentin Fuster
2006;():351-363. doi:10.1115/IMECE2006-15443.

In this work, risk-management and decision-support models for reliability prediction of flip chip packages in harsh environments have been presented. The models presented in this paper provide decision guidance for smart selection of component packaging technologies and perturbing product designs for minimal risk insertion of new packaging technologies. In addition, qualitative parameter interaction effects, which are often ignored in closed-form modeling, have been incorporated in this work. Previous studies have focused on development of modeling tools at sub-scale or component level. The tools are often available only in an offline manner for decision support and risk assessment of advanced technology programs. There is need for a turn key approach, for making trade-offs between geometry and materials and quantitatively evaluating the impact on reliability. Multivariate linear regression and robust principal components regression methods were used for developing these models. The first approach uses the potentially important variables from stepwise regression, and the second approach uses the principal components obtained from the eigen-values and eigen-vectors, for model building. Principal-component models have been included because if their added ability in addressing multi-collinearity. The statistics models are based on accelerated test data in harsh environments, while failure mechanics models are based on damage mechanics and material constitutive behavior. Statistical models developed in the present work are based on failure data collected from the published literature and extensive accelerated test reliability database in harsh environments, collected by center of advanced vehicle electronics. Sensitivity relations for geometry, materials, and architectures based on statistical models, failure mechanics based closed form models and FEA models have been developed. Convergence of statistical, failure mechanics, and FEA based model sensitivities with experimental data has been demonstrated.

Commentary by Dr. Valentin Fuster
2006;():365-374. doi:10.1115/IMECE2006-15450.

Electronic products may be subjected shock and vibration during shipping, normal usage and accidental drop. High-strain rate transient bending produced by such loads may result in failure of fine-pitch electronics. Current experimental techniques rely on electrical resistance for determination of failure. Significant advantage can be gained by prior knowledge of impending failure for applications where the consequences of system-failure may be catastrophic. This research effort focuses on an alternate approach to damage-quantification in electronic assemblies subjected to shock and vibration, without testing for electrical continuity. The proposed approach can be extended to monitor product-level damage. In this paper, statistical pattern recognition and leading indicators of shock-damage have been used to study the damage initiation and progression in shock and drop of electronic assemblies. Statistical pattern recognition is currently being employed in a variety of engineering and scientific disciplines such as biology, psychology, medicine, marketing, artificial intelligence, computer vision and remote sensing [Jain, et. al. 2000]. The application quantification of shock damage in electronic assemblies is new. Previously, free vibration of rectangular plates has been studied by various researchers [Leissa 1969, Young 1950, Gorman 1982, Gurgoze 1984, Wu 2003] for development of analytical closed-form models. In this paper, closed-form models have been developed for the eigen-frequencies and mode-shapes of electronic assemblies with various boundary conditions and component placement configurations. Model predictions have been validated with experimental data from modal analysis. Pristine configurations have been perturbed to quantify the degradation in confidence values with progression of damage. Sensitivity of leading indicators of shock-damage to subtle changes in boundary conditions, effective flexural rigidity, and transient strain response have been quantified. A damage index for Experimental Damage Monitoring has been developed using the failure indicators. The above damage monitoring approach is not based on electrical continuity and hence can be applied to any electronic assembly structure irrespective of the interconnections. The damage index developed provides parametric damage progression data, thus removing the limitation of current failure testing, where the damage progression can not be monitored. Hence the proposed method does not require the assumption that the failure occurs abruptly after some number of drops and can be extended to product level drops.

Commentary by Dr. Valentin Fuster
2006;():375-384. doi:10.1115/IMECE2006-15484.

The thermophysical properties of a commercially available Polyphenylene Sulphide (PPS)-carbon fiber composite material are experimentally characterized and used to validate application of the Nielsen thermal conductivity model to this category of polymer matrix composites. The PPS-fiber thermal conductivity was measured in the three orthogonal directions, using the laser flash thermal diffusivity method, and found to display significant anisotropy. Thermal conductivity predictions based on the Nielsen model, and using E-SEM measured values of fiber dimensions and fiber orientation and carbon fiber mass content determined from TGA analysis, were found to be within 5% of the corresponding measurements. The close agreement between predictions and measurements permitted the determination of the morphological influence of fiber material, volume content and orientation, and resin and fiber thermal conductivities, on thermal conductivity to be parametrically investigated and optimized for a given formulation. The impact of this optimization on the thermal performance of a PPS-fiber pin fin is described.

Commentary by Dr. Valentin Fuster
2006;():385-400. doi:10.1115/IMECE2006-15491.

Solder materials demonstrate evolving microstructure and mechanical behavior that changes significantly with environmental exposures such as isothermal aging and thermal cycling. These aging effects are greatly exacerbated at higher temperatures typical of thermal cycling qualification tests for harsh environment electronic packaging. In the current study, mechanical measurements of thermal aging effects and material behavior evolution of lead free solders have been performed. Extreme care has been taken so that the fabricated solder uniaxial test specimens accurately reflect the solder materials present in actual lead free solder joints. A novel specimen preparation procedure has been developed where the solder uniaxial test specimens are formed in high precision rectangular cross-section glass tubes using a vacuum suction process. The tubes are then sent through a SMT reflow to re-melt the solder in the tubes and subject them to any desired temperature profile (i.e. same as actual solder joints). Using specimens fabricated with the developed procedure, isothermal aging effects and viscoplastic material behavior evolution have been characterized for 95.5Sn4.0Ag-0.5Cu (SAC405) and 96.5Sn-3.0Ag-0.5Cu (SAC305) lead free solders, which are commonly used as the solder ball alloy in lead free BGAs and other components. Analogous tests were performed with 63Sn-37Pb eutectic solder samples for comparison purposes. In our total experimental program, samples have been solidified with both reflowed and water quenching temperature profiles, and isothermal aging has been performed at room temperature (25 °C) and elevated temperatures (100 °C, 125 °C and 150 °C). In this paper, we have concentrated on reporting the results of the room temperature aging experiments. Variations of the temperature dependent mechanical properties (elastic modulus, yield stress, ultimate strength, creep compliance, etc.) were observed and modeled as a function of room temperature aging time. Microstructural changes during. room temperature aging have also been recorded for the solder alloys and correlated with the observed mechanical behavior changes.

Commentary by Dr. Valentin Fuster
2006;():401-407. doi:10.1115/IMECE2006-15522.

Heat sinks are one of the primary mechanisms today for thermal management of electronics. In the high altitudes reached by modern military aircraft, the capacity for air cooling is reduced due to the rarefied atmosphere. With an increase in altitude there is a subsequent decrease in the density of air. A review of the literature shows a lack of research done on pin-fin heat sinks with impingement flows at low Reynolds number conditions. Experimental testing will determine the thermal resistance of a pin-fin heat sink with impingement flow at low absolute pressures. A test apparatus will be constructed, and experiments will be conducted within a hypobaric chamber. In a hypobaric chamber, it is possible to simulate altitudes up to 30 000 meters by reducing the absolute pressure using a vacuum pump. Temperature is regulated and air is circulated within the chamber. The test apparatus, which is to be completely enclosed within the hypobaric chamber, consists of a centrifugal blower forcing air through a duct. Air is impinged upon a pin-fin heat sink heated with uniform flux on the base. Incident air flow is along the axis of each circular pin-fin, and exhaust from the heat sink will be transverse to the pins. Feedthroughs are available in the chamber wall for supplying electrical power to the blower, for taking temperature measurements with embedded thermocouples, and for measuring blower shaft speed. Temperature measurements are made in the base of the heat sink, in the air, and at other points to characterize other heat losses from the apparatus. Blower speed is monitored with an optical tachometer, and by similarity laws for turbomachinery it will be possible to determine the air flow impinging upon the heat sink. Pressure in the chamber will be varied in several steps up to the equivalent of a 30 000-meter altitude, and at each step a correlation will be made between heat sink thermal resistance and Reynolds number of the impinging air.

Commentary by Dr. Valentin Fuster
2006;():409-418. doi:10.1115/IMECE2006-15542.

A software tool, "Integrated Reliability Solutions" (IRS) has been developed, based upon the methodologies that have been applied to solving mechanical reliability problems of electronic components. The tool provides a system approach to reliability modeling. This tool enables significant reductions in design cycle time, warranty costs, and time required for experimentation and accelerated life testing. It also enables robust design and optimized manufacturing processes, and the timely and accurate innovation, evaluation and validation of new technologies.

Commentary by Dr. Valentin Fuster
2006;():419-424. doi:10.1115/IMECE2006-15662.

Steady-state and residual FEA thermal stress analysis of a Concentrating Photovoltaic (CPV) cell module is performed in this study. This investigation covers the nominal and extreme operating conditions, including system startup and shutdown. The physical properties of different epoxies were substituted into the model and the model results were used to identify the optimal bonding materials. Different thermal boundary conditions were evaluated for optimal performance. As the first step of module life prediction, residual stresses corresponding to different temperatures were calculated. The analysis revealed that the thermal expansion mismatch between the bonded materials is a major design concern, since it can cause structural failure at critical interface locations.

Commentary by Dr. Valentin Fuster
2006;():425-433. doi:10.1115/IMECE2006-15678.

Warpage has long been known to cause thermomechanical reliability problems in electronic packaging. The coefficient of thermal expansion (CTE) mismatch between different materials in an electronic assembly such as solder, copper, FR-4, encapsulation molding, and silicon is known to be one of the leading causes of manufacturing defects and fatigue failures. The CTE mismatch between packaging materials induces thermomechanical stresses at interfaces between the materials. Warpage is a global effect of interfacial stress and displacement. The warpage problem in electronic packaging can be further aggravated by thermal processes such as reflow and temperature cycling. In a printed wiring board assembly (PWBA), warpage of the PWB or chip packages may result in chip package misregistration, solder joint failure, die cracking and delamination of the solder bumps between chip packages and the PWB. In this paper, the warpage of a printed wiring board assembly (PWBA) is studied using projection moiré experimental measurements and a finite element model. The effects of plastic ball grid array (PBGA) chip package placement on PWB warpage during convective reflow will be evaluated. The projection moiré experimental warpage results will show that the number of PBGA chip packages as well as their location has an effect on the warpage of the PWB. In addition to the experimental results, the finite element warpage results will be used to make recommendations on the optimal PBGA package placement locations on the PWB to minimize PWB warpage during reflow processes.

Commentary by Dr. Valentin Fuster
2006;():435-442. doi:10.1115/IMECE2006-15682.

The shadow moiré technique is a widely used method of measuring printed wiring board (PWB) warpage. It has a high resolution, high accuracy and is suitable for use in an online environment. A shortcoming of the shadow moiré technique is that it cannot be used to measure PWBs populated with chip packages. In this paper, a novel warpage measurement system based on the projection moiré technique is presented. The system can be used to measure bare PWBs as well as PWBs populated with chip packages. In order to use the projection moiré system to accurately determine the warpage of PWBs and chip packages separately, an automated chip package detection algorithm based on active contours is utilized. Unlike the shadow moiré technique which uses a glass grating, the projection moiré technique uses a virtual grating. The virtual grating sizes can be adjusted, making it versatile for measuring various PWB and chip package sizes. Without the glass grating, which is a substantial heat inertia, the PWB/PWBA/chip package sample can be heated more evenly during the thermal process. The projection moiré system described in this paper can also be used to measure PWB/PWBA/chip package warpage during convective reflow processes. In this paper, the characteristics of the projection moiré warpage measurement system will be described. In addition, the system will be used to measure the warpage of a PWB and plastic ball grid array (PBGA) packages during a Lee optimized convective reflow process. It is concluded that this projection moiré warpage measurement system is a powerful tool to study the warpage of populated PWBs during convective reflow processes.

Topics: Warping
Commentary by Dr. Valentin Fuster
2006;():443-449. doi:10.1115/IMECE2006-15704.

We will present a novel micromirror design in which tethered bimorph strips are used for mirror active alignment including beam steering and position fixing. A micromirror is attached to bimorphs that are pre-stressed at room temperature. A series of tethers link the bimorphs to the substrate to restrain their deformation. Breaking a tether by Joule heating allows the deformation of the bimorph to increase, changing the mirror position and orientation for precision alignment. With a large number of tethers, an optimum alignment can be achieved after breaking a selected group of tethers. We also report the experimental results of devices fabricated.

Commentary by Dr. Valentin Fuster
2006;():451-457. doi:10.1115/IMECE2006-15725.

Miniaturization in the electronics industry has made electronic packaging a very critical area of design and it has become crucial in gaining competitive advantage in a constantly evolving and dynamic market. One key to fast, reliable and economical electronic packaging design is quick modeling of the components and assemblies and accurate thermo-mechanical analyses. With quicker modeling there can be a greater focus on other analyses like fatigue, drop, shipping shock, moisture absorption/desorption etc. This paper presents ongoing work to automate a large part of electronic chip scale package modeling that can lead to a considerable reduction in lead time in modeling and can result in significant savings for the electronic industry. Through a host of ABAQUS scripts, modeling of multi-layered chip scale package (CSP) has been customized and has been made parameter based which can be easily manipulated by the user using ABAQUS/CAE. Solder ball modeling, which is a major component of the CSP modeling effort, is critical in analysis and consumes maximum time in chip-scale modeling due to its repetitive nature has also been automated and customized for ABAQUS/CAE. This approach can produce a big leap in chip scale modeling and analysis as the scripts can be embedded in larger automated systems that can result in a high degree of efficiency and cost saving. The paper thus discusses the methodology, scope and application of automation in CSP modeling.

Commentary by Dr. Valentin Fuster
2006;():459-465. doi:10.1115/IMECE2006-16074.

Large Flip Chip BGA (FCBGA) packages are needed in high pin out applications (>1800), e.g., ASIC's and are typically used in high reliability and robustness applications. Hence understanding the package reliability and robustness becomes one of paramount importance for efficient product design. There are various aspects to the package that need to be understood, to ensure an effective design. The focus of this paper is to understand the BGA reliability of the package with particular reference to comparison of the surface finish, vis-à-vis, between Electroless Nickel Immersion Gold (ENIG) and Solder On Pad (SOP) on the substrate side of the package, which are the typical solutions for large plastic FC-BGA packages. Tests, which include board level temperature cycling, monotonic bend and shock testing have been conducted to compare the two surface finish options. The results of these tests demonstrate that the mechanical strength of the interface exceeds by a factor of two for the SOP surface finish, while BGA design parameters play a key role in ensuring comparative temperature cycle reliability in comparison with ENIG packages.

Commentary by Dr. Valentin Fuster
2006;():467-477. doi:10.1115/IMECE2006-16255.

As the use of polymeric materials is increasing in microelectronics industry, the failure issues related to moisture are getting more popular. Moisture absorbed into the electronic package causes interfacial delamination through the synergetic effects of hygro-thermo-mechanical stresses and degradation of adhesion strength. It also results in catastrophic crack propagation during reflow process, called pop-coming. Vapor pressure inside preexisting voids at material interfaces is known to be a dominant driving force of this phenomenon. In order to explain vapor pressure generation at high reflow temperature, researchers so far have been presuming two mechanisms: liquid water boiling and quick moisture diffusion. In spite of the importance as a basis of the failure analysis, there has been little focus on the mechanism of liquid water accumulation, more exactly, high vapor pressure generation inside voids. In this study various known mechanisms of liquid water formation inside a void at polymer interface are reviewed. They include condensation, adsorption, capillary, and microfogging. As an alternative possibility, moisture diffusion around the void for a short reflow period is also assessed through numerical analysis.

Topics: Polymers , Water
Commentary by Dr. Valentin Fuster
2006;():479-485. doi:10.1115/IMECE2006-16256.

There has been an increasing interest in the applications of thin membrane in space application, flexible electronic display, manufacturing of glass displays and growth of film on materials at elevated temperatures. Because of the negligible bending stiffness of thin membranes, membranes are lack of resistance to compressive stress. For the applications at high temperatures, the thermal expansion coefficient mismatch between membrane and substrate materials may generate compressive stress that causes the membrane buckling. The study of thermal buckling of isotropic elastic plate in the context of the large - deflection theory was the subject of a series of papers[1-5]. However, it has been noted that none of these papers has considered the second buckling of the membrane resulting in membrane wrinkling. The presence of wrinkles may significantly change deflection and stress profile of membranes. So, it is important to develop an effective analysis method to investigate the wrinkle formation and evolution in membrane subjected the elevated temperature. This paper presents the experiment work to investigate wrinkle formation and evolution in membranes heated from room temperature up to 170 °C. The specimens consist of polymer and metal membranes with steel and silicon substrate respectively. A wide range of membrane shapes and aspect ratios are considered in this work. An experiment set up is developed to study the deflection profiles of membranes at discrete temperatures. The information gained from this experiment work is used to validate numerical modeling results. The Finite Element Analysis results using nonlinear post-buckling analysis are also included in this paper. The nonlinear post-buckling analysis provides a good understanding of the mechanism of wrinkle generation and evolution as temperature increased. It is shown that the first buckling of membrane significantly reduces bending stiffness thus to create localized buckling modes accounting for the wrinkle generation. The wrinkle pattern is stable until the temperature reaches the next critical value. After this critical temperature, the wrinkle pattern is changed until temperature reaches the next critical value. The new wrinkle pattern is keeping evolved until the final temperature is reached. The finite element analysis results are in good agreement with experimental observations.

Topics: Membranes
Commentary by Dr. Valentin Fuster

Multi-Scale Electrical and Mechanical Systems

2006;():489-490. doi:10.1115/IMECE2006-13441.

Among the subtractive fabrication techniques nanoimprint lithography followed by metal etching processes3,4,5 provides features with size down to tens of nanometers6,7 . With the aid of high strength tool, the resolution of electrochemical machining (ECM) has been pushed to sub-hundred nanometer regime4 . As much as the high resolution it is capable of, nanoimprint lithography followed by metal etching processes bears the multi-step, complex lithography processes that require stringent process environment control and high-cost equipments. Similarly, the pattern dimension fidelity and pattern geometry of the transferred feature is limited by the current density distribution in the liquid-state electrolyte and its physical properties. Effort has been on developing patterning techniques and logic devices that are based on the ionic mass transport property in solid electrolytes. A quantized conductance atomic switch that operates at 1MHz with 0.6V of driving potential has been developed wherein silver mobile atoms bridges and opens the tunneling gap between Pt and silver sulfide wires when driven by a gate potential8 . Nanopatterning techniques utilizing local metal cluster deposition and dissolution have also been developed to achieve sub-hundred nanometer line writing and dot deposition with scanning probe microscopy9,10,11 . Here we present a novel solid state ionic subtractive stamping technique which provides nanoscale patterning of metallic features with high resolution. Developed based upon a single-step electrochemical material dissolution process in ambient conditions, this technique offers high throughput and high fidelity in metal pattern transfer at nanoscale, as well as the flexibility to be used for various kinds of metals and to be integrated with other nano-fabrication techniques for applications such as chemical sensors and photonic structures. Shown in Figure 1 is a model of ionic migration of silver species in a solid-state ionic conductor, silver sulfide. When subjected to an electric field applied across a silver-silver sulfide interface through anode and cathode attached to them respectively, in achieving the equilibrium of the electrochemical potential of silver atoms in the silver substrate and that in silver sulfide, silver atoms in the substrate oxidize into mobile ions and electrons. These mobilized silver ions then move freely from the interface through the conduction channels in the silver sulfide bulk towards the cathode. Upon receiving electrons when reaching cathode, silver ions reduce back to atoms and deposit on the interface between the cathode and Ag2 S. The oxidation at the interface between anode and Ag2 S is an ideal tool for surface micromachining in that mass transport only occurs at the portion of the surfaces of anode where actual physical contact exists, making it an ideal tool for pattern transfer. In our preliminary experiments, silver sulfide and silver substrate were chosen and stamping apparatus was built to perform solid state ionic subtractive stamping. Stamping was performed with the chronoamperometry operation mode of the Potentiostat for chosen potentials. Stampings were also run with a fixed potential of 0.3 V but different lengths of time for stamping rate analysis. Shown in figure 2 are the SEM images of the silver sulfide stamp and the produced silver feature. The lateral resolution achieved is 120nm for line width. Shown in figure 3 are the stamping depths measured at different time steps of a stamping process and the calculated stamping rates at different time steps. The silver removal rate throughout the stamping process is found to remain the same. The constant stamping rate suggests constant ionic conduction which means constant ionic conductivity-the ionic conductivity of silver sulfide remains constant irrespective of silver concentration change, or the composition of the silver sulfide stamp. This is in good agreement with Hebb and Wagner12,13 in their electrochemical measurements of silver sulfide which states that ionic conductivity of silver sulfide is almost independent of composition, given the structure of β-form silver sulfide is quite open and the considerable freedom in the disposition of silver ions. The rough surface of the generated features seen in figure 2 is thought to be due to the small depth of the pattern on the silver sulfide stamp which causes undesirable etch of silver and pulling of silver grains; the characterization and optimization of it is currently being investigated. To conclude, we have demonstrated a unique technique to pattern metal with sub-micron resolution in a high-throughput stamping process. The process is a solid-state, room temperature process that is highly compatible with a large variety of process technologies. In our initial attempt, a lateral resolution of 120nm is achieved.

Topics: Metal stamping
Commentary by Dr. Valentin Fuster
2006;():491-492. doi:10.1115/IMECE2006-13937.

A multilayer micro-electrochemical impedance spectroscopic (μ-EIS) system with an integrated Ag/AgCI reference electrode has been developed using MEMS technologies. This μ-EIS system is used to characterize ionic and fluidic transport across nanocapillary array membranes (NCAM), which are comprised of arrays of individual nanopores. Impedance measurements giving magnitude, phase, and I-V characteristics provide insight into the interaction between translocating ions and the electric double layer (EDL) within nanocapillaries due to changes in the surface zeta potential and the ionic charge of the electrolyte. μ-EIS measurements for ionic flow through the NCAM with pore diameters from 10 to 800 nm with an aqueous salt solution indicate that these NCAM behave as nearly ideal RC circuits at electrolyte concentrations on the order of 100 mM, when the EDL within these pores do not overlap. Nyquist plots show an increase in the RC time constant with decreasing salt concentration. Under conditions of EDL overlap, hindered transport in the pores causes deviation from ideal RC circuit-like behaviour with the capacitive component of impedance beginning to dominate.

Commentary by Dr. Valentin Fuster
2006;():493-500. doi:10.1115/IMECE2006-13941.

Nano-scale substrate cleanliness is an essential requirement in variety of nanotechnology applications. Currently, the detachment and removal of sub-100nm particles is of a particular interest and challenge in semiconductor manufacture, lithography, and nanotechnology. The proposed particle removal technique based on pressure shock waves generated by a laser induced plasma (LIP) core is of interest in various nano/micro fabrication applications in which the minimum feature size has been reducing rapidly. Any removal technique adopted in a fabrication process must be on the same shrinking feature reduction curve since, for device reliability, the minimum tolerable foreign particle size on a substrate depends on the minimum feature size on a nano/micro-system or device. In recent years, we have demonstrated that nanoparticles can be detached and removed from substrates using LIP shock wavefronts. While we have experimentally established the effectiveness of the LIP technique for removing nanoparticles in the sub-100nm range, the removal mechanisms were not well-understood. In the current work, we introduce a set of novel removal mechanisms based on moment resistance of the particle-substrate bond and discuss their effectiveness and applicability in laser-induced plasma shock nanoparticle removal. To gain better understanding for the detachment mechanisms, the resultant force and rolling moment induced on the nanoparticle by the LIP shockwave front need to be determined. Since, for sub-100nm nanoparticles, the Knudsen number Kn exceeds 0.1, the applicability of the Navier-Stokes equations for the gas motion becomes questionable as the continuum assumption for the medium breaks down due to the invalidity of the transport terms in these equations. Detachment and detachment mechanisms of nanoparticles from flat surfaces subjected to shockwaves are investigated by employing molecular gas dynamic simulations using the direct simulation Monte Carlo method and experimental transient pressure data. Two new mechanisms for nanoparticle detachment based on rolling moment resistance of the adhesion bond and the elastic restitution effect are introduced. As a result of present simulations, it is computationally demonstrated that the pulsed laser-induced shockwaves can generate sufficient rolling moments to detach sub-100nm particles and initiate removal. The transient moment exerted on a 60nm polystyrene latex (PSL) particle on a silicon substrate are presented and discussed.

Commentary by Dr. Valentin Fuster
2006;():501-508. doi:10.1115/IMECE2006-14351.

Many contemporary innovations in MEMS devices result from the miniaturization of existing macro-scale systems, exploiting changes in physical phenomena with scale. In terms of a system subject to mechanical stimuli, the response of the system changes significantly as scale decreases: in particular, natural frequencies increase and the system can sustain higher acceleration levels without damage. The objective of this paper is to investigate the response of a miniature scale cantilever beam to high-G impact stimuli in order to gain an understanding of its response. The test model is a machined aluminium cantilever-beam simply supported at one end. The beam cross section is 400 × 200 microns and has lengths of 4mm, 10mm and 20mm. The test bed is an Instron Dynatup 9250HV drop table. The beam response under impact is monitored using an IDT X-Stream XS-4 high-speed camera fitted with a telecentric 10x lenses. Theoretical and computer simulated models using ANSYS and LS-DYNA software are developed and compared with experimentally measured data to verify the accuracy of the techniques used to analyse the structural behaviour of the cantilever beams. The use of high-speed imaging when testing devices for short duration events proves to be beneficial for obtaining several data sets not achievable by post processing techniques.

Commentary by Dr. Valentin Fuster
2006;():509-510. doi:10.1115/IMECE2006-14631.

Microfluidic chips have made it possible to manipulate biological fluidic samples in increasingly smaller volumes—even enabling multiplexed study of individual cells. Performing biological assays using microfluidic technology not only makes them more portable when compared to their traditional counterparts, but also decreases testing time and cost. These biofluidic circuits vary widely in design and function: multiplexed cell electroporation, on-chip cell culturing, cell-cell communication monitoring, protein crystallization, and small volume sample analysis are only a few examples of potential applications. The rapid rate of growth and change in this field creates a need for inexpensive and flexible rapid prototyping of microfluidic chips.

Commentary by Dr. Valentin Fuster
2006;():511-516. doi:10.1115/IMECE2006-15836.

Micropost-filled reactors are commonly found in many micro total analysis system applications because of their high surface area for the surrounding volume. Design rules for micropost-filled reactors are presented here to optimize the performance of the micro-preconcentrator, which is a component of a micro gas chromatography system. The dimensionless figure of merit is proposed to be used to minimize the pressure drop while maximizing the surface-area-to-volume-ratio for a given overall channel geometry of the micropost-filled preconcentrator. Two independent models from the literature are used to predict the pressure drop across the micropost-filled channels for low Reynolds number flows. The pressure drop can be expressed solely as a function of a design parameter, β = a/s, a ratio of a radius of each post and a half-spacing between two adjacent posts. Pressure drop measurements are performed to experimentally corroborate the pressure drop model and the optimization using the dimensionless figure of merit. As the number of microposts; for a given β increases in a given channel size, a greater surface-area-to-volume-ratio will occur for a fixed pressure drop. Therefore, increasing the arrays of posts with smaller diameters and spacing will optimize the microreactor for higher surface area for a given flow resistance, at least until Knudsen flow begins to dominate.

Topics: Design , Pressure drop
Commentary by Dr. Valentin Fuster
2006;():517-524. doi:10.1115/IMECE2006-16197.

This paper presents a numerical study of 3-D movement of a conducting spherical droplet in magnetic levitation mechanism. At present, we not only investigate vertical and horizontal movements of the magnetically levitated droplet, but also self-rotation of the droplet. The hybrid 3-D boundary element method (BEM) and finite element method (FEM) with edge elements are used to calculate electromagnetic fields, Lorentz force, and torques with respect to vertical and horizontal axis. By this method, finite elements are used to discretize the spherical droplet region, while boundary elements are applied to free space outside the droplet. The finite element and boundary element regions are then coupled through interface boundary conditions. The coupling of FEM/BEM is solved iteratively. The computed results agree excellently with available analytical and numerical solutions. Furthermore, the complex 3-D movement of the magnetically levitated droplet is solved and analyzed by using the current FE/BE model.

Commentary by Dr. Valentin Fuster

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