0

ASME Conference Presenter Attendance Policy and Archival Proceedings

2011;():i. doi:10.1115/IPACK2011-NS1.
FREE TO VIEW

This online compilation of papers from the ASME 2011 Pacific Rim Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Systems (InterPACK2011) represents the archival version of the Conference Proceedings. According to ASME’s conference presenter attendance policy, if a paper is not presented at the Conference, the paper will not be published in the official archival Proceedings, which are registered with the Library of Congress and are submitted for abstracting and indexing. The paper also will not be published in the ASME Digital Library and may not be cited as a published paper.

Commentary by Dr. Valentin Fuster

Advanced Packaging

2011;():1-7. doi:10.1115/IPACK2011-52028.

Semiconductor Laser diodes that emit visible light have various interesting applications such as sensing, high density optical storage and projection displays. In any opto-electronic package, the laser diode chips are typically attached or soldered to metal or ceramic substrates that have good thermal conductivity and are well-matched in coefficient of thermal expansion using solder. Some applications require a critical alignment of the front facet of the laser diode to the front edge of the substrate onto which the laser diode chip is attached to. Depending on the application, the alignment precision could be varying from 20 μm to being as stringent as 0.5 to 1 μm. In many of these applications, the cost of packaging is also a very important factor. In such applications, it is essential to develop a laser diode chip bonding process that can meet such stringent die alignments along with a low cost manufacturing process. Therefore, the objective of this research work is to provide a low cost alternative solution for die attach process that can guarantee alignment precision of 0.5 to 1 microns and can be easily adapted to high volume manufacturing. The novel technique proposed in this work uses primarily gravity force for the facet alignments between the two components. In this passive-gravity assisted precision (P-GAP) assembly process, the laser diode (LD) chip is placed on the substrate using a traditional pick and place machine and later the substrate and the chip are tilted such that the chip slides on the substrate due to the gravity and touches a mechanical stop in-front of them. This does not involve any active alignment. In addition, we have provided few ideas to improve the sliding when gravity is used. This technique has been implemented on several samples and the feasibility of achieving the alignment precision to within a micron was demonstrated.

Commentary by Dr. Valentin Fuster
2011;():9-17. doi:10.1115/IPACK2011-52049.

There is a need for electromechanical devices capable of operating in high temperature environments (>200°C) for a wide variety of applications. Today’s wide-bandgap semiconductor based power electronics have demonstrated a potential of operating above 400°C, however they are still limited by packaging. Our group has been conducting research in novel interconnect technologies to develop reliable electronic packaging for high temperature environments. Among the most promising alternative is the Au-Sn eutectic solder (80 wt.% Au - 20 wt.% Sn), which have been widely used due to its excellent mechanical and thermal properties. However, the operating temperature of this metallurgical system is still limited to ∼250°C owing to its melting temperature of 280°C. Therefore, a higher temperature resistant system is much needed, but without affecting the current processing temperature of ∼325°C typically exhibited in most high temperature Pb-Free solders. This paper presents the development and characterization of a fluxless die attach soldering process based on gold enriched solid liquid inter-diffusion (SLID). A low melting point eutectic Au-Sn was deposited in the faces of two substrates, followed by the deposition of a subsequent layer of high melting point material, gold in this instance, in one of the substrates. Deposition of all materials was performed using Jet Vapor Deposition (JVD) equipment where thicknesses were controlled to achieve specific compositions in the mixture. Sandwiched coupons where isothermally processed in a vacuum reflow furnace. Scanning electron microscopy (SEM) was employed to reveal the microstructural evolution of the samples in order to study the interfacial reactions of this fluxless bonding process. EDS analysis was used to identify the intermetallic formation and to characterize the joint in an attempt to study the kinetics of this diffusion couple. Post-processed samples confirmed the inter-diffusion mechanism evidenced by the formation of sound joints between the two substrates. As expected, it was observed that the Au was dissolved into the eutectic Au-Sn as the reflow time and temperature were increased.

Commentary by Dr. Valentin Fuster
2011;():19-25. doi:10.1115/IPACK2011-52063.

Since the thickness of the stacked silicon chips in 3D integration has been thinned to less than 100 μm, the local thermal deformation of the chips has increased drastically because of the decrease of the flexural rigidity of the thinned chips. The clear periodic thermal deformation and thus, the thermal residual stress distribution appears in the stacked chips due to the periodic alignment of metallic bumps, and they deteriorate the reliability of products. In this paper, the dominant structural factors of the local residual stress in a silicon chip are discussed quantitatively based on the results of a three-dimensional finite element analysis and the measurement of the local residual stress in a chip using stress sensor chips. The piezoresistive strain gauges were embedded in the sensor chips. The length of each gauge was 2 μm, and an unit cell consisted of 4 gauges with different crystallographic directions. This alignment of strain gauges enables to measure the tensor component of three-dimensional stress fields separately. Test flip chip substrates were made by silicon chip on which the area-arrayed tin/copper bumps were electroplated. The width of a bump was fixed at 200 μm, and the bump pitch was varied from 400 μm to 1000 μm. The thickness of the copper layer was about 40 μm and that of tin layer was about 10 μm. This tin layer was used for the rigid joint formation by alloying with copper interconnection formed on a stress sensing chip. The measured amplitude of the residual stress increased from about 30 MPa to 250 MPa depending on the combination of materials such as bump, underfill, and interconnections. It was confirmed that both the material constant of underfill and the alignment structure of fine bumps are the dominant factors of the local deformation and stress of a silicon chip mounted on area-arrayed metallic bumps. It was also confirmed experimentally that both the hound’s-tooth alignment between a TSV (Through Silicon Via) and a bump and control of mechanical properties of electroplated copper thin films used for the TSV and bump is indispensable in order to minimize the packaging-induced stress in the three-dimensionally mounted chips. This test chip is very effective for evaluating the packaging-process induced stress in 3D stacked chips quantitatively.

Commentary by Dr. Valentin Fuster
2011;():27-33. doi:10.1115/IPACK2011-52113.

The thermal performance of an electronic device is heavily dependent on the properties of the printed circuit board (PCB) to which it is attached. However, even small variations in the process used to fabricate a PCB can have drastic effects on its thermal properties. Therefore, it is necessary to experimentally verify that each stage in the manufacturing process is producing the desired result. Steady state thermal resistance measurements, taken with a comparative cut bar apparatus based on ASTM D 5470-06, were used to compare PCBs manufactured from the same design by different vendors and the effects of vias filled with epoxy versus unfilled vias on the thermal resistance of a PCB. It was found that the thermal resistance of the PCBs varied by as much as 30% between vendors and that the PCBs with epoxy filled vias had a higher thermal resistance than those with unfilled vias, possibly due to the order in which the manufacturing steps were taken.

Commentary by Dr. Valentin Fuster
2011;():35-44. doi:10.1115/IPACK2011-52124.

This paper presents a CMOS stress sensor chip including arrays of piezoresistive sensor elements with high spatial resolution sensitive to the in-plane stress components σxx – σyy and σxy , to the out-of-plane stress σxz and σyz , and to the normal stress sum σΣ = (σxx + σyy )/2 − σzz . For the first time, an application of novel vertical stress sensors is presented, measuring the mechanical stress distributions below electroless nickel (eNi) bumps subject to lateral shear forces and vertical compression. All measured stress values are linearly proportional to the applied forces. The vertical shear stress sensors resolve residual vertical shear stresses of up to 51 MPa in the shear experiments. An adjustable numerical model is established assuming two different Young’s moduli of silicon nitride (SiN) emulating the adhesion between the SiN and eNi. Qualitative agreement of the in-plane stress distributions between experiment and numerical simulation is found in the shear and compression experiments, while good correlation for σΣ is found only for temperature uncompensated stress values in the compression test. The modeling of the absolute values shows differences to the experimental data of about ±30%.

Commentary by Dr. Valentin Fuster
2011;():45-51. doi:10.1115/IPACK2011-52154.

In recent years, the research and development of hybrid cars and electrical vehicles become one of the top targets. High electric power is necessary for those cars to run in motor drive, and power devices such as inverter are employed for the control. Since operative temperature of Si power device is from −40 to 150°C level, a big cooling system is needed to control the temperature lower than 150°C. Recently the SiC chip had been developed to downsize the cooling system and reduce the loss of energy, because the operative temperature of SiC chip can be increased to over 300°C. However mounting method that can be used at high temperature environment is not established yet. The author’s group has proposed a new mounting method using Ag-Nano material to mount the SiC chip on a metal board. In existing mounting method, stress was relieved by transformation of comparatively soft solder region. Thus, in the new method, the junction Ag-Nano is too hard to relax the stress. So stress relaxation facility is given to the pure aluminum substrate side. In addition, jointing Ag-Nano on aluminum board is not possible, enabled by Ag and Ni plating on substrate. And these films prevent aluminum board from oxidizing. This mounting method achieves low temperature mounting and high reliability in thermal cycle. In this study, reliability of Ni plating was investigated because it was brought out that Ni plating becomes as a new weak point during high temperature cycle test ranged from −40 to 300°C. Mechanical properties of Ni plating were investigated first. Test specimens with plating and without plating for four point bending test were prepared to compare the difference. And stress-strain relation of plating was evaluated. In addition, fatigue strength was investigated by cyclic bending test. With these material properties, fatigue life of Ni plating in packaging structure was evaluated by finite-element-analysis. And optimum dimension of the structure was studied.

Commentary by Dr. Valentin Fuster
2011;():53-63. doi:10.1115/IPACK2011-52189.

The significant roles of Cu-filled TSV passive interposers for 3D IC integration are investigated in this study. Emphasis is placed on the roles they play as: (1) substrates; (2) carriers; (3) thermal management tools; and (4) reliability buffers. It is shown that the Cu-filled TSV passive interposers are the most cost-effective integrator for 3D IC integration system-in-package (SiP).

Commentary by Dr. Valentin Fuster
2011;():65-73. doi:10.1115/IPACK2011-52205.

The effect of Cu-filled through-silicon vias (TSVs) interposers on the reliability of 3D IC integration system-in-package (SiP) is investigated in this study. Emphasis is placed on the determination of the stresses at the Cu-low-k pads on a Moore’s law chip and the creep strain energy density per cycle at the corner solder joints between the Moore’s law chip and an interposer. Also, thermal cycling tests and failure analysis results of a test vehicle is presented and discussed.

Topics: Reliability
Commentary by Dr. Valentin Fuster
2011;():75-82. doi:10.1115/IPACK2011-52264.

A thermo-mechanical analysis is carried out on a stacked die package having through silicon via technology to study the overall reliability of the package due to varying aspect ratio (size and shape) of through silicon vias, silicon die thickness, underfill thickness and underfill material properties. Through silicon via technology is one of the most rapidly developing technologies in the semiconductor industry and assures the development for the continued role of Moore’s law and multichip integration as well as packaging approaches. Wire bond and flip-chip have been in use for long time now while TSV is the latest technology of 3D integration system which is used for primary interconnection. The benefits of the use of TSV technology are increased performance, reduced form factor and cost reduction of the package. A three dimensional finite element model of a stacked package that consists of stacked dice using through silicon vias, solder interconnect, underfill, substrate and PWB is solved numerically to assess the reliability of the overall stacked package. In this analysis, stress free temperature for stacked package is kept at 125°C while room temperature is 25°C to carry out the simulation of the stresses post cure cool down of the stacked package. Stresses are calculated at the die as well as interfaces between underfill and die and underfill and substrate to assess the reliability of the overall package. A parametric study of critical geometric parameters such as aspect ratio, thickness of silicon die and underfill thickness and process parameters is carried out to minimize the maximum stresses on the overall stacked package. Recommendations are provided with respect to controlling the critical parameters such as aspect ratio, silicon thickness, underfill thickness and varying the underfill material properties (E and α) to improve the overall reliability and strength of the package.

Topics: Reliability , Design
Commentary by Dr. Valentin Fuster
2011;():83-89. doi:10.1115/IPACK2011-52286.

The pull force and displacement of gold (Au) and copper (Cu) wires in microelectronics are investigated in this study. Emphasis is placed on (1) the development of a set of equations for determining the internal forces and deformations of wires when subjected to an external pull force, (2) the determination of the maximum pull force (when the wire breaks) based on some failure criteria of the wires; and (3) the experimental verification of the present equations.

Topics: Reliability , Wire
Commentary by Dr. Valentin Fuster
2011;():91-93. doi:10.1115/IPACK2011-52289.

Hermetic sealing of lids in ceramic microelectronic chip carriers is typically performed with eutectic solder in relatively large belt-style reflow furnaces. This process is characterized by 30 to 45-minute cycle times at temperatures above 350 C. An experimental study was undertaken with the goal of establishing a low-cost lid sealing method marked by a compact belt furnace with lower reflow temperature and lesser cycle time. This is particularly advantageous for GaAs devices which are limited to packaging process temperatures below 300 C. A series of instrumented test samples consisting of a representative die packaged in a HTCC leadless chip carrier (LCC) was prepared. Package lids were installed and sealed in a nitrogen environment with 80–20 Au-Sn lead-free solder under various cycle time and temperature conditions. Gross and fine leak testing confirmed hermeticity. Results indicate that practical sealing can be realized in the compact furnace apparatus with measurable reductions in temperature and cycle time. Seal performance is dependent upon package orientation, which suggests the process must be calibrated for unique package designs. Sandia is a multiprogram laboratory operated by Sandia Corporation, a Lockheed Martin Company, for the United States Department of Energy’s National Nuclear Security Administration under Contract DE-AC04-94AL85000.

Commentary by Dr. Valentin Fuster
2011;():95-103. doi:10.1115/IPACK2011-52294.

A novel laser ultrasound and interferometer inspection system has been successfully applied to detect solder joint defects including missing, misaligned, open, and cracked solder bumps in flip chips, land grid array packages and chip capacitors. This system uses a pulsed Nd:YAG laser to induce ultrasound in the chip packages in the thermoelastic regime; it then measures the transient out-of-plane displacement response on the package surface using a laser interferometer. The quality of solder bumps is evaluated by analyzing the transient responses. In this paper, the application of this system is expanded to evaluate quality of lead-free solder bumps in ball grid array (BGA) packages; specifically BGA packages with poor wetting are used as test vehicles. Poor wetting not only decreases the mechanical strength of interconnection at the interface between the solder bumps and substrate, but also increases electrical resistance, which is a reliability issue. Causes of poor wetting vary from materials themselves to manufacturing process. Here, poor wetting of solder bumps were intentionally created by using an improper reflow profile. The transient out-of-plane displacement responses from these packages were compared with the responses from defect-free samples. Solder bumps with poor wetting were distinguished from the normal solder bumps by unusual correlation coefficient. Then, laser ultrasound inspection results are also compared with results from X-ray inspection and continuity test. Finally, the cross-section images were used to further confirm the existence of the poor wetting in samples with unusual correlation coefficient. It can be concluded that this laser-ultrasound system is capable of identifying the presence of poor wetting in BGA packages.

Commentary by Dr. Valentin Fuster
2011;():105-114. doi:10.1115/IPACK2011-52297.

Lithographically defined spring electrical contacts have many applications for next generation electronics test and packaging. The springs can lower the cost of multi-chip modules because their rework ability addresses the known-good-die problem. Lower height chip stacking for mobile electronics markets is enabled because a sliding spring can have a much shorter profile than solder. Larger die can be directly bonded to the board because the compliance absorbs thermal expansion mismatches between substrates. Significant stress isolation is possible, which is important for mechanically sensitive die such as MEMS and low K die. Very high density is possible, as 6 (am pitch has been demonstrated. Fabrication is scalable and assembly is low temperature. This paper reviews our prototype demonstrations for these applications as well as relevant reliability data and contact studies.

Topics: Packaging
Commentary by Dr. Valentin Fuster

Modeling and Simulation

2011;():115-122. doi:10.1115/IPACK2011-52034.

Synthetic jets are driven by a periodic electrical signal to generate pulsated airflow that can provide cooling to a hot surface. The working principle of synthetic jets involves conversion of electrical energy into mechanical and fluid energy. Piezoelectric actuators, comprising of a thin metal substrate bonded to a piezoelectric disk are induced to undergo vibration motion in bending mode by an AC sine-wave voltage with zero bias. Synthetic jets, which consist of two piezoelectric actuators separated by a compliant ring at the outer periphery of the actuators, undergo a bellow-like action due to the periodic motion of the actuators, thereby ingesting air and pushing air at high velocities through the orifice. In this paper, we seek to understand and quantify the efficiency of synthetic jets with a view towards optimizing their design. In this study, energy efficiency of synthetic jet is defined based on thermodynamics principles. Analytical equations for calculating consumed electric power and airflow power are derived. Using the derived equations, energy efficiency of synthetic jets is experimentally investigated. Air velocity at the jet orifice is measured using constant temperature hotwire anemometry. Voltage signal and resultant current waveform are recorded to calculate electric power. In order to understand the structural behavior, laser vibrometer is used to measure the center out-of-plane deflection of the piezoelectric synthetic jet. Electrical power input is varied by changing signal frequency and voltage amplitude. Synthetic jets with two different orifice sizes are tested, and the efficiency of energy conversion is determined. The effects of jet design and operation conditions on energy efficiency are discussed.

Commentary by Dr. Valentin Fuster
2011;():123-129. doi:10.1115/IPACK2011-52036.

Conflicting results in reliability tests for backward compatible and Pb-free soldered assemblies has motivated RoHS-exempted industries to practice reballing. Reballing is the name given to the process of removing Pb-free solder balls from the copper (Cu) pads of the Ball Grid Array (BGA) components received through the supply chain and replacing them with SnPb solder balls. Recent studies on the subject of reballing have shown the possibility that the removed Pb-free solder ball leaves behind some intermetallic remnants of the Pb-free solder alloy and the Cu from the pads. A modeling approach based on physics of failure (PoF) is presented that quantifies the interactions between different thermal cycles applied to reballed Ball Grid Arrays (BGA) with remnants of the Pb-free solder alloy on the Cu pads. These resulting interactions are compared to backward compatible Sn-3.8 Ag-0.7Cu (SAC) balls soldered with eutectic SnPb paste for the same thermal cycles. For the latter, the risk of having improper mixing during the assembly process is also studied. The approach is formulated at the microscale, incorporating physical mechanisms of the intermetallics created with Cu, and at the macroscale, capturing the creep phenomenon of the bulk solder as dominant failure driver. Simulation results show that the reballed cases have higher inelastic energy density per cycle averaged over damage volume near the copper pads and that the inelastic energy density is higher across the bulk of the improperly mixed backward compatible solder balls when compared to properly mixed backward compatible solder balls. The results of this study permit extrapolation of laboratory results to field life predictions and to explore the design of accelerated re-balled or backward compatible BGA tests that relate better to application-specific usage environments.

Commentary by Dr. Valentin Fuster
2011;():131-142. doi:10.1115/IPACK2011-52041.

The thermal and hydrodynamic performance of passive two-phase cooling devices such as heat pipes and vapor chambers is limited by the capabilities of the capillary wick structures employed. The desired characteristics of wick microstructures are high permeability, high wicking capability and large extended meniscus area that sustains thin-film evaporation. Choices of scale and porosity of wick structures lead to tradeoffs between the desired characteristics. In the present work, models are developed to predict the capillary pressure, permeability and thin-film evaporation rates of various micropillared geometries. Novel wicking geometries such as conical and pyramidal pillars on a surface are proposed which provide high permeability, good thermal contact with the substrate and large thin-film evaporation rates. A comparison between three different micropillared geometries — cylindrical, conical and pyramidal — is presented and compared to the performance of conventional sintered particle wicks. The present work demonstrates a basis for reverse-engineering wick microstructures that can provide superior performance in phase-change cooling devices.

Commentary by Dr. Valentin Fuster
2011;():143-148. doi:10.1115/IPACK2011-52044.

This paper proposes the high reliable design method for lead-free solder joint on metal substrate on chip component. First, the crack propagation analysis method for estimating rupture life of solder joint was constructed. And then, the effect of material properties of insulating layer on metal substrate and solder joint shape for rupture life of solder joint was evaluated using crack propagation analysis. As the result, the relation between young’s modulus of insulating layer and rupture life was indicated quantitatively. Also, the relation of filet length for rupture life of solder joint was evaluated. Secondary, evaluation method of heat dissipation for metal substrate was proposed. Because thermal conductivity of insulating layer affects temperature rise of heating device. And, the relation between thermal conductivity of insulating layer and temperature rise of heating device was indicated.

Commentary by Dr. Valentin Fuster
2011;():149-156. doi:10.1115/IPACK2011-52065.

Portable electric devices such as mobile phone and portable music player become compact and improve their performance. High-density packaging technology such as CSP (Chip Size Package) and Stacked-CSP is used for improving the performance of devices. CSP has a bonded structure composed of materials with different properties. A mismatch of material properties may cause stress singularity, which lead to the failure of bonding part in structures. In the present paper, stress analysis using boundary element method and an eigenvalue analysis using finite element method are used for evaluating the intensity of singularity at a vertex in three-dimensional joints. Three-dimensional boundary element program based on the fundamental solution for two-phase isotropic materials is used for calculating the stress distribution in a three-dimensional joint. Angular function in the singular stress field at the vertex in the three-dimensional joint is calculated using eigen vector determined from the eigenvalue analysis. The joining strength of interface in several kinds of sillicon-resin specimen with different triangular bonding areas is investigated analytically and experimentally. Experiment for debonding the interface in the joints is firstly carried out. Stress singularity analysis for the three-dimensional joints subjected to an external force for debonding the joints is secondly conducted. Combining results of the experiment and the analysis yields a final stress distribution for evaluating the strength of interface. Finally, a relationship of force for delamination in joints with different bonding areas is derived, and a critical value of the 3D intensity of singularity is determined.

Topics: Joining , Resins , Silicon
Commentary by Dr. Valentin Fuster
2011;():157-163. doi:10.1115/IPACK2011-52068.

For power module, the reliability evaluation of thermal fatigue life by power cycling has been prioritized as an important concern. Since in power cycling produces there exists non-uniform temperature distribution in the power module, coupled thermal-structure analysis is required to evaluate thermal fatigue mechanism. The thermal expansion difference between a Si chip and a substrate causes thermal fatigue. In this study, thermal fatigue life of solder joints on power module was evaluated. The finite element method (FEM) was used to evaluate temperature distribution induced by joule heating. Higher temperature appears below the Al wire because the electric current flows through the bonding Al wire. Coupled thermal-structure analysis is also required to evaluate the inelastic strain distribution. The damage of each part of solder joint can be calculated from equivalent inelastic strain range and crack propagation was simulated by deleting damaged elements step by step. The initial cracks were caused below the bonding Al wire and propagated concentrically under power cycling. There is the difference from environmental thermal cycling where the crack initiated at the edge of solder layer. In addition, in order to accurately evaluate the thermal fatigue life, the factors affecting the thermal fatigue life of solder joint where verified using coupled electrical-thermal-structural analysis. Then, the relation between the thermal fatigue life of solder joint and each factor is clarified. The precision evaluation for the thermal fatigue life of power module is improved.

Topics: Fatigue life
Commentary by Dr. Valentin Fuster
2011;():165-174. doi:10.1115/IPACK2011-52081.

Supercapacitors are a strong candidate for high-power applications such as electric/hybrid vehicles and electronic devices due to their high power densities and high efficiency particularly at low temperatures. In these applications, supercapacitors are used as energy-storage devices with capability of providing the peak-power requirement. They are subject to heavy duty cycling conditions which result in significant heat generation inside the supercapacitors. Therefore, thermal management is a key issue concerning lifetime and performance of supercapacitors. Accurate modeling of temperature field inside supercapacitors is essential for designing an appropriate cooling system, meeting the safety and reliability requirements of power systems. The objective of this paper is to study the transient and spatial temperature distribution in supercapacitors, in which a supercapacitor product with prismatic structure, based on the activated carbon and organic electrolyte technology, was chosen for modeling. A multi-dimensional thermal and electrochemical coupled model was developed by a commercial software COMSOL. In this approach, the 3D energy equation was coupled with a 1D electrochemical model via the heat generation and temperature-dependent physicochemical properties, including diffusion coefficient and ionic conductivity of electrolyte ions. Location-dependent convection and radiation boundary conditions were applied to reflect different heat dissipation phenomena of all surfaces. This model is capable of predicting electrochemical performance and temperature distribution for different involved parameters. The results of this model can also be used to determine the optimum thermal management system for various supercapacitor applications.

Commentary by Dr. Valentin Fuster
2011;():175-178. doi:10.1115/IPACK2011-52098.

The viscous effects on the band gap characteristics of the piezoelectric/viscous liquid phononic crystals are studied. The expressions of the generalized eigenvalue equation for the cylindrical phononic crystals are derived. Numerical calculations are performed to discuss the band gap characteristics with different filling ratios and viscous damping parameters. Form the results, it can be observed that the out-of-plane mode will appear, which caused by the viscous effects. Both of the real and imaginary parts of frequencies will increase with the filling fraction becoming larger. The maximum of the normalized band gap width is achieved by f = 0.5. Furthermore, the band gap edges become higher with the viscous damping parameter increasing, especially for higher band gaps.

Commentary by Dr. Valentin Fuster
2011;():179-184. doi:10.1115/IPACK2011-52100.

Ultrasonic flip chip bonding is one of the widely used methods in semiconductor chip or microsystem packaging and ultrasonic (US) bonding tool is important part for the bonding machine. To perform the proper operation of US bonding, the adequate vibration frequency and mode of US tool is required and the vibration design of the tool is very important. Until recent days, however, the most of practical aspect of the tool design follows the trial-and-error approach. In this study, we introduce the method of topology optimization for US bonding tools. The solid isotropic material with penalization (SIMP) method is used to formulate topology optimization and optimal criteria (OC) method is introduced for the update scheme. The objective resonance frequency and longitudinal mode is tracked using Modal Assurance Criterion (MAC). We compare between 2D and 3D finite element models, and realize two types of US tools which are based on 3D optimization results. To ensure the validity of topology optimization applied to the high frequency and tough devices such as US bonding tools, the vibration displacements at anti-nodal points of the optimized US tools are measured by laser vibrometer.

Commentary by Dr. Valentin Fuster
2011;():185-190. doi:10.1115/IPACK2011-52101.

Since the flexural rigidity of thin semiconductor package becomes much lower than normal components, the warpage of the component becomes a much more important issue to evaluate the reliability. In this study the author propose a new practical method to measure the real time curing deformation and the elastic modulus of the resin during the whole curing process. The thermal deformation of the resin under curing was measured by using the optical digital image correlation method. Next, to examine the mechanical properties of the resin, the liquid resin was poured into an aluminum frame with thin sole, and the bending rigid of the aluminum frame was measured by the three points bending test every minutes at the curing temperature of the resin. Based upon the experimented result, the warpage of a package caused of curing shrinkage was simulated.

Commentary by Dr. Valentin Fuster
2011;():191-194. doi:10.1115/IPACK2011-52105.

Recently, the downsizing of car components becomes a big trend for the development of car electronics, and it is becoming very difficult to achieve the reliability results target without managing controlling the dispersion of the fatigue lives. The authors proposed an isothermal fatigue test method using small size solder joints to get the fatigue properties. The Manson-Coffin’s law given by this method could improve the correspondence between the simulation results and experimental results. Based upon the Manson-Coffin’s law and Miner’s law, the authors proposed a fatigue crack propagation simulation approach. Furthermore, in order to consider the heterogeneity of PCB due to the distribution of fiber network, the authors made heterogeneous model considering the distribution of the fiber. And the authors evaluated the fatigue life of solder joints in chip components with considering dispersion of the material properties by using the heterogeneous model.

Commentary by Dr. Valentin Fuster
2011;():195-199. doi:10.1115/IPACK2011-52109.

On the reliability evaluation, the phenomenon of surface roughness on the Al surface of DBA (Direct Brazed Aluminum) on power device is confirmed. This surface roughness is generated by cyclic thermal stress under thermal cycle test. In this study, the surface roughness characteristic after thermal cycle test is executed to DBA substrate and the generating mechanism was investigated. Furthermore, the effect on the fatigue life of solder joint on DBA substrate is also investigated.

Commentary by Dr. Valentin Fuster
2011;():201-205. doi:10.1115/IPACK2011-52111.

Semiconductor component manufacturers supply to different product manufacturers in a wide range of market segments, for different end use applications. The goal of electronic component qualification is to demonstrate component reliability under operating conditions in the end product configuration. While a manufacturer may have successfully qualified an individual component, operating stresses due to surrounding components or the system can decrease individual component reliability. Not accounting for these operating stresses resulting from other components or the system will lead to lower life than anticipated. Using a case study, the authors demonstrate how the fatigue life of a chip component mounted on a PCB is affected by powered components on the board in close proximity.

Topics: Reliability
Commentary by Dr. Valentin Fuster
2011;():207-211. doi:10.1115/IPACK2011-52112.

Due to environmental concerns, Pb-free solders are widely used in electronic industry for assembling electronic components on the substrate. Under the various operation conditions, solder bumps are subjected to cyclic stress and failed by fatigue. To ensure the reliability of electronic products, it is becoming important to predict the fatigue failure of the Pb-free solder bumps. In this study, effects of chip size and thermal amplitude on fatigue life of the Pb-free solder bumps were investigated by experiments and elastic-plastic finite element analysis. A parameter, which is valuable to compare the fatigue damage of electronic packages with different chip size, is introduced.

Commentary by Dr. Valentin Fuster
2011;():213-224. doi:10.1115/IPACK2011-52133.

A major challenge in maintaining quality and reliability in today’s microelectronics devices comes from the ever increasing level of integration in the device fabrication as well as the high level of current densities that are carried through the microchip during operation. Cyclic thermal events during operation, stemming from Joule heating of the metal lines, can lead to fatigue failure due to the varying thermal expansion coefficients of the different materials that compose the microchip package. To aid in the avoidance of such device failures, it is imperative to develop a predictive capability for the thermal response of micro-electronic circuits. This work studied the problem of transient Joule heating in interconnects in a two-dimensional (2D) inhomogeneous system using a reduced order modeling approach of the Proper Orthogonal Decomposition (POD) method and Galerkin Projection Technique. This study considers an interconnect structure embedded in the bulk of a microelectronic device. The effect of different types of current pulses, pulse duration, and pulse amplitude were investigated. By using a representative step function as the heat source, the model predicted the exact transient thermal behavior of the system for all other cases without generating any new observations, using just a few POD modes. To validate this unique capability, the result of the POD model was compared with a finite element (FE) model developed in LS-DYNA®. The behaviors of the POD models were in good agreements with the corresponding FE models. This close correlation provides the capability of predicting other cases based on a smaller sample set which can significantly decrease the computational cost.

Commentary by Dr. Valentin Fuster
2011;():225-234. doi:10.1115/IPACK2011-52137.

The stacking of processing and memory components in a three-dimensional (3D) configuration enables the implementation of processing systems with small form factors. Such stacking shortens the interconnection length between processing and memory components to dramatically lower the memory access latencies, and contributes to significant improvements in the memory access bandwidth. Both of these factors elevate overall system performance to levels that are not realizable with prevailing and other proposed solutions. The shorter interconnection lengths in stacked architectures also enable the use of smaller drivers for the interconnections, which in turn reduces interconnection-level energy dissipations. On the down side, stacking of processing and memory components introduces a significant thermal management challenge that is rooted in the high thermal resistance of stacked designs. This paper examines and evaluates three distinct solutions that address thermal management challenges in a system that stacks DRAM components onto a processing core. We primarily focus on three different configurations of a microchannel-based single-phase liquid cooling system with a traditional air-cooled heat sink. Our evaluations, which are intended to study the limits of each solution, assume a uniform power dissipation model for the processor and accounts for the thermal resistance offered by the thermal interface material (TIM), the interconnect layer, and through-silicon vias (TSVs). The liquid-cooled microchannel heat sink shows more promising results when integrated into the package than when added to the microprocessor package from outside.

Commentary by Dr. Valentin Fuster
2011;():235-245. doi:10.1115/IPACK2011-52139.

Multicore microprocessor chips have emerged as an industry standard in recent years and have enabled Moore’s Law to be sustained when one considers the collective performance achieved by multiple cores. The industry has favored floor plans that use identical or symmetric layouts of individual cores in a linear array or a two-dimensional (2D) array, oblivious to the non-uniform heat dissipation within each core. Such non-uniform heat dissipations have hot spots within each core that must be aggressively cooled to avoid temporary or permanent device failures that can result from high temperature gradients. This paper evaluates alternative core layouts and microchannel configurations of a single-phase liquid cooling system for multi-core chips. We first examine the use of different planar flow patterns in microchannels for a realistic quad-core processor with non-uniform energy dissipation within each core. The direction of the flows in the microchannels is varied to achieve minimum hot spot temperatures on the die. A symmetric layout of the four cores with minimum achievable hot spot temperature is then selected and subjected to impingement flow. We establish the thermal efficiency of the optimized core floor plan compared to the traditional floor plan in a quad-core design and show that impingement provides the most efficient cooling solution compared to microchannels with planar flows for the same pressure difference.

Topics: Cooling
Commentary by Dr. Valentin Fuster
2011;():247-255. doi:10.1115/IPACK2011-52144.

Heat transfer in a thermally-positioned doubly-clamped bridge, at the micro- and nano-scale, is simulated to investigate the effect of convective cooling on the mechanical response of the system. The mechanical response of the system is defined as the displacement at the center of the bridge. The heat conduction equation is solved numerically using a finite difference method to obtain the temperature distribution in the bridge. Then, thermal stress due to the temperature difference with respect to the wall temperature is calculated. The thermo-structural equation is solved numerically to get the displacement along the beam. Two systems are compared: one doubly clamped beam with a length of 100 microns, a width of 10 microns, and a thickness of 3 microns, and a second beam with a length of 10 microns, a width of 1 micron, and a thickness of 300 nanometers, in air at a pressure from 0.01 Pa to 2 MPa. Conduction within the beam as well as convection between the beam and the gas are considered. A constant heat load with respect to the time is applied to the top of the beam varying from 10 to 600 μW/μm2 . The simulations use both free molecular and continuum models to define the convective coefficient, h. The simulations are performed for three different materials: silicon, silicon carbide, and diamond. The numerical results show that the displacement and the response of thermally-positioned nano-scale devices are strongly influenced by ambient cooling. The displacement depends on the material properties, the geometry of the beam, and the Biot number. In the free molecular model, the displacement varies significantly with the pressure at high Biot numbers, while it does not depend on cooling gas pressure in the continuum case. The significant variation of displacement starts at Biot number of 0.1 which occurs at gas pressure of 27 KPa in nano-scale. As the Biot number increases, the dimensionless displacement, δ* = δk/q αl2 decreases. The displacement of the system increases significantly as the bridge length increases, while these variations are negligible when the bridge width and thickness change. Thermal noise analysis shows silicon carbide has the most physically meaningful displacements in comparison with silicon and cvd diamond.

Commentary by Dr. Valentin Fuster
2011;():257-262. doi:10.1115/IPACK2011-52160.

Robot is an electromechanical device or machine which is controlled by computer or electronic programming to perform tasks automatically. Mobile robots in particular have become very popular and are used for numerous applications such as industries, military, factories and for performing many dangerous and inaccessible tasks. Robots generally vary in size from extremely small to large scales. Robot is a costly device and involves complex components / functionalities there by leading to immense heat dissipation. Thermal management of the robot holds the key which contains motor controllers that generate a tremendous amount of heat as it will affect its agility and mechanical reliability. This paper involves the design & cooling techniques of a quadruped robot.

Commentary by Dr. Valentin Fuster
2011;():263-269. doi:10.1115/IPACK2011-52170.

In this paper, motivated by a need to develop heat spreaders with post-containing (or nested channeled) configurations, we develop analytical models for the Squeeze Flow behavior of particle-filled Thermal Interface Materials (TIMs) between parallel plates and those with posts. The fluids are modeled as either Newtonian, or as Bingham fluids. The pressure distribution is analytically described for axisymmetric and non-axisymmetric configurations of fluids squeezed between parallel plates as well as for non-planar configurations with a cylindrical post at the center of one of the two circular plates. The developed analytical solutions to Newtonian behavior of the fluids are validated using squeeze flow models created in a commercial finite element code (COMSOL). The analysis for non-planar geometries is verified that as the post height is reduced to zero, the developed solution reduces to that of the parallel plate configuration. The influence of the height of the post on the force is systematically analyzed from which it is observed that the force required to compress the fluid increases with the post height. With increased post height, the force solution deviates by a greater amount from the parallel plate solution. The Bond-Line Thickness (BLT) of Newtonian and Bingham fluids contained within circular plates is determined. It is shown that materials with greater yield strength produce higher BLTs. The effect of backpressure is also shown to increase the BLT. Lastly, it is shown that as particles are added into the fluid, the effective viscosity increases and as a result a greater force is required to squeeze the fluid material.

Commentary by Dr. Valentin Fuster
2011;():271-279. doi:10.1115/IPACK2011-52181.

Heat sinks are used in modern electronic packaging system to enhance and sustain system thermal performance by dissipating heat away from IC components. Pin fins are commonly used in heat sink applications. Conventional metallic pins fins are efficient in low Biot number range whereas high thermal performance can be achieved in high Biot number regions with orthotropic composite pin fins due to their adjustable thermal properties. However, several challenges related to performance as well as manufacturing need to be addressed before they can be successfully implemented in a heat sink design. A heat sink assembly with metallic base plate and polymer composite pin fins is a solution to address manufacturing constraints. During the service life of an electronic packaging, the heat sink assembly is subjected to power cycles. Cyclic thermal stresses will be important at the pin-fin and base-plate interface due to thermal mismatch. The cyclic nature of stresses can lead to fatigue failure that will affect the reliability of the heat sink and electronic packaging. A finite element model of the heat sink is used to investigate the thermal stress cyclic effect on thermo-mechanical reliability performance. The aim is to assess the reliability performance of the epoxy bond at the polymer composite pin fins and metallic base plate interface in a heat-sink assembly.

Commentary by Dr. Valentin Fuster
2011;():281-297. doi:10.1115/IPACK2011-52196.

In this paper, fracture properties of Sn3Ag0.5Cu leadfree high strain-rate solder-copper interface have been evaluated and validated with those from experimental methods. Bi-material Copper-Solder specimen have been tested at strain rates typical of shock and vibration with impact-hammer tensile testing machine. Models for crack initiation and propagation have been developed using Line spring method and extended finite element method (XFEM). Critical stress intensity factor for Sn3Ag0.5Cu solder-copper interface have been extracted from line spring models. Displacements and derivatives of displacements have been measured at crack tip and near interface of bi-material specimen using high speed imaging in conjunction with digital image correlation. Specimens have been tested at strain rates of 20s−1 and 55s−1 and the event is monitored using high speed data acquisition system as well as high speed cameras with frame rates in the neighborhood of 300,000 fps. Previously the authors have applied the technique of XFEM and DIC for predicting failure location and to develop constitutive models in leaded and few leadfree solder alloys [Lall 2010a ]. The measured fracture properties have been applied to prediction of failure in ball-grid arrays subjected to high-g shock loading in the neighborhood of 12500g in JEDEC configuration. Prediction of fracture in board assemblies using explicit finite element full-field models of board assemblies under transient-shock is new. Stress intensity factor at Copper pad and bulk solder interface is also evaluated in ball grid array packages.

Topics: Alloys , Springs
Commentary by Dr. Valentin Fuster
2011;():299-305. doi:10.1115/IPACK2011-52200.

3D or stacked-die packages are becoming increasingly popular in the electronic packaging industry because of the current market demand for cheaper and smaller products with high performance characteristics. As a result, the IC silicon wafers have to be grinded through wafer-thinning processes to achieve greater packaging density. However, it is possible to induce crack of the chips during stacking process or in the use of the device. Therefore, this study aims to determine the die strength of (1 0 0) silicon which can provide to designers for reliability of the die. Several methods have already been adopted to determine the strength of silicon die. These methods include three-point bending test (3PB), four-point bending test (4PB) and ball-breaker test. However, 3PB and 4PB have difficulty for application not only in experiment set ups and silicon die sample preparation aspects but also in actual use because of their sensitivity to both edge and surface defects. Therefore, the ball-breaker test is then proposed in this study to measure the maximum allowable force of silicon die. Meanwhile, comparing with experiment data, the finite element method (FEM) analysis using commercial software ANSYS/LSDYNA3D® are introduced to determine the silicon die strength. Moreover, the 3D model of the ball-breaker test is verified through the Hertzian contact theory. The effect of the thickness on silicon die strength and the failure modes are also discussed in this study. As the applied force increases, the crack appears on the edge of the contact area on the top surface and flare out within the die. However, the radial crack occurs on the bottom surface while the bending effect on the bottom side of the test die has become significant as the die thickness decreases. The early failure may occur at the position and then crack through the top surface causing the die breakage. In other words, the determined strength in this experiment decreases as the thickness of test die becomes increasingly thin. Furthermore, the simulation results show that the allowable force of silicon dies increases as the softer foundation material is applied while the bending behavior is not significant. However, the breakage of the thinner test die placed on the softer material is much easier to happen because the tensile stress on the bottom surface resulting from the bending behavior increases rapidly and significantly influences the die breakage.

Topics: Silicon
Commentary by Dr. Valentin Fuster
2011;():307-316. doi:10.1115/IPACK2011-52233.

Since the introduction of Cu/low-k as the interconnect material, the chip-package interaction (CPI) has become a critical reliability challenge for flip chip packages. Revision of underfill material must be considered, which may compromise the life of flipchip interconnect by releasing the stresses transferred to the silicon devices from the solder bumps, and thereby maintain the overall package reliability. Thus, it is important to understand the thermo-mechanical behavior of solder bumps. In this study, the solder bump reliability in flip chip package was investigated through an experimental technique and numerical analysis. For the experimental assessment, thermo-mechanical behavior of solder joints, especially the solder bumps located at the chip corners where most failures usually occur was investigated. Digital Image Correlation (DIC) technique with optical microscope was utilized to quantify the deformation behavior and strains of a solder bump of flip-chip package subjected to thermal loading from 25°C to 100°C. As a specimen preparation for DIC technique, a flip-chip specimen was cross-sectioned before a manual polishing process followed by wet etching method in order to generate natural speckle patterns with high enough contrast on the measuring surface. Finally, finite element analysis (FEA) was conducted by simulating the thermal loading applied in the experiments, and validated with experimental results. Then, using the FEA analysis, parametric study for underfill material properties were performed on the reliability of flip chip package, by varying the glass transition temperature (Tg), Young’s modulus (E), and coefficient of thermal expansion (CTE). Averaged plastic work of the corner solder bump and stress at the die side were obtained and used as damage indicators for solder bumps and low-k dielectrics layer, respectively. The results show that high Tg, and E of underfill are generally desirable to improve the reliability of solder interconnects in the flip chip package.

Commentary by Dr. Valentin Fuster
2011;():317-323. doi:10.1115/IPACK2011-52237.

The trend towards decreasing dielectric constant of Interlayer Dielectric (ILD) materials has required significant trade-off between electrical performance and mechanical integrity of the die stack. Fracture caused by thermal stresses due to large coefficient of thermal expansion (CTE) mismatch between these materials arising during fabrication or testing are often the main driving force for failure. In this paper, we use CAD-inspired hierarchical field compositions [1] to carry out Isogeometric (meshfree) fracture simulations. We model cracks as arbitrary curves/surfaces and the crack propagation criterion is based on the evolving energy release rate (ERR) of the system. We simulate the solder reflow process to assess the impact of chip-package interaction on the reliability of ILD stacks. We use multi-level modeling to extract displacement boundary conditions for the local model of the ILD stack. Eight layers of metallization are considered in the ILD stack. We study the relative risks of replacing stronger dielectric (SiO2) with weaker dielectrics (SiCOH, ULK) on the criticality of preexisting flaws in the structure. Further, we study the impact of varying interfacial toughness values on the crack growth patterns in ILD stacks. Crack patterns reflect the propensity towards predominantly bulk failure with increasing interfacial toughness.

Commentary by Dr. Valentin Fuster
2011;():325-328. doi:10.1115/IPACK2011-52241.

Thermal conduction and mechanical strength around TSV (Through Silicon Via) structures of 3D SiP (Three Dimensional System in Package) were discussed both cases of with and without void in TSV by using a large scale simulator based on FEM, ADVENTURECluster® for ensuring the reliability of 3D SiP. In the results, the thermal performance that was required in 3D SiP was estimated to ensure the reliability. Simulations for thermal stresses around TSV structure in 3D SiP under thermal cycle condition due to power ON/OFF were carried out. In case that void was not in TSV, stresses in TSV were close to hydrostatic pressure and the magnitude of the equivalent stress was lower than the yield stress of copper. However, the level of the stresses, especially in Si chips, should not be negligible in inducing damages to TSVs and Si single crystals. In case that void was in TSV, stress was concentrated around void in TSV and the magnitude of the equivalent stress was lower than the yield stress of copper. The level of stresses applied to Si chip was slightly reduced due to void in TSV. However, its level should not be negligible in inducing damages to TSVs and Si single crystals.

Commentary by Dr. Valentin Fuster
2011;():329-343. doi:10.1115/IPACK2011-52243.

This paper examines the thermodynamic and thermal transport properties of the 2D graphene lattice. The interatomic interactions are modeled using the Tersoff interatomic potential and are used to evaluate phonon dispersion curves, density of states and thermodynamic properties of graphene as functions of temperature. Perturbation theory is applied to calculate the transition probabilities for three-phonon scattering. The matrix elements of the perturbing Hamiltonian are calculated using the anharmonic interatomic force constants obtained from the interatomic potential as well. An algorithm to accurately quantify the contours of energy balance for three-phonon scattering events is presented and applied to calculate the net transition probability from a given phonon mode. Under the linear approximation, the Boltzmann transport equation (BTE) is applied to compute the thermal conductivity of graphene, giving spectral and polarization-resolved information. Predictions of thermal conductivity for a wide range of parameters elucidate the behavior of diffusive phonon transport. The complete spectral detail of selection rules, important phonon scattering pathways, and phonon relaxation times in graphene are provided, contrasting graphene with other materials, along with implications for graphene electronics. We also highlight the specific scattering processes that are important in Raman spectroscopy based measurements of graphene thermal conductivity, and provide a plausible explanation for the observed dependence on laser spot size.

Commentary by Dr. Valentin Fuster
2011;():345-350. doi:10.1115/IPACK2011-52247.

Power devices are used in inverters in a variety of electrical equipment, for instance, hybrid-power cars, electric vehicles, and generators. These types of equipment are used to decrease the negative impact on the environment, and thus, the power devices need to function effectively as electric power converters for the long-term stability of the equipment. In short, the long-term reliability, i.e., the life, of the power device is important, and a high level of reliability is required. In the development process of power devices, it is necessary to conduct thermal fatigue tests to evaluate the reliability. However, such tests are extended over a long period of time, which makes it difficult to shorten the development period. Therefore, a simulation technique needs to be developed to forecast the life of a thermal fatigue test in order to reduce the development period. During the thermal fatigue test, thermal stress is caused by differences in the line expansion coefficient between solder joint materials. Thermal stress causes crack generation and propagation in solder. The thermal resistance of a device increases steadily as the cracks grow. This raises the temperature of the device and increases thermal stress. As a result, crack propagation is accelerated. However, conventional crack propagation analysis does not take this phenomenon into account. We developed a method of crack propagation analysis that takes into account the changes in thermal and electrical boundary conditions resulting from the crack propagation. The method is a combination of electrical conduction analysis, heat transfer analysis, and crack propagation analysis. The boundary condition of the heat transfer analysis is determined from the results of the electrical conduction analysis. The boundary condition of the crack propagation analysis is determined from the results of the heat transfer analysis. The crack propagation behavior in solder is calculated by repeating these analyses. This method reproduces the drastic increase in thermal resistance in the latter part of the thermal fatigue test, and the results agree well with the experimental results. We confirmed that the temperature distribution of the device changes as the crack propagates and that thermal and electrical coupled analysis has a major effect on the prediction of fatigue life of power device products. We also revealed that the thermal fatigue life is affected by the position of the heat source and cracks.

Commentary by Dr. Valentin Fuster
2011;():351-356. doi:10.1115/IPACK2011-52258.

The risk of fracture in Interlayer Dielectric (ILD) stack is evaluated for various configurations of flip-chip packages in this paper. A novel analysis on the mechanical behavior of package with a focus on die surface provides the insights into the critical deformation state as well as its location. In Controlled Collapse Chip Connection (C4) process, the reflow phase involves a cooling of the entire package from the reflow temperature to room temperature, and is critical for package induced die cracking (Chip-Package Interaction or CPI). We use commercial finite element software ABAQUS to construct local sub-models of ILD region from global models of a representative 3-D package with component materials modeled as being temperature dependent elastic or elasto-plastic as appropriate. The risk of ILD fracture is systematically investigated using the described approach.

Commentary by Dr. Valentin Fuster
2011;():357-359. doi:10.1115/IPACK2011-52283.

Atomistic analyses of thermal conduction across ZrB2 /SiC based nanocomposite interface are performed using first principles density functional theory (DFT) with plane-wave basis sets. The changes in the thermal properties of nanocomposites have been analyzed under the effect of straining and temperature and compared for their phononic and electronic dependence.

Commentary by Dr. Valentin Fuster
2011;():361-367. doi:10.1115/IPACK2011-52284.

Nanoscale engineered materials with tailored thermal properties are desirable for applications such as highly efficient thermoelectric, microelectronic and optoelectronic devices. It has been shown earlier that by judiciously varying interface thermal boundary resistance (TBR) thermal conductivity in nanostructures could be controlled. Two types of nanostructures that have gained significant attention owing to the presence of TBR are superlattices and nanocomposites. A systematic comparison of thermal behavior of superlattices and nanocomposites considering their characteristic structural factors such as periodicity and period length for superlattices, and morphology for nanocomposites, under different extents of straining at a range of temperatures remains to be performed. In this presented work, such analyses are performed for a set of Si-Ge superlattices and Si-Ge biomimetic nanocomposites using non-equilibrium molecular dynamics (NEMD) simulations at three different temperatures (400 K, 600 K, and 800 K) and at strain levels varying between −10% and 10%. The analysis of interface TBR contradicts the usual notion that each interface contributes equally to the heat transfer resistance in a layered structure. The dependence of thermal conductivity of superlattice on the direction of heat flow gives it a characteristic somewhat similar to a thermal diode as found in this study. The comparison of thermal behavior of superlattices and nanocomposites indicate that the nanoscale morphology differences between the superlattices and the nanocomposites lead to a striking contrast in the phonon spectral density, interfacial thermal boundary resistance, and thermal conductivity. Both compressive and tensile strains are observed to be important factors in tailoring the thermal conductivity of the analyzed superlattices, whereas have very insignificant influence on the thermal conductivity of the analyzed nanocomposites.

Commentary by Dr. Valentin Fuster

MEMS, NEMS

2011;():369-374. doi:10.1115/IPACK2011-52002.

Microphone is a critical component for seamless communication converting an acoustic signal (vocal) to an electrical signal. Traditionally Electrets Condenser Microphones (ECM) have been the primary proponent of audio component in many consumer products. With functionally rich consumer devices (example smart phones, etc) there is a growing trend to look at components with higher functionality but a smaller form factor. Microelectronic Mechanical Systems (MEMS) microphone is seen as a possible replacement to ECM due to its significant reduction in form fit with additional functionality. The paper is an effort to illustrate steps that can be considered while designing MEMS microphone in a system. This includes Design considerations, Reliability tests, Manufacturing challenges and Readiness to ensure higher yield during the final assembly. Manufacturing issues (Top 5) and guideline presented in the paper are not just to increase the assembly yield (system level), but also to increase an awareness upfront to the design phase to help create a robust system/product.

Commentary by Dr. Valentin Fuster
2011;():375-379. doi:10.1115/IPACK2011-52038.

We present the design and fabrication of a microchip capable of performing mechanical (tensile, fracture, fatigue), electrical (conductivity and band gap) and thermal (conductivity and specific heat) characterization of materials and interfaces. The chip can study thin films and wires of any material that can be deposited on a substrate or study thin coupons if the specimen is in bulk form. The 3 mm × 3 mm size of the chip results in the unique capability of in-situ testing in analytical chambers such as the transmission electron microscope. The basic concept is to ’see’ the micro-mechanisms while ‘measuring’ the deformation and transport properties of materials and interfaces. The advantage of such simultaneous acquisition of quantitative and qualitative data is the accurate and quick physics-based modeling of materials behavior. We present preliminary studies on multi-physics, or the coupling among mechanical thermal and electrical domains in materials will be presented. These results are particularly important when the specimen dimension becomes comparable to the mean free paths of electron and phonons.

Commentary by Dr. Valentin Fuster
2011;():381-386. doi:10.1115/IPACK2011-52062.

A new highly sensitive strain measurement method has been developed by applying the change of the electronic conductivity of CNTs. It is reported that most multi-walled carbon nanotubes (MWCNTs) show metallic conductivity and they are rather cheap comparing with single-walled carbon nanotubes (SWCNTs). The effect of the longitudinal axial strain on the band structures of electrons in CNTs was analyzed by applying the abinitio calculation based on the density functional theory. The change of the band structure of a MWCNT under uni-axial strain was analyzed. It was found that the electric conductivity of (MWCNTs) changes drastically because of the large change of their band gap. Therefore, the authors have focused on the possibility of the application of MWCNTs to a highly sensitive strain sensor. Multi-walled CNTs were dispersed in various kinds of resins such as epoxy, polycarbonate, and polyisoprene to form a thin film which can be easily attached to rounded surfaces. The length and diameter of the CNTs were about 5 μm and 50 nm, respectively. One of the base materials of resin employed was polycarbonate and the volumetric concentration of CNT dispersed was about 11.5%. The thickness of the film was about 500 μm. Uni-axial strain was applied to the CNT-dispersed resin by applying a 4 point bending method, and the change of the electric resistance was measured. The range of the applied strain was from −0.025% to 0.025%. The electric resistance changed almost linearly with the applied strain. The ratio of the resistance change under the tensile strain was about 400%/%strain and that under the compressive strain was about 150%/%strain. The CNTs were also dispersed in polyisoprene by about 5%. Uni-axial tesile strain was also applied to the CNT-dispersed rubber. The maximum strain was 240%. It was found that the resistance of the rubber increased monotonically with the increase of the amplitude of the applied strain. The increase rate also increased with the amplitude of the applied strain, and the maximum rate reached about 25%/%strain. Two-dimensional strain fields were evaluated by using finely area-arrayed CNT-dispersed resin made by MEMS technology with spatial resolution of 50 μm.

Topics: Sensors , Carbon , Nanotubes , Resins
Commentary by Dr. Valentin Fuster
2011;():387-393. doi:10.1115/IPACK2011-52074.

This paper presents the design, fabrication, and experimental results of a multiple-beam tuning-fork gyroscope (MB-TFG). Based on a numerical model of thermoelastic damping, a multiple-beam tuning-fork structure is designed with high Quality factors (Qs) in its two operation modes. A simple mask that defines the device through trenches is employed to implement this MB-TFG design on silicon-on-insulator wafers. The highest measured Qs of the fabricated MB-TFGs in vacuum are 255,000 in the drive-mode and 103,000 in the sense-mode, at a frequency of 15.7kHz. Under a frequency difference of 4Hz between the two modes (operation frequency is 16.8kHz) and a drive-mode vibration amplitude of 3.0μm, the measured rate sensitivity is 80μVPP /°/s with an equivalent impedance of 2.5MΩ. The calculated overall rate resolution of this device is 0.377hr°/√Hz.

Topics: Design
Commentary by Dr. Valentin Fuster
2011;():395-399. doi:10.1115/IPACK2011-52183.

Reliability and long term stability are the greatest challenges for commercialization of MEMS gyroscopes. Their vast use in different applications that required MEMS gyroscopes to function from medium to harsh environments make necessary to evaluate the performance of MEMS gyroscope under those conditions. This paper focuses on the combined long term effects of temperature and humidity on the performance of MEMS vibratory gyroscope. Performance of the MEMS gyroscope was evaluated over time by conducting temperature humidity bias (THB) test on a COTS (commercial off-the-shelf) single axis MEMS vibratory gyroscope having an operating temperature range from −40°C to +85°C. The gyroscope sensors were exposed to 60°C and 90%RH (Relative Humidity) for 500 hours. Six single axis gyroscopes were tested, three with in-situ device calibration and three without in-situ device calibration. Out of three MEMS vibratory gyroscopes tested without in-situ device calibration, it was observed that samples had minimum and maximum in-situ zero rate output (ZRO) drift of 1.3°/s and 2.2°/s respectively over 500 hours. These drifts were disappeared when gyroscope sensors were tested after six months by keeping at room condition. Other three single axis gyroscopes were tested in the same chamber with in-situ device calibration which didn’t show any major performance ZRO drift.

Commentary by Dr. Valentin Fuster
2011;():401-407. doi:10.1115/IPACK2011-52201.

The characteristic of MEMS component is affected by different process procedures such as depositing and etching thin films on substrate. These processes might induce residual stresses or deformations in MEMS component, which will reduce its efficiency and quality, and it is very unfavorable in MEMS development. This study develops a methodology that uses Finite Element Analysis (FEA) along with process modeling technology to analyze the residual stress in a MEMS microphone structure. The residual stress of thin film is composed of thermal and intrinsic stress. The thermal stress can be obtained directly in FEA but not for the intrinsic stress, which is a process-dependent material property. The intrinsic stress in multilayered structure is obtained from Stoney’s experiment which measures the curvature on blanket wafer after each process. A comparison of the experimental and simulated results showed that dislocation induced intrinsic stress in aluminum can be rearrangement after first annealing. The lattice mismatch induced intrinsic stress, however, will influence the residual stress of the aluminum film when its thickness is under 1μm. The residual stresses and the deformations in two electrode plates are presented for the process simulation in the MEMS microphone. The polysilicon would buckle and warp downward if it is subjected to compressive stress. However, the polysilicon diaphragm would be flat in the positive intrinsic stress.

Commentary by Dr. Valentin Fuster
2011;():409-415. doi:10.1115/IPACK2011-52250.

The fracture and fatigue behaviors of polysilicon thin film structures with arbitrary shapes were formulated by taking the stress distribution into account. The parameters appearing in both Weibull distribution and Paris’ law that describe the static strength and fatigue behaviors, respectively, are estimated using the maximum likelihood method on the basis of the results of tensile static fracture and fatigue tests performed on two types of polysilicon thin film specimens with different shapes fabricated using the same conditions. The difference between the fatigue lifetime distributions between the two types was well explained by applying the formula with a unique set of parameters. These results suggest that the fracture and fatigue behaviors of polysilicon thin films have a unique characteristics regardless of stress distributions.

Commentary by Dr. Valentin Fuster
2011;():417-424. doi:10.1115/IPACK2011-52259.

An ionic polymer-metal composite (IPMC) consisting of a thin perfuorinated ionomer membrane, electrodes plated on both faces, undergoes large bending motion when a small electric field is applied across its thickness in a hydrated state. On the other hand, when small load is applied on IPMC, the electric field is induced in the polymer membrane depending on the magnitude of loading. The characteristics of IPMC are ease of miniaturization, low density and mechanical flexibility. Therefore, it is considered to have a wide range of applications from MEMS sensors to actuators. In this paper, we developed the fabrication process of IPMC actuator with palladium electrodes, which have lower stiffness than the conventional IPMC actuator with Au or Pt electrodes. The deformation of IPMC actuator is evaluated under various solvents, various temperatures, and various frequencies of input voltages. We developed the numerical model of IPMC actuator that can change the solution temperature and the ion species and compared the simulation results to the experimental results.

Commentary by Dr. Valentin Fuster
2011;():425-428. doi:10.1115/IPACK2011-52270.

Capability of detecting local interface strength variation with 10 ! m scale resolution was investigated in reference to the interface between vapor-deposited gold (Au) and SiO2 with a practically homogeneous strength. Uncertainties in the evaluation procedure were thoroughly examined, which was to be excluded from the apparent scatter of evaluation results. The intrinsic scatter of strength in a damascene Cu/SiN cap interface was successfully specified to be at least 2.45 J/m2 .

Commentary by Dr. Valentin Fuster
2011;():429-436. doi:10.1115/IPACK2011-52290.

The concept of micro-electro-mechanical systems (MEMS) sensors directly fabricated on a ceramic substrate, which can be used for a package of end product, was proposed. As demonstrations of the sensors directly fabricated on a ceramic package, an accelerometer and a magnetoresistive (MR) sensor are focused on, and their fabrications on a ceramic substrate is investigated. The accelerometer utilizes a fringe capacitance formed in a ferroelectric material. For this sensor, in stead of a previously used bulk PZT plate, a screen-printed BaTiO3 (BTO) film on a ceramic alumina substrate was herein employed. An accelerometer using a BTO film was practically fabricated. The sensitivity of it was estimated as 0.1 pF/g, which is degraded a little compare with the previously developed accelerometer using a PZT plate; however, the order is the same. The magnetoresistive (MR) sensor can detect not only x- and y-axes magnetic field intensities but also z-axis one, where all fields are based on the sensor coordinate system. Namely, not only azimuth but also angle of elevation of the sensor can be detected from triaxis components of geomagnetic field. The principle is as follows: a permalloy (FeNi) plate is stood aside MR element. The plate distorts magnetic field and generates x- (or y-) component from originally z-directional field. So, the resistance of MR element changes in proportional to z-axis field intensity, provided that other axes intensities are kept constant.

Commentary by Dr. Valentin Fuster
2011;():437-441. doi:10.1115/IPACK2011-52293.

Macrofiber piezoelectric composites are thin rectangular patches made of polyimide film, epoxy and a single layer of rectangular lead zirconium titanate fibers and are commercially available. As a basis for this consideration, the useful life of the MFC is being characterized to determine the effect of loading condition on the performance of the material as it is fatigued by cyclical piezoelectric excitation. The test specimen consists of the MFC laminated to a cantilevered stainless steel beam using epoxy and is actuated at the first resonant frequency of the beam laminate by the cyclic application of 1000 volts. Strain and beam tip displacement measurements are used as a basis for determining the performance of the MFC as it is cyclically actuated under varying beam thicknesses.

Commentary by Dr. Valentin Fuster

Multi Physics Based Reliability

2011;():443-451. doi:10.1115/IPACK2011-52047.

The reliability or lifetime of micro-joints on printed circuit boards (PCBs) is significantly affected by fatigue processes, including fatigue crack initiation and propagation to failure. Accordingly, the industries producing electronic devices and components strongly desire a new nondestructive inspection technology, which detects micro-cracks appearing as thermal fatigue fractures in the joints. In this investigation, we applied a synchrotron radiation X-ray micro-tomography system called the SP-μCT to three-dimensionally and nondestructively evaluate the fatigue crack propagation process in complex-shaped solder joints. The observed specimens have a typical joint structure in which chip type resistors 1.0 mm in length and 0.5 mm in width are mounted on an FR-4 substrate by joining with Sn-3.0Ag-0.5Cu solder. A thermal cycle test was carried out, and specimens were collected at fixed cycle numbers. The same solder joints were observed successively using the SP-μCT at beamline BL20XU at SPring-8, the largest synchrotron radiation facility in Japan. An X-ray energy of 29.0 keV was selected to obtain computed tomography (CT) images with high contrast among some components, and a refraction-contrast imaging technique was also applied to the visualization of fatigue cracks in the solder joints. The following results were obtained. At the early stage in the fatigue process of normal joints, the main fatigue cracks were clearly observed to initiate from the region around the solder joint tip and the vicinity of the chip corner. Additionally, many micro-cracks roughly 5 to 10 μm in length also formed in the thin solder layer between the chip and substrate. The important observed fact is that these micro-cracks deform, grow, and connect to each other due to the thermal cyclic loading, prior to main crack propagation. On the other hand, in case of solder joints which included relatively larger initial voids, the voids deformed, and the fatigue cracks initiated and propagated from the surface of the voids. Furthermore, by employing the three-dimensional crack images, the crack dimensions were quantified straightforwardly by measuring the surface area of the fatigue crack, and the fatigue crack propagation process was also accurately evaluated via the average crack propagation rate. Consequently, the obtained CT images clearly illustrate the process of crack propagation due to the thermal cyclic loading of a solder joint. In contrast, such information has not been obtained in any form by industrially employed X-ray CT systems or finite element analyses.

Commentary by Dr. Valentin Fuster
2011;():453-456. doi:10.1115/IPACK2011-52052.

A study of NiFe alloy as under bump metallurgy (UBM) for Pb-free interconnect has been performed. Intermetallic growth rate of NiFe and SnAg solder is about 10x slower than that of Ni and SnAg solder. The thin and uniform intermetallic compound FeSn2 showed excellent thermal and electromigration stability. By slowing down or stopping the UBM dissolution, NiFe effectively eliminated the early EM fails that are common with Ni UBM. NiFe is an interesting candidate for the chip and substrate surface metallurgy of Pb-free interconnects for high power applications.

Commentary by Dr. Valentin Fuster
2011;():457-462. doi:10.1115/IPACK2011-52057.

In this study, the change of the resistivity of carbon nanotubes and graphene sheets under strain was analyzed by applying a quantum chemical molecular dynamics analysis and the first principle calculation. Various combinations of double-walled carbon nanotube structures were modeled for the analysis. The change of the band structure was calculated by changing the amplitude of the applied strain. It was found in some cases that the band structure changes drastically from metallic band structure to semiconductive one, and this result clearly indicated that the electronic conductivity of the MWCNT decreased significantly in a three-dimensional strain field. It was also found that there is a critical strain at which the electronic band structure changes from metallic to semiconductive and vice versa. This result indicated that the metallic CNT changes a semiconductive CNT depending on the applied strain field. The effect of the diameter of the zigzag type CNT on the critical strain of buckling deformation was analyzed under uni-axial strain. In this analysis, the aspect ratio of each structure was fixed at 10. It was found that the critical strain decreased monotonically with the decrease of the diameter. This was because that the flexural rigidity of a cylinder decreased with the decrease of its diameter when the thickness of the wall of the cylinder was fixed. It was found that the critical strain decreased drastically from about 5% to 0.5% when the aspect ratio was changed from 10 to 30. Since the typical aspect ratio of CNTs often exceeds 1000, most CNTs should show buckling deformation when an axial compressive strain is applied to the CNTs. Finally, the shape of a six-membered ring of the CNT was found to be the dominant factor that determines the electronic band structure of a CNT. The change of the band structure of a grapheme sheet was analyzed by applying the abinitio calculation based on density functional theory. It was found that the fluctuation of the atomic distance among the six-membered ring is the most dominant factor of the electronic band structure. When the fluctuation exceeded about 10%, band gap appeared in the deformed six-membered ring, and thus, the electronic conductivity of the grapheme sheet change from metallic one to semiconductive one. It is therefore, possible to predict the change of the electronic conductivity of a CNT by considering the local shape of a six-membered ring in the deformed CNT.

Commentary by Dr. Valentin Fuster
2011;():463-471. doi:10.1115/IPACK2011-52073.

A corner of bonded dissimilar materials is one of the main causes of the failure of electronic packages or MEMS structures. These materials are sometimes anisotropic materials and piezoelectric materials. To evaluate the integrity of a corner of bonded piezoelectric materials is useful for the reliability of electronic packages and MEMS. Asymptotic solutions around the interfacial corner between piezoelectric bimaterials can be obtained by the combination of the Stroh formalism and the Williams eigenfunction expansion method. Based on an extension of the Stroh formalism and the H-integral derived from Betti’s reciprocal principle for piezoelectric problems, we analyzed the stress intensity factors (SIFs) and asymptotic solutions of piezoelectric bimaterials. The eigenvalues and eigenvectors of an interfacial corner between dissimilar piezoelectric anisotropic materials are determined using the key matrix. The H-integral for piezoelectric problems is introduced to obtain the scalar coefficients, which are related to the SIFs. We propose a new definition of the SIFs of an interfacial corner for piezoelectric materials, and we demonstrated the accuracy of the SIFs by comparing the asymptotic solutions with the results obtained by the finite element method (FEM) with very fine meshes. Proposed method can analyze the stress intensity factors of a corner and a crack between dissimilar isotropic materials, anisotropic materials and anisotropic piezoelectric materials.

Commentary by Dr. Valentin Fuster
2011;():473-478. doi:10.1115/IPACK2011-52096.

Mechanical evaluation method of adhesive strength for bonding IC chips in chip-stacked packages is investigated. These film adhesives are required to bond IC chips securely under JEDEC moisture/reflow test. The stress condition of film adhesives under the moisture/reflow test is analyzed by FEM to clarify proper stress condition for the adhesive test. Thermal strain, moisture expansion and strain induced by vapor pressure is considered. It is found that the shear stress is the main loading factor on reflow process in the analysis. A shear test using chevron-shaped chip is proposed as the adhesive test, which apply shear load to the film adhesive at the corner of a chip. The specimen is fabricated by the same process of actual semiconductor manufacturing. The evaluation method is conducted without any problem. The proposed method is thought to be suitable for film adhesives of chip bonding.

Commentary by Dr. Valentin Fuster
2011;():479-486. doi:10.1115/IPACK2011-52150.

In this study, the effects of uniaxial stress on n-type metal-oxide-semiconductor field effect transistors are investigated by experiments and numerical simulations. In the numerical evaluation, mechanical stress simulation and drift-diffusion device simulation are conducted to consider the impact of stress distribution in the device. The device simulation incorporates an electron mobility model by considering the effects of stress on the following: 1) change in relative population, 2) momentum relaxation time and 3) effective mass of electrons in conduction-band valleys. The variations in the dc characteristics (i.e., drain current and transconductance) of n-type metal-oxide-semiconductor field effect transistors with a gate length of 12μm are evaluated under (nominal) uniaxial stress applied to the device parallel (0°), 45° and perpendicular (90°) to the current flow direction. The results of device simulation are in good qualitative agreement with the experimental results; the device simulation including the present electron mobility model can determine the uniaxial-load-direction dependence of the stress sensitivity of the change in transconductance.

Commentary by Dr. Valentin Fuster
2011;():487-491. doi:10.1115/IPACK2011-52169.

Multi-walled Carbon nanotube (MWCNT) has a great tolerance to electromigration (EM). Therefore, MWCNT is expected to be applied to via-material of electronic devices. But, the damage mechanism of MWCNT has not yet been revealed though oxidation by Joule heating and the EM by high density electron flow are proposed as causes of the MWCNT damage under high current density. In this study, we performed acceleration tests of MWCNT to reveal the damage mechanism of MWCNT under high current density. As a result of the acceleration test, lifetime in low vacuum condition with a low oxygen concentration was longer than that in the air. And, local evaporation of carbon due to oxidation appeared near the cathode end of CNT under both conditions. We confirmed presence of two mechanisms of CNT damage; oxidation and EM. It was shown that the oxidation mechanism at the damage site due to EM was enhanced under oxygen rich condition.

Commentary by Dr. Valentin Fuster
2011;():493-506. doi:10.1115/IPACK2011-52185.

Microprocessor packaging in modern workstations and servers often consists of one or more large flip chip die that are mounted to a high performance ceramic chip carrier. The final assembly configuration features a complex stack up of flip chip area array solder interconnects, underfill, ceramic substrate, lid, heat sink, thermal interface materials, second level CBGA solder joints, organic PCB, etc., so that a very complicated set of loads is transmitted to the microprocessor chip. Several trends in the evolution of this packaging architecture have exacerbated die stress levels including the transition to larger die, high CTE ceramic substrates, lead free solder joints, higher levels of power generation, and larger heat sinks with increased clamping forces. Die stress effects are of concern due to several reasons including degradation of silicon device performance (mobility/speed), damage that can occur to the copper/low-k top level interconnect layers, and potential mechanical failure of the silicon in extreme cases. In this work, we have used test chips containing piezoresistive sensors to measure the buildup of mechanical stresses in a microprocessor die after various steps of the CBGA assembly process, as well as due to heat sink clamping. The developed normal stresses are compressive (triaxial compression) across the die surface, with significant in-plane and out-of-plane (interfacial) shear stresses also present at the die corners. The compressive stresses have been found to increase with each assembly step (flip chip solder joint reflow, underfill dispense and cure, lid attachment, CBGA assembly to PCB, and heat sink clamping). Levels exceeding 500 MPa have been observed for extremely high heat sink clamping forces. The utilized (111) silicon test chips were able to measure the complete three-dimensional stress state (all 6 stress components) at each sensor site being monitored by the data acquisition hardware. The test chips had dimensions of 20 × 20 mm, and 3600 lead free solder interconnects (full area array) were used to connect the chips to the high CTE ceramic chip carriers. Before packaging, the sensor resistances were measured by directly probing the individual test chip wafers. The chips were then diced, reflowed to the ceramic substrate, and then underfilled and cured. A metallic lid and second level solder balls were attached to complete the flip chip ceramic BGA components. After every packaging step (flip chip solder ball reflow, underfill dispense and cure, lid attachment and adhesive cure), the sensor resistances were re-measured, so that the die stresses induced by each assembly operation could be characterized. Finally, CBGAs with the stress sensing chips were soldered to organic PCB test boards. A simulated heat sink loading was then applied, and the stresses were measured as a function of the clamping force. The heat sink clamping pressure distribution was monitored using in-situ resistive sensors in the TIM2 position between the lid and heat sink. The measured stress changes due to heat sink clamping where correlated with finite element simulations. With suitable detail in the models, excellent correlation has been obtained.

Commentary by Dr. Valentin Fuster
2011;():507-518. doi:10.1115/IPACK2011-52186.

Solder joints in electronic assemblies are typically subjected to thermal cycling, either in actual application or in accelerated life testing used for qualification. Mismatches in the thermal expansion coefficients of the assembly materials leads to the solder joints being subjected to cyclic (positive/negative) mechanical strains and stresses. This cyclic loading leads to thermomechanical fatigue damage that involves damage accumulation, crack initiation, crack propagation, and failure. While the effects of aging on solder constitutive behavior (stress-strain and creep) have been examined in some detail, there have been no prior studies on the effects of aging on solder failure and fatigue behavior. In this investigation, we have examined the effects of aging on the cyclic stress-strain behavior of lead free solders. Uniaxial SAC lead free solder specimens were subjected to cyclic (tension/compression) mechanical loading. Samples were cyclically loaded under both strain control (constant positive and negative strain limits) and stress control (constant positive and negative stress limits). The hysteresis loop size (area) was calculated from the measured cyclic stress-strain curves for a given solder alloy and temperature. This area represents the strain energy density dissipated per cycle, which can be typically correlated to the damage accumulation in the joint. The tests in this investigation were performed with SAC105 solder alloy. Prior to cyclic loading, the specimens in this study were aged (preconditioned) at 125 °C for various aging times (0–6 months). From the recorded cyclic stress-strain curves, we have been able to characterize and empirically model the evolution of the solder hysteresis loops with aging. Similar to solder stress-strain and creep behaviors, there is a strong effect of aging on the hysteresis loop size (and thus the rate of damage accumulation) in the solder specimens. The observed degradations in the fatigue/cyclic behavior of the lead free solders are highly accelerated for lower silver content alloys (e.g., SAC105), and for aging and testing at higher temperatures. In our current work, we are also subjecting aged solder samples to cyclic loading until failure occurs. Our ultimate goal is to understand the effects of aging on the thermomechanical fatigue life.

Commentary by Dr. Valentin Fuster
2011;():519-536. doi:10.1115/IPACK2011-52194.

Electronic products are subjected to high G-levels during mechanical shock and vibration. Failure-modes include solder-joint failures, pad cratering, chip-cracking, copper trace fracture, and underfill fillet failures. The second-level interconnects may be experience high-strain rates and accrue damage during repetitive exposure to mechanical shock. Industry migration to leadfree solders has resulted in proliferation of a wide variety of solder alloy compositions. Few of the popular tin-silver-copper alloys include Sn1Ag0.5Cu and Sn3Ag0.5Cu. The high strain rate properties of leadfree solder alloys are scarce. Typical material tests systems are not well suited for measurement of high strain rates typical of mechanical shock. Previously, high strain rates techniques such as the Split Hopkinson Pressure Bar (SHPB) can be used for strain rates of 1000 per sec. However, measurement of materials at strain rates of 1–100 per sec which are typical of mechanical shock is difficult to address. In this paper, a new test-technique developed by the authors has been presented for measurement of material constitutive behavior. The instrument enables attaining strain rates in the neighborhood of 1 to 100 per sec. High speed cameras operating at 300,000 fps have been used in conjunction with digital image correlation for the measurement of full-field strain during the test. Constancy of cross-head velocity has been demonstrated during the test from the unloaded state to the specimen failure. Solder alloy constitutive behavior has been measured for SAC105, and SAC305 solders. Constitutive model has been fit to the material data. Samples have been tested at various time under thermal aging at 25°C and 125°C. The constitutive model has been embedded into an explicit finite element framework for the purpose of life-prediction of leadfree interconnects. Test assemblies has been fabricated and tested under JEDEC JESD22-B111 specified condition for mechanical shock. Model predictions have been correlated with experimental data.

Topics: Alloys
Commentary by Dr. Valentin Fuster
2011;():537-547. doi:10.1115/IPACK2011-52195.

Goldmann Constants and Norris-Landzberg acceleration factors for lead-free solders have been developed based on ridge regression models (RR) for reliability prediction and part selection of area-array packaging architectures under thermo-mechanical loads. Ridge regression adds a small positive bias to the diagonal of the covariance matrix to prevent high sensitivity to variables that are correlated. The proposed procedure proves to be a better tool for prediction than multiple-linear regression models. Models have been developed in conjunction with Stepwise Regression Methods for identification of the main effects. Package architectures studied include, BGA packages mounted on copper-core and no-core printed circuit assemblies in harsh environments. The models have been developed based on thermo-mechanical reliability data acquired on copper-core and no-core assemblies in four different thermal cycling conditions. Packages with Sn3Ag0.5Cu solder alloy interconnects have been examined. The models have been developed based on perturbation of accelerated test thermo-mechanical failure data. Data has been gathered on nine different thermal cycle conditions with SAC305 alloys. The thermal cycle conditions differ in temperature range, dwell times, maximum temperature and minimum temperature to enable development of constants needed for the life prediction and assessment of acceleration factors. Norris-Landzberg acceleration factors have been benchmarked against previously published values. In addition, model predictions have been validated against validation datasets which have not been used for model development. Convergence of statistical models with experimental data has been demonstrated using a single factor design of experiment study for individual factors including temperature cycle magnitude, relative coefficient of thermal expansion, and diagonal length of the chip. The predicted and measured acceleration factors have also been computed and correlated. Good correlations have been achieved for parameters examined.

Commentary by Dr. Valentin Fuster
2011;():549-562. doi:10.1115/IPACK2011-52197.

Electronic assemblies have been monitored using state-space vectors from resistance spectroscopy, phase-sensitive detection and particle filtering (PF) to quantify damage initiation, progression and remaining useful life of the electronic assembly. A prognostication health management (PHM) methodology has been presented for electronic components subjected to mechanical shock and vibration. The presented methodology is an advancement of the state-of-art, which presently focuses on reactive failure detection and provides limited or no insight into the system reliability and residual life. Previously damage initiation, damage progression, and residual life in the pre-failure space has been correlated with micro-structural damage based proxies, feature vectors based on time, spectral and joint time-frequency characteristics of electronics [Lall2004a-d , 2005a-b , 2006a-f , 2007a-e , 2008a-f ]. Precise resistance measurements based on the resistance spectroscopy method have been used to monitor interconnects for damage and prognosticate failure [Lall 2009a,b , 2010a,b , Constable 1992, 2001]. In this paper, the effectiveness of the proposed particle filter and resistance spectroscopy based approach in a prognostic health management (PHM) framework has been demonstrated for electronics. The measured state variable has been related to the underlying damage state using non-linear finite element analysis. The particle filter has been used to estimate the state variable, rate of change of the state variable, acceleration of the state variable and construct a feature vector. The estimated state-space parameters have been used to extrapolate the feature vector into the future and predict the time-to-failure at which the feature vector will cross the failure threshold. Remaining useful life has been calculated based on the evolution of the state space feature vector. Standard prognostic health management metrics were used to quantify the performance of the algorithm against the actual remaining useful life. Application to part replacement decisions for ultra-high reliability system has been demonstrated. Using the technique described in the paper the appropriate time to reorder a replacement part could be monitored, and defended statistically. Robustness of the prognostication algorithm has been quantified using standard performance evaluation metrics.

Commentary by Dr. Valentin Fuster
2011;():563-578. doi:10.1115/IPACK2011-52198.

Electronic systems under extreme shock and vibration environments including shock and vibration may sustain several failure modes simultaneously. Previous experience of the authors indicates that the dominant failure modes experienced by packages in a drop and shock frame work are in the solder interconnects including cracks at the package and the board interface, pad cratering, copper trace fatigue, and bulk-failure in the solder joint. In this paper, a method has been presented for failure mode classification using a combination of Karhunen Loéve transform with parity-based stepwise supervised training of a perceptrons. Early classification of multiple failure modes in the pre-failure space using supervised neural networks in conjunction with Karhunen Loéve transform is new. Feature space has been formed by joint time frequency analysis. Since the cumulative damage may be accrued under repetitive loading with exposure to multiple shock events, the area array assemblies have been exposed to shock and feature vectors constructed to track damage initiation and progression. Error Back propagation learning algorithm has been used for stepwise parity of each particular failure mode. The classified failure modes and failure regions belonging to each particular failure modes in the feature space are also validated by simulation of the designed neural network used for parity of feature space. Statistical similarity and validation of different classified dominant failure modes is performed by multivariate analysis of variance and Hoteling’s T-square. The results of different classified dominant failure modes are also correlated with the experimental cross sections of the failed test assemblies. The methodology adopted in this paper can perform real-time fault monitoring with identification of specific dominant failure mode and is scalable to system level reliability.

Commentary by Dr. Valentin Fuster
2011;():579-583. doi:10.1115/IPACK2011-52219.

It has been a common practice in the microelectronics industry to evaluate the long-term solder joint reliability using the accelerated temperature cycling (ATC) test. The thermal fatigue failure mechanism of solder joints during the ATC test involves the initiation of microcracks and, subsequently, their propagation and coalescence for a complete joint separation. Traditionally, the industry employs methods based on the measurement of the daisy-chain resistance to monitor the failure of the solder joints. Yet, there is no specific study to investigate the relationship between the resistance change during the ATC test and the crack formation of the solder fatigue. This study aims to provide an experimental investigation on such relationship. A custom-made sample is designed and fabricated in the study. The fatigue crack growth in solder joints of certain custom-made assemblies can be directly inspected during the test. The daisy-chain resistance is real-time monitored. The test results reveal that the electrical resistance monitoring approach is not effective in detecting the fatigue crack initiation and subsequent propagation. As a result, a partially degraded interconnect cannot be identified. Therefore, new monitoring methods should be developed for this purpose.

Commentary by Dr. Valentin Fuster
2011;():585-590. doi:10.1115/IPACK2011-52230.

Increasing miniaturization has led a significant increase in the current densities seen in flip-chip solder joints. This has made the study of failure in solder joints by void propagation due to electromigration and stress migration more important. In this study, we develop a phase field model for the motion of voids through a flip chip solder interconnect. We derive equations of motion for the void accounting for energetic contributions from the active factors of surface energy, stress and electric potential, taking into account both surface diffusion and transfer of the material through the bulk of the material. We describe the implementation of this model using finite elements, coupled with a commercial finite element solver to solve for the fields driving the void motion.

Commentary by Dr. Valentin Fuster
2011;():591-602. doi:10.1115/IPACK2011-52231.

The consumer electronics industry stands at a critical juncture where manufacturers strive to incorporate more functionality in smaller packages. In the highly competitive consumer electronics market, a continued demand for products with smallest possible form-factor yet high functionality has led to the proliferation of 3D packaging technologies. Package-on-Package (PoP) architectures, in particular have attracted a lot of interest, especially in portable electronics industry. The advantages of these stacked 3D architectures include simplified and compact design, savings of board space allowing for more package landings, reduced pin counts and optimized production costs. While a lot of recent research, in the field of PoP architectures has been focused on development of optimum process flows and warpage control during reflow, the effects of reflow parameters on the quality of PoP build and the associated reflow defects including warpage have not been extensively researched. Additionally, studies on reliability issues associated with PoP assemblies in drop and shock environments are scarce. Since PoP architectures find their applications mainly in portable electronics, which are susceptible to frequent drops and careless handling at the hand of the consumer, the reliability of PoP architectures in environments representative of the real world is critical to their success in the industry. In this study, Single component PoP test vehicles have been fabricated as per JEDEC standards for quantifying the reliability of PoP packages in drop and shock. Daisy chained double-stack PoP components have been used to identify failure for subsequent drop/shock performance analysis. Experimental strain data acquired using Digital Image Correlation and high speed continuity data- for identifying failure has been used in conjunction with validated FE simulations of drop test events; for development of life prediction models for PoP architectures. Validated node based global-local FE simulations are used to predict strains in critical solder balls in both layers of the PoP stack. The drop/shock reliability studies and life prediction models presented in this work, present an insight into PoP failures and eliminate the need for exhaustive testing procedures.

Commentary by Dr. Valentin Fuster
2011;():603-608. doi:10.1115/IPACK2011-52232.

The ever increasing power density in modern semiconductor devices requires heat dissipation solution such as heat sink to remove the heat away from the device. A compressive loading was applied to reduce the interfacial thermal resistance between package and heat sink. In this study both numerical modeling and experimental approaches were employed to study the effect of compressive loading on the interconnect reliability, especially for high power density package, under thermal cycling loading conditions. The JEDEC standard thermal cycle tests were conducted and the resistance of the daisy chained circuits was in-situ measured to record the failure time. The failure analysis has been performed to indentify the failure modes of solder joint with and without the presence of compressive loading. A finite element based thermal fatigue life prediction model for SAC305 solder joint under compressive loading was also developed and validated with the experimental results.

Topics: Reliability
Commentary by Dr. Valentin Fuster
2011;():609-615. doi:10.1115/IPACK2011-52260.

Flip Chip (FC) technology has now become the mainstream solution for high performance packages. From commercial gaming machines to high reliability servers, the FC package is gaining more market share over traditional packaging technologies, such as wire bond. Extensive research has been carried out to make the flip chip more robust, smaller foot prints, and excellent performance. FC packages are fabricated typically in two main configurations. Bare die FC packages leave the non active side of the die exposed. This allows the customer to apply their preferred heat dissipation scheme during board level attach. Lidded FC packages use a metallic lid attached to the die. Bare die package can be further subdivided into bare die underfilled package and bare die flip chip molded ball grid array (FCm BGA) package. Each of these packaging configurations has advantages as well as disadvantages. FCm BGA uses molding compound or EMC instead of capillary underfill, to protect FC die, and eliminate the need for a lid. Package warpage reduced a lot by adding a lid with the bare die FC package. However, the package and board level reliability for the above package types are still debatable. In this study test vehicles with three package types with bumps and BGAs are daisy chain to measure in situ data during accelerated tests. Impact of standard vs. low CTE (coefficient of thermal expansion) core substrate, accelerated temperature cycle conditions (temperature cycle condition “B”, “H”, and “J” according to JEDEC), and package level vs. package mounted on the board level reliability will be investigated. Comprehensive reliability data will help to select the right package type for next generation large die large body flip chip application.

Commentary by Dr. Valentin Fuster
2011;():617-625. doi:10.1115/IPACK2011-52296.

Solders have been utilized extensively in the MEMS packaging industry to create vacuum or hermetic seals in a variety of applications. MEMS technology is finding applications in wide range of products like pressure sensors, actuators, flow control devices etc. For many harsh low temperature environment applications, like commercial refrigeration systems, MEMS based pressure sensors and flow actuators are directly mounted on to metal substrates using solders to create hermetic sealing. Solders attaching silicon devices directly to metal substrates may be subjected to very high thermal stresses due to significant difference in thermal expansion coefficients during chip operation or environment temperatures. In this paper, case study of a high powered MEMS chip (referred in the paper as die) operating in a commercial refrigeration system is presented. Accelerated test method for qualifying solder joint for high pressure applications is briefly discussed. Lab experiments showing typical refrigeration cycle thermal load on solder joint are presented. Based on the study, concepts of die power toggling and power allocation towards enhancing hermetic solder joint reliability are discussed. Detailed numerical case studies are presented to quantify the improvement in solder joint reliability due to the proposed concept.

Commentary by Dr. Valentin Fuster

Electrical

2011;():627-631. doi:10.1115/IPACK2011-52254.

The need for better high frequency performance, improved I/O power decoupling, and introduction of multi-chip processors are just some of the drivers for developing embedded capacitor technologies. One new technology, the Thin Film Embedded Package Capacitor (TFC) can target an improvement in the high frequency performance of the microprocessor power delivery network. Using this technology prototype packages for an Intel Microprocessor were fabricated and the impedance of the power delivery network (PDN) measured. The packages with the embedded TFCs demonstrated a reduction by more than a factor of 2 in the high frequency power delivery network impedance, and correspondingly improved voltage droop.

Topics: Thin films
Commentary by Dr. Valentin Fuster
2011;():633-639. doi:10.1115/IPACK2011-52268.

Discrete components, such as capacitors and inductors, play an important role in the analysis and design of electronic packages and printed circuit boards. Although the electrical parameters of discrete components are described by manufacturers, the component performance at product operating conditions can vary drastically from the manufacturer’s specification. Accurate characterization of discrete package components at operating conditions is essential to understand product operation. This paper will introduce a method to characterize discrete capacitors and inductors while applying multiple operating conditions simultaneously. Several inductor options will be evaluated, including a newly introduced metal composite component.

Commentary by Dr. Valentin Fuster
2011;():641-646. doi:10.1115/IPACK2011-52274.

Even though it has always been known that Signal Integrity analysis and Power Integrity (Power Delivery) analysis are related, historically they have been treated and analyzed independently with some timing and voltage buckets used to tie the effects of one on the other. When the voltage and timing margins were large, this approach worked quite well. However as voltage levels, timing windows and their margins have shrunk, the traditional method of analyzing them independently no longer suffices. The signal quality and timing (eye height & eye width) losses due to the effects of power delivery are no longer negligible. The concept of signal integrity & power delivery co-simulation (referred to as SIPD or SIPI co-sim) is a methodology developed to address this problem. In this paper we will use the DDR bus as an example to illustrate the impacts of power delivery on the signal and highlight how badly the margin loss would have been underestimated if the effects of power delivery were ignored. The paper will demonstrate how SIPD co-sim can quantify or illustrate - the effects of data randomization, margin gain with fully random data patterns, margin loss due to the effects of Burst-Idle-Burst data patterns, definition of noise & eye diagram BER, statistically significant noise in system, etc.

Topics: Simulation , Signals
Commentary by Dr. Valentin Fuster
2011;():647-652. doi:10.1115/IPACK2011-52276.

In this work, guided by electromagnetics-based first principles, we develop a circuit simulator that allows for the simulation of a circuit including both nonlinear devices and the linear network in linear complexity. Moreover, it permits an almost embarrassingly parallel implementation on a many-core computing platform, and hence achieving linear speedup. The proposed circuit simulator rigorously captures the coupling between nonlinear circuits and the linear network. In addition, it bypasses the step of extraction, producing an RLC (resistor-inductor-capacitor) representation of the linear network without any numerical computation. Application to die-package co-simulation as well as simulation of very large-scale on-chip circuits involving over 800,000 CMOS transistors and interconnects having hundreds of millions of unknowns has demonstrated the superior performance of the proposed first-principle-guided circuit simulator.

Topics: Design , Circuits
Commentary by Dr. Valentin Fuster
2011;():653-661. doi:10.1115/IPACK2011-52279.

This paper describes an accurate and efficient analysis methodology that enables circuit optimization directly guided by platform-level metric such as link eye margin. Prior to this work, such analysis was not feasible due to significant compute time required by complex circuit simulations. A new method of developing highly abstracted behavioral models of complex circuit blocks is a critical element of this analysis methodology. The method uses statistical signaling analysis and optimization capabilities coupled with behavioral modeling of I/O clocking, transmitter and receiver circuitry that are based on accurate circuit simulations. We also present measured data from products and test chips that show correlation between measured and modeled data within 10–15%. Finally, we describe how the methodology was used to optimize the design of a high speed serial link and achieve approximately 70% improvement in eye margins with limited design iterations.

Topics: Design
Commentary by Dr. Valentin Fuster
2011;():663-669. doi:10.1115/IPACK2011-52280.

Large-scale public cloud commodity computing is a potential paradigm-shifter for EDA tools. However, to go beyond merely web-hosted software and to exploit the true power of on-demand scalable computing is as yet an unmet challenge on many fronts. In this paper, we examine one computationally expensive and rapidly growing area within EDA as a candidate for the cloud, namely parasitic extraction and electromagnetic field simulation. With the growing emphasis on multifunctional systems in consumer electronics around commodity chips, the need for scale and speed in such tools is paramount. We examine from three aspects the suitability of and modifications needed to accelerated multilevel algorithms in boundary element methods in order to ensure cloud deployment: scalability without hitting Amdahl’s law prematurely, fault tolerance with low time penalties in realistic computing systems, and encryption-free approaches to ensuring IP security.

Commentary by Dr. Valentin Fuster
2011;():671-674. doi:10.1115/IPACK2011-52282.

RF System-in-Package (SiP) has become a viable packaging platform, which offers great flexibility to integrate ICs with different processes and different architects. With operating frequency becoming higher and multiple available technologies embedded in one package, the system could fail due to the undesired noise coupling resulted from the close proximity of the components. Therefore, the design methodology with signal integrity (SI), power integrity (PI), and electromagnetic compatibility (EMC) analysis becomes essential to tackle the SiP integration issues. The paper presents a RF SiP design methodology with SI/PI/EMC simulations, which greatly reduces the design time and enables first-pass success.

Commentary by Dr. Valentin Fuster
2011;():675-679. doi:10.1115/IPACK2011-52287.

In this paper, a simple circuit model for IC multiple power and ground via arrays in a multilayer PCB is built based on the resonant cavity model. Using the circuit model, the parasitic inductance for the IC power and ground connection is quantitatively investigated according to via number and via patterns. The stack-up configuration of the power/ground plane pair is not critical for PDN performance in multilayer PCBs, as long as there are sufficient IC power/ground vias in an alternating pattern. The outcome of this work can be used to guide the pin-map design for high-speed packages.

Topics: Design
Commentary by Dr. Valentin Fuster
2011;():681-684. doi:10.1115/IPACK2011-52291.

The impact of power integrity on processor performance is critical in nano-scale era. We proposed the enhanced pre-silicon simulation to accurately capture the power delivery quality. The post silicon performance measurements correlates well with pre-silicon analysis and demonstrate that power integrity could impact performance up to 15% in low and high frequencies.

Commentary by Dr. Valentin Fuster

Emerging Technologies

2011;():685-692. doi:10.1115/IPACK2011-52046.

Hydrophobic surfaces with microscale roughness can be rendered ultrahydrophobic by the addition of sub-micron scale roughness. A simple yet highly effective concept of fabricating hierarchical structured surfaces using a single-step deep reactive ion etch process is proposed. Using this method the complexities generally associated with fabrication of two-tier roughness structures are eliminated. Experiments are conducted on two double-roughness surfaces with different surface roughness, achieved by varying the size of the microscale roughness features. The surfaces are characterized in terms of static contact angle and roll-off angle and compared with surfaces consisting of only single-tier microscale roughness. The robustness of the new hierarchical roughness surfaces is verified through droplet impingement tests. The hierarchical surfaces are more resistant to wetting than the single roughness surfaces and show higher coefficients of restitution for droplets bouncing off the surface. The droplet dynamics upon impingement are explored.

Commentary by Dr. Valentin Fuster
2011;():693-701. doi:10.1115/IPACK2011-52061.

The static shape of droplets under electrowetting actuation is well-understood. The steady-state shape of the droplet is obtained based on the balance of surface tension and electrowetting forces, and the change in apparent contact angle is well-characterized by the Young-Lippmann equation. However, the transient droplet shape behavior when a voltage is suddenly applied across a droplet has received less attention. Additional dynamic frictional forces are at play during this transient process. We present a model to predict this transient behavior of the droplet shape under electrowetting actuation. The droplet shape is modeled using the volume of fluid method. The electrowetting and dynamic frictional forces are included as an effective dynamic contact angle through a force balance at the contact line. The model is used to predict the transient behavior of water droplets on smooth hydrophobic surfaces under electrowetting actuation. The predictions of transient behavior of droplet shape and contact radius are in excellent agreement our experimental measurements. The internal fluid motion is explained and the droplet motion is shown to initiate from the contact line. An approximate mathematical model is also developed to understand the physics of the droplet motion and to describe the overall droplet motion and the contact line velocities.

Commentary by Dr. Valentin Fuster
2011;():703-708. doi:10.1115/IPACK2011-52064.

A novel noncontact stress/strain measurement method has been developed for monitoring dynamic strain on the surface of various structures under operation. The change of electrical properties of carbon nanotubes (CNT)-dispersed resin was investigated to evaluate the possibility of its application to a highly sensitive and remote strain sensor without interconnections. It was validated that the electrical impedance of the CNT-dispersed resin changes drastically at frequencies higher than 500 kHz under strain. Application of microwave showed the possibility of the non-contact measurement of the change of electrical impedance of the resin under dynamic load by measuring the change of its reflectivity obtained from the surface of the resin. A theoretical method to estimate the change of the intensity of the microwave reflected from the resin was discussed based on the microwave theory. The change of the reflectance under tensile strain of 20% was calculated by the method using the measured change of the impedance of the resin under the frequency range between 1Hz and 10MHz. As a result, the maximum change of the reflectance was estimated as 1.2% at 630 kHz. Therefore, it is possible to realize remote monitoring of the strain field on the surface of various products under operation by applying the CNT-dispersed resin.

Commentary by Dr. Valentin Fuster
2011;():709-712. doi:10.1115/IPACK2011-52071.

Fine thermoelectric elements were fabricated on an electrode chip where the tips of the Pt and W thin wires having the diameter of 5 μm were welded together by Joule heat welding. Firstly, the dissimilar metal weld was contacted to thin wire heater and the voltage appeared in the circuit due to Seebeck effect was measured. Current was supplied to the one of the thermoelectric element and the temperature at the Pt/W weld was measured by the other element. It was found that the temperature at dissimilar metal weld depended on the direction of current and Peltier effect was successfully observed.

Commentary by Dr. Valentin Fuster
2011;():713-721. doi:10.1115/IPACK2011-52078.

Today’s consumer market demands electronics that are smaller, faster and cheaper. To cater to these demands, novel materials, new designs, and new packaging technologies are introduced frequently. Wafer Level Chip Scale Package (WLCSP) is one of the emerging package technologies that have the key advantages of reduced cost and smaller footprint. The portable consumer electronics are frequently dropped; hence the emphasis of reliability is shifting towards study of effects of mechanical shock loading increasingly. Mechanical loading typically induces brittle fractures (also known as intermetallic failures) between the solder bumps and bond pads at the silicon die side. This type of failure mechanism is typically characterized by the board level drop test. WLCSP is a variant of the flip-chip interconnection technique. In WLCSPs, the active side of the die is inverted and connected to the PCB by solder balls. The size of these solder balls is typically large enough (300μm pre-reflow for 0.5mm pitch and 250μm pre-reflow for 0.4mm pitch) to avoid use of underfill that is required for the flip-chip interconnects. Several variations are incorporated in the package design parameters to meet the performance, reliability, and footprint requirements of the package assembly. The design parameters investigated in this effort are solder ball compositions with different Silver (Ag) content, backside lamination with different thickness, WLCSP type –Direct and Re-Distribution Layer (RDL), bond pad thickness, and sputtered versus electroplated Under Bump Metallurgy (UBM) deposition methods for 8×8, 9×9, and 10×10 array sizes. The test vehicles built using these design parameters were drop tested using JEDEC recommended test boards and conditions as per JESD22-B11. Cross sectional analysis was used to identify, confirm, and classify the intermetallic, and bulk solder failures. The objective of this research was to quantify the effects and interactions of WLCSP design parameters through drop test. The drop test data was collected and treated as a right censored data. Further, it was analyzed by fitting empirical distributions using the grouped and un-grouped data approach. Data analysis showed that design parameters had a significant effect on the drop performance and played a vital role in influencing the package reliability.

Commentary by Dr. Valentin Fuster
2011;():723-731. doi:10.1115/IPACK2011-52143.

System-On-Film (SOF) module is a complex integration of a fine pitch high density die and surface mounted discrete devices on a polyimide (PI) film laminate. The die is connected to the film using a thermo-compression flip-chip bonding (TCB) process which is capable of providing a very high density interconnect at less than 50um pitch. Several design and bonding parameters have to be controlled in order to achieve a reliable bond between the Au bumps on the die and the Sn plated Cu traces on the PI film. In the current work, the TCB process is studied using Finite Element Analysis (FEA) to optimize the design parameters and assure proper process margins. The resultant forces acting on the bump-to-trace interfaces are quantified across the different potential geometrical combinations. Baseline simulations showed higher stresses on specific bump locations and stress gradients acting on the bumps along the different sides of the die. These observations were correlated to both the failures and near failures on the actual test vehicles. Further simulations were then utilized to optimize and navigate design tradeoffs at both the die and flexible substrate design levels for a more robust design solution. Construction analysis performed on parts built using optimized design parameters showed significant improvements and correlated well with the simulation results.

Commentary by Dr. Valentin Fuster
2011;():733-739. doi:10.1115/IPACK2011-52190.

We conducted an analytic study of concentrated solar photovoltaic and hot water co-generation based on various solar cell technologies and micro channel heat sinks. By co-optimizing the electricity generation and heat transport in the system, one can minimize the cost of the key materials and compare different tradeoffs as a function of concentration ratio or other parameters. Concentrated solar Photovoltaic (PV) based on multi junction cells can yield around 35–40% efficiency. They are suitable for high photon energy flux and they are already available in the market. However, due to high heat fluxes at large concentrations, such as 100–1000 Suns, heat sinks could be costly in terms of material mass, space, energy for pumping fluid, and system complexity. In addition, since the efficiency of solar cells decreases as the ambient temperature increases, there is a tradeoff between electricity and hot water cogeneration. Similar to our previous analysis of thermoelectric (TE) and hot water co-generation, PV/solar thermal system is also optimized. The results are compared with thermoelectric systems as a function of the concentration ratio. The solar concentrated co-generation system using either PV or TE for direct electricity generation collects more than 80% of solar energy when it is optimized. We calculate the overall cost minima as a function of concentration ratio. Although there are some differences between PV and TE, the optimum concentration ratio for the system is in the range of 100–300 Suns for both.

Commentary by Dr. Valentin Fuster
2011;():741-747. doi:10.1115/IPACK2011-52191.

Energy recovery from waste heat is attracting more and more attention. All electronic systems consume electricity but only a fraction of it is used for information processing and for human interfaces, such as displays. Lots of energy is dissipated as heat. There are some discussions on waste heat recovery from the electronic systems such as laptop computers. However the efficiency of energy conversion for such utilization is not very attractive due to the maximum allowable temperature of the heat source devices. This leads to very low limits of Carnot efficiency. In contrast to thermodynamic heat engines, Brayton cycle, free piston Stirling engines, etc., authors previously reported that thermoelectric (TE) can be a cost-effective device if the TE and the heat sink are co-optimized, and if some parasitic effects could be reduced. Since the heat already exists and it is free, the additional cost and energy payback time are the key measures to evaluate the value of the energy recovery system. In this report, we will start with the optimum model of the TE power generation system. Then, theoretical maximum output, cost impact and energy payback are evaluated in the examples of electronics system. Entropy Generation Minimization (EGM) is a method already familiar in thermal management of electronics. The optimum thermoelectric waste heat recovery design is compared with the EGM approach. Exergy analysis evaluates the useful energy flow in the optimum TE system. This comprehensive analysis is used to predict the potential future impact of the TE material development, as the dimensionless figure-of-merit (ZT) is improved.

Commentary by Dr. Valentin Fuster
2011;():749-755. doi:10.1115/IPACK2011-52214.

Laser measurement and laser processing techniques have been gaining strong attention from various applications [1,2]. This research aims at the development of a fluidic laser beam shaper, and in order to fulfill the objective, characteristics of the thermal lens effect are studied. This phenomenon has the optical property of a concave lens since the refractive index distribution on the optical axis is formed when the liquid is irradiated. One reason for the refractive index distribution in the liquid is the temperature distribution in the liquid when it is irradiated. In this research, effects of the pump power and propagation distance of the probe beam to probe beam profile are investigated experimentally and theoretically, in order to develop fluidic laser beam shaper. It is indicated that, by controlling some parameters in thermal lens system as pump power (in the regime of linear optics) and absorption coefficient, input Gaussian beam can be converted into flat-top beam profile. The relationship among the distance to obtain a flat-top beam, pump power and absorption coefficient is investigated to show the flexibility of fluidic laser beam shaper in many fields of laser application.

Commentary by Dr. Valentin Fuster
2011;():757-768. doi:10.1115/IPACK2011-52244.

In this paper, we analyze cross plane phonon transport and thermal conductivity in two-dimensional Si/Ge nanocomposites. A non-gray BTE model that includes full details of phonon dispersion, the spread in phonon mean free paths and the frequency dependent transmissivity is used to simulate thermal transport. The general conclusions inferred from gray BTE simulations that the thermal conductivity of the nanocomposite is much lower than its constituent materials and interfacial density as the parameter determining thermal conductivity remain the same. However, it is found that the gray BTE significantly overpredicts thermal conductivity in the length scales of interest and quantitatively reliable results are obtained only upon inclusion of the details of phonon dispersion. The transition of phonon transport from ballistic regime to near diffusive regime is observed by looking at a large range of length scales. Non-equilibrium energy exchange between optical and acoustic phonons and the granularity in phonon mean free paths are found to significantly affect thermal conductivity leading to departures from the frequently employed gray approximation. It is also found that the frequency content of thermal conductivity in the nanocomposite extends out to a much larger frequency range unlike bulk Si and Ge. Scattering against heterogeneous interfaces is very effective in suppressing thermal conductivity contribution from the low frequency acoustic phonons but less so for high frequency phonons, which have much smaller mean free paths.

Commentary by Dr. Valentin Fuster
2011;():769-778. doi:10.1115/IPACK2011-52245.

Using the linearized Boltzmann transport equation and perturbation theory, we analyze the reduction in the intrinsic thermal conductivity of few-layer graphene sheets accounting for all possible three-phonon scattering events. Even with weak coupling between layers, a significant reduction in the thermal conductivity of the out-of-plane acoustic modes is apparent. The main effect of this weak coupling is to open many new three-phonon scattering channels that are otherwise absent in graphene. The highly restrictive selection rule that leads to a high thermal conductivity of ZA phonons in single-layer graphene is only weakly broken with the addition of multiple layers, and ZA phonons still dominate thermal conductivity. We also find that the decrease in thermal conductivity is mainly caused by decreased contributions of the higher-order overtones of the fundamental out-of-plane acoustic mode. Moreover, the extent of reduction is largest when going from single to bilayer graphene and saturates for four layers. The results compare remarkably well over the entire temperature range with measurements of of graphene and graphite.

Commentary by Dr. Valentin Fuster
2011;():779-782. doi:10.1115/IPACK2011-52295.

Reliability has been studied in the PV industry using a variety of experimental and modeling techniques, to probe specific aspects of design and performance. In this paper, a methodology that integrates experimental and modeling techniques to enable risk mitigation in the development cycle and reliability estimation is presented.

Commentary by Dr. Valentin Fuster

Sorry! You do not have access to this content. For assistance or to subscribe, please contact us:

  • TELEPHONE: 1-800-843-2763 (Toll-free in the USA)
  • EMAIL: asmedigitalcollection@asme.org
Sign In