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Eulerian Multiphase Conjugate Model for Chip-Embedded Micro-Channel Flow Boiling

[+] Author Affiliations
Pritish R. Parida, Timothy J. Chainer

IBM T. J. Watson Research Center, Yorktown Heights, NY

Hsin-Hua Tsuei

Computer Aided Engineering Associates, Inc., Middlebury, CT

Paper No. IPACK2015-48489, pp. V003T10A027; 11 pages
  • ASME 2015 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems collocated with the ASME 2015 13th International Conference on Nanochannels, Microchannels, and Minichannels
  • Volume 3: Advanced Fabrication and Manufacturing; Emerging Technology Frontiers; Energy, Health and Water- Applications of Nano-, Micro- and Mini-Scale Devices; MEMS and NEMS; Technology Update Talks; Thermal Management Using Micro Channels, Jets, Sprays
  • San Francisco, California, USA, July 6–9, 2015
  • Conference Sponsors: Electronic and Photonic Packaging Division
  • ISBN: 978-0-7918-5690-1
  • Copyright © 2015 by ASME


The 3D (three dimensional) integration of microelectronic chips into chip stacks is an enabling technology to provide a possible path for increasing computational performance. However, 3D chip stacks require a solution to significant new thermal challenges. As a feasible solution, two-phase cooling utilizing a chip-to-chip interconnect-compatible dielectric fluid can be used. This chip-integrated micrometer scale two-phase cooling technology can be essential to fully optimize the benefits of improved integration density and modularity of 3D stacking of high performance integrated circuits (ICs) for future computing systems; but is faced with significant developmental challenges including high fidelity modeling.

In the present work, an Eulerian multiphase model has been developed for simulating two-phase evaporative cooling through chip embedded microscale cavities. First, the model was used to predict the flow and heat transfer characteristics for coolant R245fa flowing through a single straight micro channel with cross section 100 × 100 um and length 10 mm. The flow is sub-cooled in the initial section of the channel and saturated in the remaining. The results were compared to experimental data available from literature, focusing on the model capability to predict the correct flow pattern, temperature profile and pressure drop. Next, the validated model was extended to the simulation of complex flow geometries expected in microprocessor chip-stacks with chip-to-chip interconnects.

Copyright © 2015 by ASME



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