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Reduced Order Modeling for Chip-Embedded Micro-Channel Flow Boiling

[+] Author Affiliations
Pritish R. Parida

IBM T. J. Watson Research Center, Yorktown Heights, NY

Paper No. IPACK2015-48370, pp. V001T09A085; 10 pages
doi:10.1115/IPACK2015-48370
From:
  • ASME 2015 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems collocated with the ASME 2015 13th International Conference on Nanochannels, Microchannels, and Minichannels
  • Volume 1: Thermal Management
  • San Francisco, California, USA, July 6–9, 2015
  • Conference Sponsors: Electronic and Photonic Packaging Division
  • ISBN: 978-0-7918-5688-8
  • Copyright © 2015 by ASME

abstract

The information technology (IT) industry is exploring three-dimensional (3D) stacking of chips to maintain future computing scalability. However, 3D chip stacks require a solution to significant new thermal challenges. Interlayer two-phase evaporative cooling with a chip-to-chip interconnect-compatible dielectric fluid is an enabling technology but faces significant development issues. One such issue is the inability to thermally model a microprocessor with spatially varying heat sources together with a two phase microfluidic convection network. While progress has been made on two-phase conjugate simulations at the chip and channel levels, none of those provide a computationally manageable approach.

In the present study, a reduced physics conjugate heat transfer model has been developed for simulating two-phase flow boiling through chip embedded micron scale cavities. This model has been validated with good accuracy against data available from literature. The validated model was then extended to predict the thermal performance of a state-of-the-art microprocessor chip with embedded two-phase cooling, where significant improvements in device junction temperatures were observed compared to the baseline cooling solution.

Copyright © 2015 by ASME

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