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Full Scale Simulation of an Integrated Monolithic Heat Sink for Thermal Management of a High Power Density GaN-SiC Chip

[+] Author Affiliations
Tanya Liu, Farzad Houshmand, Catherine Gorle, Sebastian Scholl, Hyoungsoon Lee, Yoonjin Won, Mehdi Asheghi, Kenneth Goodson

Stanford University, Stanford, CA

Hooman Kazemi, Kenneth Vanhille

Nuvotronics LLC, Radford, VA

Paper No. IPACK2015-48592, pp. V001T09A057; 9 pages
doi:10.1115/IPACK2015-48592
From:
  • ASME 2015 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems collocated with the ASME 2015 13th International Conference on Nanochannels, Microchannels, and Minichannels
  • Volume 1: Thermal Management
  • San Francisco, California, USA, July 6–9, 2015
  • Conference Sponsors: Electronic and Photonic Packaging Division
  • ISBN: 978-0-7918-5688-8
  • Copyright © 2015 by ASME

abstract

Advances in manufacturing techniques are inspiring the design of novel integrated microscale thermal cooling devices seeking to push the limits of current thermal management solutions in high heat flux applications. These advanced cooling technologies can be used to improve the performance of high power density electronics such as GaN-based RF power amplifiers. However, their optimal design requires careful analysis of the combined effects of conduction and convection.

Many numerical simulations and optimization studies have been performed for single cell models of microchannel heat sinks, but these simulations do not provide insight into the flow and heat transfer through the entire device. This study therefore presents the results of conjugate heat transfer CFD simulations for a complex copper monolithic heat sink integrated with a 100 micron thick, 5 mm by 1 mm high power density GaN-SiC chip. The computational model (13 million cells) represents both the chip and the heat sink, which consists of multiple inlets and outlets for fluid entry and exit, delivery and collection manifold systems, and an array of fins that form rectangular microchannels. Total chip powers of up to 150 W at the GaN gates were considered, and a quarter of the device was modeled for total inlet mass flow rates of 1.44 g/s and 1.8 g/s (0.36 g/s and 0.45 g/s for the quarter device), corresponding to laminar flow at Reynolds numbers between 19.5 and 119.3. It was observed that the mass flow rates through individual microchannels in the device vary by up to 45%, depending on the inlet/outlet locations and pressure drop in the manifolds. The results demonstrate that full device simulations provide valuable insight into the multiple parameters that affect cooling performance.

Copyright © 2015 by ASME

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