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Chip Package Co-Design: Effect of Substrate Warpage on BEOL Reliability

[+] Author Affiliations
Sathyanarayanan Raghavan, Suresh Sitaraman

Georgia Institute of Technology, Atlanta, GA

Ilko Schmadlak

Freescale Semiconductor, Munich, Germany

George Leal

Freescale Semiconductor, Austin, TX

Paper No. IMECE2013-65877, pp. V010T11A074; 6 pages
  • ASME 2013 International Mechanical Engineering Congress and Exposition
  • Volume 10: Micro- and Nano-Systems Engineering and Packaging
  • San Diego, California, USA, November 15–21, 2013
  • Conference Sponsors: ASME
  • ISBN: 978-0-7918-5639-0
  • Copyright © 2013 by ASME


Large-scale integration at lower cost has led to the usage of multi-layered organic substrates in flip-chip assemblies. However, the warpage of substrate plays an important role in the reliability of back-end-of-line (BEOL) stack on a chip. In this work, we study the effect of substrate layer configuration, and thus the warpage of the substrate at reflow temperature on BEOL reliability. A plane-strain flip-chip on substrate assembly model is utilized to study the die and solder stresses for different substrate layer configurations. Apart from studying the die stresses, fracture mechanics based approach is used to study the effect of substrate configuration on energy available for a crack present in back-end-of-line (BEOL) stack. In this paper, we describe the methodology to model the substrate with initial warpage at reflow temperature, characterize the effect of the initial warpage at reflow temperature on die stresses at room temperature and further use fracture mechanics based approach to predict the change in risk for a crack present in BEOL stack for different substrate warpage configurations at reflow temperature.

Copyright © 2013 by ASME
Topics: Reliability , Warping , Design



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