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A Hierarchical Framework for Thermal Modelling of Electronic Devices: From Atoms to Chips

[+] Author Affiliations
David A. Romero, Elham Pakseresht, Daniel Sellan, Aydin Nabovati, Cristina Amon

University of Toronto, Toronto, ON, Canada

Paper No. IPACK2013-73202, pp. V002T08A043; 9 pages
doi:10.1115/IPACK2013-73202
From:
  • ASME 2013 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems
  • Volume 2: Thermal Management; Data Centers and Energy Efficient Electronic Systems
  • Burlingame, California, USA, July 16–18, 2013
  • Conference Sponsors: Electronic and Photonic Packaging Division
  • ISBN: 978-0-7918-5576-8
  • Copyright © 2013 by ASME

abstract

In this work, we provide an overview of a hierarchical computational framework to predict thermal transport in electronic devices through integration of physics-based models at different length scales. Information from atomistic simulations at the smallest length scales are transferred to upper levels of the hierarchy, up to thermal models for the chip. The proposed methodology includes five levels of length scales in electronic devices, namely (i) atomistic level, (ii) thin film and nanowire level, (iii) transistor and logic gate level, (iv) functional block level, and (v) chip level. At the first level of the hierarchy, properties of energy carriers in a semiconductor material (e.g., phonons) are obtained from atomistic level simulations, such as Molecular Dynamics (MD) and Lattice Dynamics (LD) calculations. At the second level, thermal transport in thin silicon films is modelled using a Lattice Boltzmann Method (LBM) for phonons. The outcome of these simulations is a size-dependent thermal conductivity for silicon films. At the third level of the hierarchy, these effective thermal conductivities are used in thermal modelling of logic gates. Detailed structures of different types of logic gates are reconstructed based on different manufacturing technologies (MOSFET and FinFET) at different technology nodes. Since the characteristic sizes of different parts of the logic gates are comparable to the mean free path of energy carriers, we use the size-dependent, effective thermal conductivities that were calculated at lower levels of the hierarchy to build simulation models for the logic gates. Based on these models, we calculate an equivalent thermal conductance for the logic gates, which would then be used in the upper level simulations to determine an equivalent thermal conductance for different functional blocks of the die based on their internal structure and the number and type of logic gates found in each functional block. Overall, the proposed hierarchical model enables us to include the effect of atomistic-level physics into package-level simulations, and thus, have an accurate prediction of thermal transport in an electronic device.

Copyright © 2013 by ASME
Topics: Atoms , Modeling

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