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Experimental Measurement of the Thermal Performance of a Two-Die 3D Integrated Circuit (3D IC)

[+] Author Affiliations
Leila Choobineh, Ankur Jain

University of Texas, Arlington, Arlington, TX

Nick Vo, Trent Uehling

Freescale Semiconductor, Austin, TX

Paper No. IPACK2013-73167, pp. V002T08A034; 5 pages
  • ASME 2013 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems
  • Volume 2: Thermal Management; Data Centers and Energy Efficient Electronic Systems
  • Burlingame, California, USA, July 16–18, 2013
  • Conference Sponsors: Electronic and Photonic Packaging Division
  • ISBN: 978-0-7918-5576-8
  • Copyright © 2013 by ASME


Accurate measurement of the thermal performance of vertically-stacked three-dimensional integrated circuits (3D ICs) is critical for optimal design and performance. Experimental measurements also help validate thermal models for predicting the temperature field in a 3D IC. This paper presents results from thermal measurements on a two-die 3D IC. The experimental setup and procedure is described. Transient and steady-state measurements are made while heating the top die or the bottom die. Results indicate that passage of electrical current through the heaters in top/bottom die induces a measureable temperature rise. There appears to be a unique asymmetry in thermal performance between the top die and the bottom die. The top die is found to heat up faster and more than the bottom die. Results presented in this paper are expected to play a key role in validation of simulation-based and analytical thermal models for 3D ICs, and lead to a better fundamental understanding of heat transport in stacked systems. This is expected to lead to effective thermal design and characterization tools for 3D ICs.

Copyright © 2013 by ASME



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