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Inelastic Thermal Stress Simulation for Si Chip and Insulator Around TSV in 3D SiP

[+] Author Affiliations
Takahiro Kinoshita, Takashi Kawakami, Takeshi Wakamatsu, Shunpei Shima

Toyama Prefectural University, Toyama, Japan

Keiji Matsumoto, Sayuri Kohara, Fumiaki Yamada, Yasumitsu Orii

Association of Super-Advanced Electronics Technologies, Tokyo, Japan

Paper No. IPACK2013-73151, pp. V001T04A009; 4 pages
  • ASME 2013 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems
  • Volume 1: Advanced Packaging; Emerging Technologies; Modeling and Simulation; Multi-Physics Based Reliability; MEMS and NEMS; Materials and Processes
  • Burlingame, California, USA, July 16–18, 2013
  • Conference Sponsors: Electronic and Photonic Packaging Division
  • ISBN: 978-0-7918-5575-1
  • Copyright © 2013 by ASME


Stresses and mechanical strength of brittle materials (Si chip and insulator) around TSV (Through Silicon Via) structures in 3D SiP (Three Dimensional System in Package) were discussed under device operation condition and reflow process condition by using a large scale simulator ADVENTURECluster®, which was based on FEM (Finite Element Method), for ensuring the reliability of 3D SiP.

In case of the device operation, the equivalent stress of TSV were lower than yield stress of copper, and the maximum principal stress of Si and insulator were also lower than its bending strength. In case of the reflow process, the equivalent stress of TSV were over the yield stress of copper, and the maximum principal stresses of Si and insulator were closed to its bending strength. In addition, steep stress elevations were shown at edge part of Si and insulator. It will be a singular stress field by stress concentration. Its stress singularity was evaluated and the local strength of Si chip and insulator was discussed.

Copyright © 2013 by ASME



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