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Measurement of Microprocessor Die Stress due to Thermal Cycling, Power Cycling, and Second Level Assembly

[+] Author Affiliations
Jordan C. Roberts, Mohammad Motalab, Safina Hussain, Jeffrey C. Suhling, Richard C. Jaeger, Pradeep Lall

Auburn University, Auburn, AL

Paper No. IPACK2013-73244, pp. V001T01A005; 11 pages
doi:10.1115/IPACK2013-73244
From:
  • ASME 2013 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems
  • Volume 1: Advanced Packaging; Emerging Technologies; Modeling and Simulation; Multi-Physics Based Reliability; MEMS and NEMS; Materials and Processes
  • Burlingame, California, USA, July 16–18, 2013
  • Conference Sponsors: Electronic and Photonic Packaging Division
  • ISBN: 978-0-7918-5575-1
  • Copyright © 2013 by ASME

abstract

In the current work, we have extended our past studies on Flip Chip Ceramic Ball Grid Array (FC-BGA) microprocessor packaging configurations to investigate in-situ die stress variation during thermal and power cycling. The utilized (111) silicon sensor rosettes were able to measure the complete three-dimensional stress state (all 6 stress components) at each sensor site being monitored by the data acquisition hardware. The test chips had dimensions of 20 × 20 mm, and 3600 lead free solder interconnects (full area array) were used to connect the chips to high CTE ceramic chip carriers. A unique package carrier was developed to allow measurement of the die stresses in the FC-CBGA components under thermal and power cycling loads without inducing any additional mechanical loadings.

Initial experiments consisted of measuring the die stress levels while the components were subjected to a slow (quasi-static) temperature changes from 0 to 100 C. In later testing, long term thermal cycling of selected parts was performed from 0 to 100 C (40 minute cycle, 10 minute ramps and dwells). After various durations of cycling, the sensor resistances at critical locations on the die device surface (e.g. die center and die corners) were recorded. From the resistance data, the stresses at each site were calculated and plotted versus time. Finally, thermal and power cycling of selected parts was performed, and in-situ measurements of the transient die stress variations were performed. Power cycling was implemented by exciting the on-chip heaters on the test chips with various power levels. During the thermal/power cycling, sensor resistances at critical locations on the die device surface (e.g. die center and die corners) were recorded continuously. From the resistance data, the stresses at each site were calculated and plotted versus time.

Copyright © 2013 by ASME
Topics: Manufacturing , Stress

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