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Early Power Delivery Analysis of Bump Depopulation

[+] Author Affiliations
Houle Gan, Krishna Bharath

Intel Corp., Chandler, AZ

Paper No. IPACK2013-73119, pp. V001T01A002; 5 pages
doi:10.1115/IPACK2013-73119
From:
  • ASME 2013 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems
  • Volume 1: Advanced Packaging; Emerging Technologies; Modeling and Simulation; Multi-Physics Based Reliability; MEMS and NEMS; Materials and Processes
  • Burlingame, California, USA, July 16–18, 2013
  • Conference Sponsors: Electronic and Photonic Packaging Division
  • ISBN: 978-0-7918-5575-1
  • Copyright © 2013 by ASME

abstract

In this paper, a modeling flow has been developed for the analysis of large-area die-package power delivery networks. The analysis is implemented in an early pathfinding phase of a product development cycle so that technology options such as bump pitch and pattern can be defined before the real physical design is completed. The flow utilizes a popular commercially available on-die power delivery simulator, combined with a suite of custom software developed internally, and delivers worst-case static and dynamic voltage drops across a sufficiently representative portion of the die (larger than 1mm2 and with full silicon metal stack). Scenarios of different bump depopulation are then compared and any potential power delivery risk is identified. The flow has been employed to analyze the power delivery problem of a realistic on-die region containing logics from graphics block, where the impact of increasing levels of bump depopulation due to encroachment from adjacent I/O circuits was studied. Results have shown the effectiveness and efficiency of the proposed flow.

Copyright © 2013 by ASME

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