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3D Thermal Resistance Network Method for the Design of Highly Integrated Packages

[+] Author Affiliations
Lauren Boteler

U. S. Army Research Laboratory, Adelphi, MD

Andrew Smith

U. S. Naval Academy, Annapolis, MD

Paper No. HT2013-17575, pp. V003T10A009; 9 pages
  • ASME 2013 Heat Transfer Summer Conference collocated with the ASME 2013 7th International Conference on Energy Sustainability and the ASME 2013 11th International Conference on Fuel Cell Science, Engineering and Technology
  • Volume 3: Gas Turbine Heat Transfer; Transport Phenomena in Materials Processing and Manufacturing; Heat Transfer in Electronic Equipment; Symposium in Honor of Professor Richard Goldstein; Symposium in Honor of Prof. Spalding; Symposium in Honor of Prof. Arthur E. Bergles
  • Minneapolis, Minnesota, USA, July 14–19, 2013
  • Conference Sponsors: Heat Transfer Division
  • ISBN: 978-0-7918-5549-2


There is a continual market pull in the electronics industry for smaller products with more capabilities, creating a growing need for 3D stacked electronics. This work presents a generic, easy to use approach, to estimate the thermal performance in a generic NxMxP stack using 3D heterogeneous integrated packaging (3D HIP) approach as a baseline. 3D HIP is a microfabrication packaging technology that helps facilitate chip stacking. While this work is demonstrated utilizing the 3D HIP geometry, the technique is easily adapted to most packaging approaches, both 3D and planar. A low order model has been developed with a combination numerical-analytical approach and a 3D resistor network to estimate the chip temperatures. The resistor network solves quickly in MATLAB, enabling fast, iterative thermal analyses and design through the parametric studies of the chip dimensions, number of chips, chip layout, material types, cooling solutions, etc. The model has been validated against full 3D numerical models in COMSOL for a number of conditions including variation of chip dimensions, substrate thickness, number of chips, and material types. The temperature difference between the resistor network model and the COMSOL model was always within 5%. This method can be utilized to identify potential cooling approaches based on the power dissipation per chip and the packaging approach and also to determine the maximum temperatures of each chip. The code achieves significant time saving as compared to full FEA models while providing similar results.



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