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FCBGA Footprints and Solder Joint Reliability

[+] Author Affiliations
Frank Z. Liang, Rick L. Williams

Intel Corporation

Paper No. IMECE2004-60041, pp. 371-375; 5 pages
doi:10.1115/IMECE2004-60041
From:
  • ASME 2004 International Mechanical Engineering Congress and Exposition
  • Electronic and Photonic Packaging, Electrical Systems Design and Photonics, and Nanotechnology
  • Anaheim, California, USA, November 13 – 19, 2004
  • Conference Sponsors: Electronic and Photonic Packaging Division
  • ISBN: 0-7918-4707-1 | eISBN: 0-7918-4178-2, 0-7918-4179-0, 0-7918-4180-4
  • Copyright © 2004 by ASME

abstract

As electronic package input/output density increases and cost constraints drive the package size smaller, the one area where a designer can not compromise is solder joint reliability. Maintaining flip chip ball grid array (FCBGA) solder joint reliability (SJR) has been at the top of the designer’s critical list with decreasing package size. The FCBGA footprint will need to be modified for a variety of reasons to meet routing optimization, power delivery, electrical performance to name a few. The designer must deal with several competing proposals (electrical performance, cost and use conditions) trying to optimize the FCBGA footprint while being aware that some modifications can negatively affect SJR. This paper investigates solder ball layouts and their effect on SJR through both finite element (FE) models and empirical tests. In addition, consideration of next generation layout is presented to optimize routability while preserving SJR. When feasible, empirical tests were run to validate predictive models.

Copyright © 2004 by ASME

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