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Nanoscale Heat Conduction in the SOI, Strained-Si and Tri-Gate Transistors

[+] Author Affiliations
Mehdi Asheghi

Carnegie Mellon University, Pittsburgh, PA

Paper No. NANO2004-46050, pp. 33-36; 4 pages
doi:10.1115/NANO2004-46050
From:
  • ASME 2004 3rd Integrated Nanosystems Conference
  • Design, Synthesis, and Applications
  • Pasadena, California, USA, September 22–24, 2004
  • Conference Sponsors: Nanotechnology Institute
  • ISBN: 0-7918-4177-4 | eISBN: 0-7918-3749-1
  • Copyright © 2004 by ASME

abstract

There have been many attempts in the recent years to improve the device performance by enhancing carrier mobility by using the strained-induced changes in silicon electronic bands [1–4] or reducing the junction capacitance in silicon-on-insulator (SOI) technology. Strained silicon on insulator (SSOI) is another promising technology, which is expected to show even higher performance, in terms of speed and power consumption, comparing to the regular strained-Si transistors. In this technology, the strained silicon is incorporated in the silicon on insulator (SOI) technology such that the strained-Si introduces high mobility for electrons and holes and the insulator layer (usually SiO2 ) exhibits low junction capacitance due to its small dielectric constant [5, 6]. In these devices a layer of SiGe may exist between the strined-Si layer and insulator (strained Si-on-SiGe-on-insulator, SGOI) [6] or the strained-Si layer can be directly on top of the insulator [7]. Latter is advantageous for eliminating some of the key problems associated with the fabrication of SGOI.

Copyright © 2004 by ASME

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