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Thermal Performance Improvement of Through Silicon Via (TSV) Technology on 3-D Stack Packages

[+] Author Affiliations
Wei-Shen Kuo, Mingzong Wang, Eason Chen, Jeng-Yuan Lai, Yu-Po Wang

Siliconware Precision Industries Co., Ltd., Taichung, Taiwan

Paper No. IMECE2008-67240, pp. 1523-1526; 4 pages
  • ASME 2008 International Mechanical Engineering Congress and Exposition
  • Volume 10: Heat Transfer, Fluid Flows, and Thermal Systems, Parts A, B, and C
  • Boston, Massachusetts, USA, October 31–November 6, 2008
  • Conference Sponsors: ASME
  • ISBN: 978-0-7918-4871-5 | eISBN: 978-0-7918-3840-2
  • Copyright © 2008 by ASME


With electronic package tends to be lighter, thinner and smaller, the stacking of the many chips in the 3-D stack packages become more and more popular package. However, the stacking of the multi-function chips in the 3-D stack packages will result in high thermal dissipation. Thermal management has turned into one of the most primary challenge of semiconductor designers. The new technology is required to remove the heat effectively. 3-D stacked package with Through Silicon Via (TSV) technology is developed for two chips in a package. Electrical connections in the silicon interposer are formed by TSV. The silicon interposer has better thermal conductivity than that without interposer, therefore the package thermal resistance is lower. In this paper, thermal evaluations on Flip-Chip Ball Grid Array (FC-BGA) packages were presented using CFD modeling technique. The evaluation topics covered impact of Through Silicon Via (TSV) and dummy bumps, various power consumption, die size and package size effects. Besides, the thermal performance of the package would be decided by thermal conductivity of under fill. Finally, thermal suggestions were concluded for designers to design in TSV arrangements to effectively dissipate hot source.

Copyright © 2008 by ASME
Topics: Silicon



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