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Cu Pillar Bump FCBGA Package Design and Reliability Assessments

[+] Author Affiliations
Nicholas Kao, Yen-Chang Hu, Yuan-Lin Tseng, Eason Chen, Jeng-Yuan Lai, Yu-Po Wang

Siliconware Precision Industries Co., Ltd., Taichung, Taiwan

Paper No. IMECE2008-69019, pp. 177-182; 6 pages
  • ASME 2008 International Mechanical Engineering Congress and Exposition
  • Volume 6: Electronics and Photonics
  • Boston, Massachusetts, USA, October 31–November 6, 2008
  • Conference Sponsors: ASME
  • ISBN: 978-0-7918-4867-8 | eISBN: 978-0-7918-3840-2
  • Copyright © 2008 by ASME


With the trend of electronic consumer product toward more functionality, high performance and miniaturization, IC chip is required to deliver more Input/Output (I/O) and better electrical characteristics under same package form factor. Flip Chip BGA (FCBGA) package was developed to meet those requirements offering better electrical performance, more I/O pin accommodation and high transmission speed. However, the flip chip technology is encountering its structure limitation as the bump pitch is getting smaller and smaller because the spherical geometry bump shape is to limit the fine bump pitch arrangement and it’s also difficult to fill by underfill between narrow gaps. As this demand, a new fine bump pitch technology is developed as “Cu pillar bump” with the structure of Cu post and solder tip. The Cu pillar bump is plating process manufactured structure and composes with copper cylinder (Cu post) and mushroom shape solder cap (Solder tip). The geometry of Cu pillar bump not only provides a finer bump pitch, but also enhances the thermal performances due to the higher conductivity than conventional solder material. This paper mainly characterized the Cu pillar bump structure stress performances of FCBGA package to prevent reliability failures by finite element models. First, the bump stress and Cu/low-k stress of Cu pillar bump were studied to compare with conventional bump structure. The purpose is to investigate the potential reliability risk of Cu pillar bump structure. Secondly, the bump stress and Cu/low-k stress distribution were evaluated for different Polyimide (PI) layer, Under Bump Metallization (UBM) size and solder mask opening (SMO) size. This study can show the stress contribution of each design factor. Thirdly, a matrix which combination UBM size, Cu post thickness, SMO size, PI opening and PI thickness were studied to observe the stress distribution. Finally, the stress simulation results were experimentally validated by reliability tests.

Copyright © 2008 by ASME



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