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A Heterogeneous System-Level Power Macro-Modeling for Network-on-Chip Router

[+] Author Affiliations
Ning Wu, Fang Zhou, Ying Zhang, Fen Ge

Nanjing University of Aeronautics and Astronautics, Nanjing, China

Paper No. DETC2011-48908, pp. 47-52; 6 pages
doi:10.1115/DETC2011-48908
From:
  • ASME 2011 International Design Engineering Technical Conferences and Computers and Information in Engineering Conference
  • Volume 3: 2011 ASME/IEEE International Conference on Mechatronic and Embedded Systems and Applications, Parts A and B
  • Washington, DC, USA, August 28–31, 2011
  • Conference Sponsors: Design Engineering Division and Computers and Information in Engineering Division
  • ISBN: 978-0-7918-5480-8
  • Copyright © 2011 by ASME

abstract

A heterogeneous macro-model for power extraction of the Network-on-Chip router at system level is proposed, with higher accuracy to overcome the shortcoming of existing architecture-level power simulators, which is aimed to evaluate the network performance rapidly and guide the communication structure design. Each module of the router is modeled by different methods according to different characteristics. The input/output ports, the routing algorithm and the crossbar switch are established by multiple linear regression because of their single data flow state. The arbiter is established based on BP neural network due to its numerous states. Several experiments with different traffic loads and input sequences are carried out to verify the power model. Experimental results show that our power model is higher speed over the gate-level simulation, and the average estimation error is 5.0%. As a case study, we use the proposed model to evaluate the performance of different core mappings for H.264 decoder in system-level low power design.

Copyright © 2011 by ASME
Topics: Modeling , Networks

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