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Stresses in Area Array Assemblies Subjected to Thermal Cycling

[+] Author Affiliations
Jordan Roberts, M. Kaysar Rahim, Safina Hussain, Jeffrey C. Suhling, Richard C. Jaeger, Pradeep Lall

Auburn University, Auburn, AL

Paper No. IMECE2009-11925, pp. 267-278; 12 pages
doi:10.1115/IMECE2009-11925
From:
  • ASME 2009 International Mechanical Engineering Congress and Exposition
  • Volume 5: Electronics and Photonics
  • Lake Buena Vista, Florida, USA, November 13–19, 2009
  • Conference Sponsors: ASME
  • ISBN: 978-0-7918-4378-9 | eISBN: 978-0-7918-3863-1
  • Copyright © 2009 by ASME

abstract

Thermal cycling accelerated life testing is often used to qualify area array packages (e.g. Ball Grid Arrays and Flip Chip) for various applications. Finite element life predictions for thermal cycling configurations are challenging due to the complicated temperature/time dependent constitutive relations and failure criteria needed for solders and encapsulants and their interfaces, aging/evolving material behavior (e.g. solders), difficulties in modeling plating finishes, the complicated geometries of typical electronic assemblies, etc. In addition, in-situ measurements of stresses and strains in assemblies subjected to temperature cycling is difficult because of the extreme environmental conditions and the fact that the primary materials/interfaces of interest (e.g. solder joints, die device surface, wire bonds, etc.) are embedded within the assembly (not at the surface). For these reasons, we really know quite little about the evolution of the stresses, strains, and deformations occurring within sophisticated electronic packaging geometries during thermal cycling. In our research, we are using test chips containing piezoresistive stress sensors to continuously characterize the in-situ die surface stress during long-term thermal cycling of several different area array packaging technologies including plastic ball grid array (PBGA) components, ceramic ball grid array (CBGA) components, and flip chip on laminate assemblies. The utilized (111) silicon test chips are able to measure the complete three-dimensional stress state (all 6 stress components) at each sensor site being monitored by the data acquisition hardware. The die stresses are initially measured at room temperature after packaging. The assemblies are then subjected to thermal cycling over various temperature ranges including 0 to 100 °C, −40 to 125 °C, and −55 to 125 °C, for up to 3000 thermal cycles. During the thermal cycling, sensor resistances at critical locations on the die device surface (e.g. the die center and die corners) are recorded. From the resistance data, the stresses at each site can be calculated and plotted versus time. The experimental observations show significant cycle-to-cycle evolution in the stress magnitudes due to material aging effects, stress relaxation and creep phenomena, and development of interfacial damage. The observed stress variations as a function of thermal cycling duration are also being correlated with the observed delaminations at the die surface (as measured using scanning acoustic microscopy (C-SAM)) and finite element simulations that include material constitutive models that incorporate thermal aging effects.

Copyright © 2009 by ASME
Topics: Stress

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