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Nanotopography in Silicon Wafer Manufacturing: A Literature Review

[+] Author Affiliations
Na Qin

Dalian University of Technology, Dalian, Liaoning, China; Kansas State University, Manhattan, KS

Z. J. Pei

Kansas State University, Manhattan, KS

D. M. Guo

Dalian University of Technology, Dalian, Liaoning, China

Paper No. MSEC2009-84201, pp. 721-728; 8 pages
doi:10.1115/MSEC2009-84201
From:
  • ASME 2009 International Manufacturing Science and Engineering Conference
  • ASME 2009 International Manufacturing Science and Engineering Conference, Volume 1
  • West Lafayette, Indiana, USA, October 4–7, 2009
  • Conference Sponsors: Manufacturing Engineering Division
  • ISBN: 978-0-7918-4361-1 | eISBN: 978-0-7918-3859-4
  • Copyright © 2009 by ASME

abstract

Nanotopograhphy on unpatterned silicon wafers is becoming a serious issue in IC fabrication, especially with the decreasing critical dimension. However, there are no review papers to summarize the literature on nanotopography in silicon wafer manufacturing. This paper reviews the literature on nanotopography in silicon wafer manufacturing. It first describes the significance and definition of nanotopography. It then presents the methods and principles of nanotopography measurement. It also discusses experimental investigations about the effects of simultaneous double side grinding process on nanotopography.

Copyright © 2009 by ASME

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