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An Economic Study on Chemical Mechanical Polishing of Silicon Wafers

[+] Author Affiliations
Emmanuel A. Baisie, Man Yang, Ravindra Kaware, Maria Hooker, Z. C. Li

North Carolina Agricultural & Technical State University, Greensboro, NC

Wangping Sun

Oregon Institute of Technology, Klamath Falls, OR

X. H. Zhang

Seagate Technology, Minneapolis, MN

Paper No. MSEC2009-84072, pp. 691-697; 7 pages
doi:10.1115/MSEC2009-84072
From:
  • ASME 2009 International Manufacturing Science and Engineering Conference
  • ASME 2009 International Manufacturing Science and Engineering Conference, Volume 1
  • West Lafayette, Indiana, USA, October 4–7, 2009
  • Conference Sponsors: Manufacturing Engineering Division
  • ISBN: 978-0-7918-4361-1 | eISBN: 978-0-7918-3859-4
  • Copyright © 2009 by ASME

abstract

Chemical mechanical polishing (CMP) is used to remove irregularities on the silicon wafer surface. The importance of CMP is the achievement of both local and global planarity of wafer surface. This paper presents an economic study on CMP of silicon wafers. A cost model is developed to predict the total cost for CMP of silicon wafers. An input-output model is developed to analyze parameters relevant to the fixed cost and variable cost. The labor cost is investigated through a flow chart of the labor operation. Based on the cost model, a hypothetical case study is conducted to show the model’s capability of performing sensitivity analysis and identifying critical factors for the total cost for strategic management purposes.

Copyright © 2009 by ASME

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