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Achievement of High Flatness of Large Diameter Silicon Wafer in Double-Sided Polishing: Optimization of Polishing Conditions Considering Relative Motion Direction

[+] Author Affiliations
Kenji Hirose, Toshiyuki Enomoto

Osaka University, Suita, Osaka, Japan

Paper No. MSEC2009-84055, pp. 671-676; 6 pages
  • ASME 2009 International Manufacturing Science and Engineering Conference
  • ASME 2009 International Manufacturing Science and Engineering Conference, Volume 1
  • West Lafayette, Indiana, USA, October 4–7, 2009
  • Conference Sponsors: Manufacturing Engineering Division
  • ISBN: 978-0-7918-4361-1 | eISBN: 978-0-7918-3859-4
  • Copyright © 2009 by ASME


Silicon (Si) wafers are the most commonly used substrates for manufacturing semiconductor devices. The design rule is miniaturized, and the chip size is increasing to improve the degree of the device integration. Then Si wafer is required to be manufactured with the higher flatness and larger diameter to meet above demands. The double-sided polishing is widely adopted as the finishing process of the wafer manufacturing, because the wafers with the good surface quality and flatness can be obtained economically. However, the polishing technology has serious problems: It is very difficult to set the appropriate conditions for stably polishing the Si wafer and wearing the pad to the high flatness. In our previous work, the optimization of the polishing conditions with the theoretical calculation was conducted, however, the calculation did not consider the relative motion direction having large influence on polishing behaviours. In this study, the optimizing method considering the relative motion direction was newly developed, and it was revealed that the calculation results corresponded well with the experimental results. Furthermore, it was found that the time-fluctuation of the wafer flatness was larger in the case of the wafer having taper shape, compared to that having convex shape in the calculation.

Copyright © 2009 by ASME



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