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Development of a Numerical Model for Non-Uniformly Powered Die to Improve Both Thermal and Device Clock Performance

[+] Author Affiliations
Saket Karajgikar, Dereje Agonafer

The University of Texas at Arlington, Arlington, TX

Kanad Ghose, Bahgat Sammakia

SUNY Binghamton, Binghamton, NY

Cristina Amon

University of Toronto, Toronto, ON, Canada

Gamal Refai-Ahmed

Advanced Micro Devices, Inc., Markham, ON, Canada

Paper No. InterPACK2009-89188, pp. 111-118; 8 pages
  • ASME 2009 InterPACK Conference collocated with the ASME 2009 Summer Heat Transfer Conference and the ASME 2009 3rd International Conference on Energy Sustainability
  • ASME 2009 InterPACK Conference, Volume 2
  • San Francisco, California, USA, July 19–23, 2009
  • Conference Sponsors: Electronic and Photonic Packaging Division
  • ISBN: 978-0-7918-4360-4 | eISBN: 978-0-7918-3851-8
  • Copyright © 2009 by ASME


Integration of different functional components such as level two (L2) cache memory, high-speed I/O interfaces, memory controller, etc. has enhanced microprocessor performance. In this architecture, certain functional units on the microprocessor dissipate a significant fraction of the total power while other functional blocks dissipate little or no power. This highly non-uniform power distribution results in a large temperature gradient with localized hot spots that may have detrimental effect on computer performance and product reliability as well as yield. Moving the functional blocks may reduce the junction temperature but can also affect the performance by a factor as high as 35%. In this paper, multi-objective optimization is performed to minimize the junction temperature without significantly altering the computer performance. From the results, the minimum and the maximum temperature was 82.4°C and 94.5°C with a corresponding penalty on the performance of 35% and 0% respectively. The optimized location of the functional blocks resulted in a temperature of 83.2°C for a performance loss of 5%.

Copyright © 2009 by ASME



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