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High-Density Room-Temperature 3D Chip-Stacking Using Mechanical Caulking With Compliant Bump and Through-Hole-Electrode

[+] Author Affiliations
Naoya Watanabe, Tanemasa Asano

Kyushu University, Fukuoka, Fukuoka, Japan

Michihiro Kawashita, Yasuhiro Yoshimura, Naotaka Tanaka

Hitachi Ltd., Hitachinaka, Ibaraki, Japan

Paper No. InterPACK2009-89274, pp. 33-38; 6 pages
doi:10.1115/InterPACK2009-89274
From:
  • ASME 2009 InterPACK Conference collocated with the ASME 2009 Summer Heat Transfer Conference and the ASME 2009 3rd International Conference on Energy Sustainability
  • ASME 2009 InterPACK Conference, Volume 1
  • San Francisco, California, USA, July 19–23, 2009
  • Conference Sponsors: Electronic and Photonic Packaging Division
  • ISBN: 978-0-7918-4359-8 | eISBN: 978-0-7918-3851-8
  • Copyright © 2009 by ASME

abstract

In this study, we employ a novel compliant bump in 3D chip-stacking using mechanical caulking. The compliant bump prepared in this work has a cone-like structure and is made of Au. It is fabricated using an “undercut resist method,” which combines undercut resist pattern formation with electroplating. The size of the compliant bump (approximately 10–30 μm in diameter) is much smaller than that of the stud bump. We demonstrate that by using a mechanical caulking process with a compliant bump and a through-hole-electrode, high-density through-hole-electrode interconnection (I/O number: 8,000, pitch: 20 μm) becomes possible, even at room temperature.

Copyright © 2009 by ASME

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