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Stress Measurement Errors in Flip Chip Packages Using Multi-Element Sensor Rosettes on (111) Silicon

[+] Author Affiliations
Richard C. Jaeger, Jeffrey C. Suhling, Safina Hussain, Jordan C. Roberts, Mohammad A. Motalab

Auburn University, Auburn, AL

Chun-Hyung Cho

Hongik University, Chungcheongnam-Do, South Korea

Paper No. InterPACK2009-89245, pp. 15-25; 11 pages
  • ASME 2009 InterPACK Conference collocated with the ASME 2009 Summer Heat Transfer Conference and the ASME 2009 3rd International Conference on Energy Sustainability
  • ASME 2009 InterPACK Conference, Volume 1
  • San Francisco, California, USA, July 19–23, 2009
  • Conference Sponsors: Electronic and Photonic Packaging Division
  • ISBN: 978-0-7918-4359-8 | eISBN: 978-0-7918-3851-8
  • Copyright © 2009 by ASME


Multi-element resistor rosettes on silicon are widely utilized to measure integrated circuit die stress in electronic packages and other applications. Previous analyses of many sources of error have led to rosette optimization and the realization that temperature compensated stress extraction should be used whenever possible. A previous paper initated a study of the errors in stress extraction due to the inherent uncertainty in knowledge of the values of the piezoresistive coefficients and temperature. In this work, we apply the earlier results to an analysis of the sensitivities and errors in the extracted stresses on an integrated circuit die in a flip-chip package. A finite-element model for a basic flip-chip configuration is utilized to estimate the stress across the surface of the silicon die. These results are used to evaluate the stress sensitivities to coefficient and temperature errors throughout the die surface. The sensitivities are stress dependent and vary widely from very small to very large over the die surface. The results confirm that temperature compensated rosette configurations should be utilized whenever possible.

Copyright © 2009 by ASME



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