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Copper Plating Process for Through Silicon Via With High Aspect Ratio in Advanced Packaging

[+] Author Affiliations
Yu Hung Huang, Huei-Huang Lee, Sheng-Jye Hwang

National Cheng Kung University, Tainan City, Taiwan

Durn-Yuan Huang

Chung Hwa University of Medical Technology, Tainan County, Taiwan

Paper No. InterPACK2009-89163, pp. 9-14; 6 pages
doi:10.1115/InterPACK2009-89163
From:
  • ASME 2009 InterPACK Conference collocated with the ASME 2009 Summer Heat Transfer Conference and the ASME 2009 3rd International Conference on Energy Sustainability
  • ASME 2009 InterPACK Conference, Volume 1
  • San Francisco, California, USA, July 19–23, 2009
  • Conference Sponsors: Electronic and Photonic Packaging Division
  • ISBN: 978-0-7918-4359-8 | eISBN: 978-0-7918-3851-8
  • Copyright © 2009 by ASME

abstract

Through silicon via (TSV) is a technology which allows devices to be connected three-dimensionally. Three dimensional vertical integration using TSV Cu interconnect can greatly increase the packaging density and is one of the most advanced and promising technologies for future IC packaging. However, Cu filling of void free through silicon via with high aspect ratio (AR≥10) has been a challenge for a long time. In this paper, successful fabrication of void free TSV with very high aspect ratio was demonstrated via electroplating process. Proper equipment and processing conditions for electroplating are required. The same equipment and similar chemicals and process conditions could also be applied to fabricate high quality redistribution line technology (RDL).

Copyright © 2009 by ASME

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