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Silicon Hot Spot Remediation With a Germanium Self Cooling Layer

[+] Author Affiliations
Horacio Nochetto, Peng Wang, Avram Bar-Cohen

University of Maryland, College Park, College Park, MD

Paper No. IPACK2011-52229, pp. 319-326; 8 pages
  • ASME 2011 Pacific Rim Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Systems
  • ASME 2011 Pacific Rim Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Systems, MEMS and NEMS: Volume 2
  • Portland, Oregon, USA, July 6–8, 2011
  • ISBN: 978-0-7918-4462-5
  • Copyright © 2011 by ASME


Driven by shrinking feature sizes, microprocessor hot spots have emerged as the primary driver for on-chip cooling of today’s IC technologies. Current thermal management technologies offer few choices for such on-chip hot spot remediation. A solid state germanium self-cooling layer, fabricated on top of the silicon chip, is proposed and demonstrated to have great promise for reducing the severity of on-chip hot spots. 3D thermo-electrical coupled simulations are used to investigate the effectiveness of a bi-layer device containing a germanium self-cooling layer above an electrically insulated silicon layer. The parametric variables of applied current, cooler size, silicon percentage, and total die thickness are sequentially optimized for the lowest hot spot temperature compared to a non-self-cooled silicon chip. Results suggest that the localized self-cooling of the germanium layer coupled with the higher thermal conductivity of the silicon chip can significantly reduce the temperature rise resulting from a micro-scaled hot spot.

Copyright © 2011 by ASME
Topics: Cooling , Germanium , Silicon



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