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An Investigation of Power Migration Policies for Many-Core Processors to Manage On-Chip Thermal Profile

[+] Author Affiliations
Man Prakash Gupta, Minki Cho, Saibal Mukhopadhyay, Satish Kumar

Georgia Institute of Technology, Atlanta, GA

Paper No. IPACK2011-52094, pp. 153-163; 11 pages
doi:10.1115/IPACK2011-52094
From:
  • ASME 2011 Pacific Rim Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Systems
  • ASME 2011 Pacific Rim Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Systems, MEMS and NEMS: Volume 2
  • Portland, Oregon, USA, July 6–8, 2011
  • ISBN: 978-0-7918-4462-5
  • Copyright © 2011 by ASME

abstract

Transition from single core to multicore technology has brought daunting challenge for thermal management of microprocessor chips. The issue of power dissipation in next generation chip will be far more critical as further transition from multicore to many-core processors is soon to be expected. It is very important to obtain uniform on-chip thermal profile with low peak temperature for improved performance and reliability of many-core processors. In this paper, a proactive thermal management technique called ‘power multiplexing’ is explored for many-core processors. Power multiplexing involves redistribution of locations of power dissipating cores at regular time intervals to obtain uniform thermal profile with low peak temperature. Three different migration policies namely random, cyclic and global coolest replace have been employed for power multiplexing and their efficacy in reducing the peak temperature and thermal gradient on chip is investigated. A comparative study of these policies has been performed enlisting their limits and advantages from the thermal and implementation perspective considering important relevant parameters such as migration frequency. For a given migration frequency, global coolest replace policy is found to be the most effective among the three policies considered as this policy leads to 10 °C reduction in peak temperature and 20 °C reduction in maximum spatial temperature difference on a 256 core chip. Proximity of active cores or power configuration on chip is characterized by a parameter ‘proximity index’ which emerges as an important parameter to represent the spatial power distribution on a chip. Global coolest replace policy optimizes the power map on chip taking care of not only the proximity of active cores but also the finite-size effect of chip and the 3D system of electronic package leading to almost uniform thermal profile on chip with lower average temperature.

Copyright © 2011 by ASME

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