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Power/Ground Pin-Map Design for Power Integrity

[+] Author Affiliations
Jingook Kim, James Drewniak, Jun Fan

Missouri University of Science and Technology, Rolla, MO

Paper No. IPACK2011-52287, pp. 675-679; 5 pages
doi:10.1115/IPACK2011-52287
From:
  • ASME 2011 Pacific Rim Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Systems
  • ASME 2011 Pacific Rim Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Systems, MEMS and NEMS: Volume 1
  • Portland, Oregon, USA, July 6–8, 2011
  • ISBN: 978-0-7918-4461-8
  • Copyright © 2011 by ASME

abstract

In this paper, a simple circuit model for IC multiple power and ground via arrays in a multilayer PCB is built based on the resonant cavity model. Using the circuit model, the parasitic inductance for the IC power and ground connection is quantitatively investigated according to via number and via patterns. The stack-up configuration of the power/ground plane pair is not critical for PDN performance in multilayer PCBs, as long as there are sufficient IC power/ground vias in an alternating pattern. The outcome of this work can be used to guide the pin-map design for high-speed packages.

Copyright © 2011 by ASME
Topics: Design

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