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An Accurate and Efficient Link Analysis Methodology for High Speed I/O Design

[+] Author Affiliations
Mohiuddin Mazumder, Sitaraman Iyer, Fulvio Spagna, Zuoguo Wu, Beomtaek Lee

Intel Corporation, Santa Clara, CA

James Jaussi

Intel Corporation, Hillsboro, OR

Arvind Kumar

Intel Corporation, Hudson, MA

Paper No. IPACK2011-52279, pp. 653-661; 9 pages
  • ASME 2011 Pacific Rim Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Systems
  • ASME 2011 Pacific Rim Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Systems, MEMS and NEMS: Volume 1
  • Portland, Oregon, USA, July 6–8, 2011
  • ISBN: 978-0-7918-4461-8
  • Copyright © 2011 by ASME


This paper describes an accurate and efficient analysis methodology that enables circuit optimization directly guided by platform-level metric such as link eye margin. Prior to this work, such analysis was not feasible due to significant compute time required by complex circuit simulations. A new method of developing highly abstracted behavioral models of complex circuit blocks is a critical element of this analysis methodology. The method uses statistical signaling analysis and optimization capabilities coupled with behavioral modeling of I/O clocking, transmitter and receiver circuitry that are based on accurate circuit simulations. We also present measured data from products and test chips that show correlation between measured and modeled data within 10–15%. Finally, we describe how the methodology was used to optimize the design of a high speed serial link and achieve approximately 70% improvement in eye margins with limited design iterations.

Copyright © 2011 by ASME
Topics: Design



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