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Signal and Power Integrity Co-Simulation on DDR Memory

[+] Author Affiliations
Md. Ruhul Quddus

Intel Corporation, Hillsboro, OR

Sanjiv Soman

Intel Corporation, Dupont, WA

Paper No. IPACK2011-52274, pp. 641-646; 6 pages
  • ASME 2011 Pacific Rim Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Systems
  • ASME 2011 Pacific Rim Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Systems, MEMS and NEMS: Volume 1
  • Portland, Oregon, USA, July 6–8, 2011
  • ISBN: 978-0-7918-4461-8
  • Copyright © 2011 by ASME


Even though it has always been known that Signal Integrity analysis and Power Integrity (Power Delivery) analysis are related, historically they have been treated and analyzed independently with some timing and voltage buckets used to tie the effects of one on the other. When the voltage and timing margins were large, this approach worked quite well. However as voltage levels, timing windows and their margins have shrunk, the traditional method of analyzing them independently no longer suffices. The signal quality and timing (eye height & eye width) losses due to the effects of power delivery are no longer negligible. The concept of signal integrity & power delivery co-simulation (referred to as SIPD or SIPI co-sim) is a methodology developed to address this problem. In this paper we will use the DDR bus as an example to illustrate the impacts of power delivery on the signal and highlight how badly the margin loss would have been underestimated if the effects of power delivery were ignored. The paper will demonstrate how SIPD co-sim can quantify or illustrate - the effects of data randomization, margin gain with fully random data patterns, margin loss due to the effects of Burst-Idle-Burst data patterns, definition of noise & eye diagram BER, statistically significant noise in system, etc.

Copyright © 2011 by ASME
Topics: Simulation , Signals



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