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Nature of Package-Induced Deformation and the Risk of Fracture in Low-k Dielectric Stacks

[+] Author Affiliations
Hung-Yun Lin, Abhishek Tambat, Ganesh Subbarayan

Purdue University, West Lafayette, IN

Ian Claydon, Dae Young Jung, Bahgat Sammakia

Binghamton University, Binghamton, NY

Paper No. IPACK2011-52258, pp. 351-356; 6 pages
  • ASME 2011 Pacific Rim Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Systems
  • ASME 2011 Pacific Rim Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Systems, MEMS and NEMS: Volume 1
  • Portland, Oregon, USA, July 6–8, 2011
  • ISBN: 978-0-7918-4461-8
  • Copyright © 2011 by ASME


The risk of fracture in Interlayer Dielectric (ILD) stack is evaluated for various configurations of flip-chip packages in this paper. A novel analysis on the mechanical behavior of package with a focus on die surface provides the insights into the critical deformation state as well as its location. In Controlled Collapse Chip Connection (C4) process, the reflow phase involves a cooling of the entire package from the reflow temperature to room temperature, and is critical for package induced die cracking (Chip-Package Interaction or CPI). We use commercial finite element software ABAQUS to construct local sub-models of ILD region from global models of a representative 3-D package with component materials modeled as being temperature dependent elastic or elasto-plastic as appropriate. The risk of ILD fracture is systematically investigated using the described approach.

Copyright © 2011 by ASME



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