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Thermal Stress of Through Silicon Vias and Si Chips in 3D SiP

[+] Author Affiliations
Takahiro Kinoshita, Takashi Kawakami, Tatsuhiro Hori

Toyama Prefectural University, Toyama, Japan

Keiji Matsumoto, Sayuri Kohara, Yasumitsu Orii, Fumiaki Yamada, Morihiro Kada

Association of Super-Advanced Electronics Technologies, Tokyo, Japan

Paper No. IPACK2011-52241, pp. 325-328; 4 pages
doi:10.1115/IPACK2011-52241
From:
  • ASME 2011 Pacific Rim Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Systems
  • ASME 2011 Pacific Rim Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Systems, MEMS and NEMS: Volume 1
  • Portland, Oregon, USA, July 6–8, 2011
  • ISBN: 978-0-7918-4461-8
  • Copyright © 2011 by ASME

abstract

Thermal conduction and mechanical strength around TSV (Through Silicon Via) structures of 3D SiP (Three Dimensional System in Package) were discussed both cases of with and without void in TSV by using a large scale simulator based on FEM, ADVENTURECluster® for ensuring the reliability of 3D SiP. In the results, the thermal performance that was required in 3D SiP was estimated to ensure the reliability. Simulations for thermal stresses around TSV structure in 3D SiP under thermal cycle condition due to power ON/OFF were carried out. In case that void was not in TSV, stresses in TSV were close to hydrostatic pressure and the magnitude of the equivalent stress was lower than the yield stress of copper. However, the level of the stresses, especially in Si chips, should not be negligible in inducing damages to TSVs and Si single crystals. In case that void was in TSV, stress was concentrated around void in TSV and the magnitude of the equivalent stress was lower than the yield stress of copper. The level of stresses applied to Si chip was slightly reduced due to void in TSV. However, its level should not be negligible in inducing damages to TSVs and Si single crystals.

Copyright © 2011 by ASME

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