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Effects of TSV Interposer on the Reliability of 3D IC Integration SiP

[+] Author Affiliations
John H. Lau

Industrial Technology Research Institute (ITRI), Hsinchu, Taiwan

Xiaowu Zhang

Institute of Microelectronics (IME), Singapore

Paper No. IPACK2011-52205, pp. 65-73; 9 pages
doi:10.1115/IPACK2011-52205
From:
  • ASME 2011 Pacific Rim Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Systems
  • ASME 2011 Pacific Rim Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Systems, MEMS and NEMS: Volume 1
  • Portland, Oregon, USA, July 6–8, 2011
  • ISBN: 978-0-7918-4461-8
  • Copyright © 2011 by ASME

abstract

The effect of Cu-filled through-silicon vias (TSVs) interposers on the reliability of 3D IC integration system-in-package (SiP) is investigated in this study. Emphasis is placed on the determination of the stresses at the Cu-low-k pads on a Moore’s law chip and the creep strain energy density per cycle at the corner solder joints between the Moore’s law chip and an interposer. Also, thermal cycling tests and failure analysis results of a test vehicle is presented and discussed.

Copyright © 2011 by ASME
Topics: Reliability

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