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Modeling and Designing a Device Using MuGFETs

[+] Author Affiliations
V. K. Lamba

HCTM Kaithal, Kaithal, Haryana, India

Derick Engles, S. S. Malik

Guru Nanak Dev University, Amritsar, Punjab, India

Paper No. ENIC2008-53015, pp. 89-93; 5 pages
doi:10.1115/ENIC2008-53015
From:
  • ASME 2008 3rd Energy Nanotechnology International Conference collocated with the Heat Transfer, Fluids Engineering, and Energy Sustainability Conferences
  • ASME 2008 3rd Energy Nanotechnology International Conference
  • Jacksonville, Florida, USA, August 10–14, 2008
  • Conference Sponsors: Nanotechnology Institute
  • ISBN: 0-7918-4323-9 | eISBN: 0-7918-3832-3
  • Copyright © 2008 by ASME

abstract

This work describes computer simulations of various, Silicon on Insulator (SOI) Metal Oxide Semiconductor Field Effect Transistor (MOSFETs) with double and triple-gate structures, as well as gate-all-around devices. To explore the optimum design space for four different gate structures, simulations were performed with four variable device parameters: gate length, channel width, doping concentration, and silicon film thickness. The efficiency of the different gate structures is shown to be dependent of these parameters. Here short-channel properties of multi-gate SOI MOSFETs (MuGFETs) are studied by numerical simulation. The evolution of characteristics such as Drain induced barrier lowering (DIBL), sub-threshold slope, and threshold voltage roll-off is analyzed as a function of channel length, silicon film or fin thickness, gate dielectric thickness and dielectric constant, and as a function of the radius of curvature of the corners. The notion of an equivalent gate number is introduced. As a general rule, increasing the equivalent gate number improves the short-channel behavior of the devices. Similarly, increasing the radius of curvature of the corners improves the control of the channel region by the gate.

Copyright © 2008 by ASME
Topics: Design , Modeling

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