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Fabrication of Nanoscale Vias by Offset Patterning

[+] Author Affiliations
Chi Ho Lau, S. W. Ricky Lee

Hong Kong University of Science and Technology, Clear Water Bay, Kowloon, Hong Kong, China

Paper No. MicroNano2008-70131, pp. 615-618; 4 pages
  • 2008 Second International Conference on Integration and Commercialization of Micro and Nanosystems
  • 2008 Second International Conference on Integration and Commercialization of Micro and Nanosystems
  • Clear Water Bay, Kowloon, Hong Kong, June 3–5, 2008
  • Conference Sponsors: Nanotechnology Institute
  • ISBN: 0-7918-4294-0 | eISBN: 0-7918-3819-6
  • Copyright © 2008 by ASME


Patterning of features with photolithography technique by overlying multiple exposure patterns with intentional offset reduces the effective size of the resultant opening when the openings overlap incompletely. The size of resultant opening depends on the size of the parental opening and the degree of overlap. Overlapping via patterns helps to achieve small via size from photolithography. In the present study, two oxide layers with via pattern were involved. The bottom oxide layer was deposited and patterned first. The top oxide layer and the poly-Si sandwich layer were then deposited on the patterned bottom oxide layer and patterned with an offset afterwards. Experimental results show resultant vias with size reduction by more than 50% compared with the parental vias. The equivalent diameter of the resultant vias goes down to as small as 400 nm. It was found that the equivalent diameter decreases with reduction in parental via size. The length-to-width ratio of the resultant vias opening increases as the parental via size becomes larger. The offset distance is also found to contribute significant effect to the size of the resultant via. The large offset distance leads to small but high-aspect ratio resultant vias.

Copyright © 2008 by ASME



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