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Hermetic Packaging Technique Featuring Through-Wafer Interconnects and Low Temperature Direct Bond

[+] Author Affiliations
James Lee, Tony Rogers

Applied Microengineering Limited, Didcot, Oxfordshire, UK

Paper No. MicroNano2008-70288, pp. 107-112; 6 pages
doi:10.1115/MicroNano2008-70288
From:
  • 2008 Second International Conference on Integration and Commercialization of Micro and Nanosystems
  • 2008 Second International Conference on Integration and Commercialization of Micro and Nanosystems
  • Clear Water Bay, Kowloon, Hong Kong, June 3–5, 2008
  • Conference Sponsors: Nanotechnology Institute
  • ISBN: 0-7918-4294-0 | eISBN: 0-7918-3819-6
  • Copyright © 2008 by ASME

abstract

A novel wafer level packaging method suitable for low production volumes, R&D, and multi-project wafers is presented, providing a hermetic seal suitable for vacuum encapsulation with wafers bonded at a low temperature. Hermetic through-wafer interconnects are bump bonded to a CMOS chip encapsulated by bonding a cap wafer after activating surfaces with free radicals, the Silicon-Silicon direct bond is then annealed to a high strength at 200°C to avoid chip damage. The application for which this system is proposed is an implantable multi-contact active nerve electrode for the treatment of epilepsy via vagus nerve stimulation. Although intended for human implantation of integrated systems, this technology may be applied across a range of devices requiring hermetic or vacuum sealing and through-wafer interconnection. Solid electroplated through-wafer interconnects (aspect ratio 5) enable hermetic interconnection of direct bonded packages with low connection impedance, offering benefits across a range of packaging applications. A key feature of this packaging method is it’s versatility, the proposed embodiment features chip to wafer bonding with an ASIC, but the package is equally suitable for MEMS devices and also for wafer to wafer bonding.

Copyright © 2008 by ASME

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