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Laser Ultrasonic Inspection of Solder Bumps in Flip Chip Packages Using Virtual Package Device as Reference

[+] Author Affiliations
I. Charles Ume, Jie Gong, Razid Ahmad, Abel Valdes

Georgia Institute of Technology, Atlanta, GA

Paper No. IMECE2010-39970, pp. 507-516; 10 pages
doi:10.1115/IMECE2010-39970
From:
  • ASME 2010 International Mechanical Engineering Congress and Exposition
  • Volume 4: Electronics and Photonics
  • Vancouver, British Columbia, Canada, November 12–18, 2010
  • Conference Sponsors: ASME
  • ISBN: 978-0-7918-4428-1
  • Copyright © 2010 by ASME

abstract

Flip chip package is widely used in the electronic device manufacturing industry. The top side of a flip chip device is manufactured with solder bumps. The device is then flipped on its top so that the solder bumps can be bonded to a substrate, forming the mechanical and electrical connection between the device and substrate. As a result, the solder bumps are sandwiched between the silicon die and the substrate, making them no longer visible for usual inspection. A novel solder joint inspection system capable of evaluating the quality of the hidden solder bumps on a flip chip package has been developed using laser ultrasound techniques. The system pulses a laser onto the top surface of a chip package to generate ultrasonic waves in the package and excite structural vibrations which can then be measured using an interferometer. Since defective solder bumps cause changes in the transient vibration response of a tested sample, quality of the tested sample can be assessed by correlating its vibration responses to that of a known good device. A limitation of this implementation is the necessity of a known-good reference chip package, which typically involves expensive testing using alternate methods. In this paper, the development of a method capable of generating a virtual reference chip package is presented. This method, called Hybrid Reference Method, uses a statistical approach to find which packages in a sample set are most similar and then averages their time domain signals to generate a virtual chip package, known as the Hybrid Reference Package. The signals associated with Hybrid Reference Package are then correlated with the time domain signals obtained from the packages under inspection to obtain a quality signature. Finally, defective and non-defective chip packages are separated by estimating a beta distribution that fits the quality signature histogram of the inspected packages and then determining a cutoff threshold for an acceptable quality signature. This method was applied to two types of flip chip packages where no pre-established known-good reference package was available. The results of this quality analysis were validated by comparison with electrical test and X-ray results.

Copyright © 2010 by ASME

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