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Thermal-Aware Power Migration in Many-Core Processors

[+] Author Affiliations
Avinash Raghu, Saket Karajgikar, Dereje Agonafer

The University of Texas at Arlington, Arlington, TX

Bahgat Sammakia

Binghamton University, State University of New York, Vestal, NY

Gamal Refai-Ahmed

Advanced Micro Devices, Inc., Sunnyvale, CA

Paper No. IMECE2010-40232, pp. 385-392; 8 pages
doi:10.1115/IMECE2010-40232
From:
  • ASME 2010 International Mechanical Engineering Congress and Exposition
  • Volume 4: Electronics and Photonics
  • Vancouver, British Columbia, Canada, November 12–18, 2010
  • Conference Sponsors: ASME
  • ISBN: 978-0-7918-4428-1
  • Copyright © 2010 by ASME

abstract

The demand for greater performance in applications involving high levels of parallelism and sequential computation, has led to an increase in design complexity, has rendered the single-core processor obsolete for such applications and resulted in more cores being put onto a single chip. While improving performance, this has lead to increased power densities and, consequently, increased die temperature. Also, the power distribution across the die surface is not uniform, resulting in hot spots. The increase in die temperature results in decreased performance and reliability and increased leakage currents and cooling costs. Spreading activity across a multi-core chip is increasingly being considered as a way to contain chip temperatures while minimally degrading performance. This paper investigates power migration, or “core hopping,” which involves dynamic allocation of workload among the cores on a many-core processor. This work numerically analyzed core hopping for different configurations of a many-core processor, and performed the migration based on both time of activity and temperature of individual cores. Based on the analysis, this work demonstrated a notable drop in junction temperature of about 8°C.

Copyright © 2010 by ASME

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