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Thermal-Enhanced and Cost-Effective 3D IC Integration With TSV (Through-Silicon Via) Interposers for High-Performance Applications

[+] Author Affiliations
John H. Lau

Industrial Technology Research Institute, Hsinchu, Taiwan

Y. S. Chan, S. W. Ricky Lee

The Hong Kong University of Science and Technology, Hong Kong, China

Paper No. IMECE2010-40975, pp. 137-144; 8 pages
  • ASME 2010 International Mechanical Engineering Congress and Exposition
  • Volume 4: Electronics and Photonics
  • Vancouver, British Columbia, Canada, November 12–18, 2010
  • Conference Sponsors: ASME
  • ISBN: 978-0-7918-4428-1
  • Copyright © 2010 by ASME


A low-cost (with bare chips) and high (electrical, thermal, and mechanical) performance 3D IC integration system-in-package (SiP) is designed and described. This system consists of a silicon interposer with through-silicon vias (TSV) [1–24] and redistribution layers (RDL), which carries the high-power flip chips with microbumps on its top surface and the low-power chips at its bottom surface. TSVs in the high- and low-power chips are optional but should be avoided. The backside of the high-power chips is attached to a heat spreader with or w/o a heat sink. This 3D IC integration system is supported (packaged) by a simple conventional organic substrate. The heat spreader (with or w/o heat sink) and the substrate are connected by a ring stiffener, which provides adequate standoff for the 3D IC integration system. This novel structural design offers potential solutions for high-power, high-performance, high pin-count, ultra fine-pitch, small real-estate, and low-cost applications. Thermal management and reliability of the proposed systems are demonstrated by simulations based on heat-transfer theory and time and temperature dependent creep theory.

Copyright © 2010 by ASME
Topics: Silicon



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