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Reliability Assessment of 3D Chip Stacking Package Using Metal Bonding and Through Silicon Via Technologies

[+] Author Affiliations
Shih-Yi Syu, Tuan-Yu Hung, Chao-Jen Huang, Han-Jung Wang, Kuo-Ning Chiang

National Tsing Hua University, HsinChu, Taiwan

Hsin-Li Lee

Industrial Technology Research Institute, HsinChu, Taiwan

Paper No. IMECE2010-40158, pp. 113-120; 8 pages
  • ASME 2010 International Mechanical Engineering Congress and Exposition
  • Volume 4: Electronics and Photonics
  • Vancouver, British Columbia, Canada, November 12–18, 2010
  • Conference Sponsors: ASME
  • ISBN: 978-0-7918-4428-1
  • Copyright © 2010 by ASME


In this study, the thermo-mechanical finite element (FE) analysis of the 3D chip stacking packaging is accomplished by employing the commercial software, ANSYS®. After manufacturing process, the thickness of the deposited material becomes variable. For the most part, this is due to the uncertainty of the manufacture process. In analyzing the effect of thickness difference, the process modeling technique is adopted. The technique can be demonstrated by comparing simulation results and the designed experiment for established chip displacement measurements. The out-of-plane displacement of the fabricated chip is measured by the Twyman-Green (T/G) interferometer. According to the results simulated by the validated process modeling technique, the effect of the thickness difference of the ABF layer is insignificant. In thermo-mechanical FE analysis, the thermal expansion of ABF material can induce stress concentration at the copper via. Moreover, thermal expansion of the ABF material and copper via can also affect the reliability of the silicon chip. Based on the design concept, the effect of the copper via diameter is analyzed. Based on the results, the stress concentration phenomenon at the copper via improves as the diameter increases. However, a larger thermal expansion of the copper via can damage the chip structure because of the larger diameter.

Copyright © 2010 by ASME



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