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Comparison of Enabling Wafer Bonding Techniques for TSV Integration

[+] Author Affiliations
Bioh Kim

EV Group, Inc., Tempe, AZ

Thorsten Matthias, Markus Wimplinger, Paul Kettner, Paul Lindner

EV Group, Florian/Inn, Austria

Paper No. IMECE2010-40002, pp. 97-104; 8 pages
  • ASME 2010 International Mechanical Engineering Congress and Exposition
  • Volume 4: Electronics and Photonics
  • Vancouver, British Columbia, Canada, November 12–18, 2010
  • Conference Sponsors: ASME
  • ISBN: 978-0-7918-4428-1
  • Copyright © 2010 by ASME


In this study are compared the technical merits and demerits of three bonding methods suitable for manufacturing 3D-ICs. Patterned metal thermo-compression bonding facilitates fine-pitch, high-density TSV stacking with lower electrical resistance and higher mechanical strength. Direct Cu-Cu bonding is preferred over transient liquid phase bonding with Sn or Sn alloys, but reliable Cu-Cu bonds result only from high process temperature and long process time. Both bonding temperature and post-bond annealing temperature have the most significant influence on Cu-Cu bond properties. The pre-bonding of silicon oxide bonds occurs at room temperature and thus does not induce any run-out errors in wafer alignment, resulting in higher post-bond alignment accuracy. Subsequent heating to high temperatures is necessary to achieve covalent bonds, but modifying the surface chemistry by plasma activation allows the formation of strong chemical bonds at significantly lower annealing temperatures (200–400°C). Adhesive bonding has such advantages as low bonding temperature and process time compared to metal bonding, the tolerance to wafer topography and surface conditions, and the ability to join any wafer materials. However, the material reflow imposes some challenges for maintaining the alignment accuracy and another major concern is the reliability of polymer adhesives during the post-bond processes.

Copyright © 2010 by ASME



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