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State-of-the-Art and Trends in Through-Silicon Via (TSV) and 3D Integrations

[+] Author Affiliations
John H. Lau

Industrial Technology Research Institute (ITRI), Chutung, Hsinchu, Taiwan

Paper No. IMECE2010-37783, pp. 69-78; 10 pages
  • ASME 2010 International Mechanical Engineering Congress and Exposition
  • Volume 4: Electronics and Photonics
  • Vancouver, British Columbia, Canada, November 12–18, 2010
  • Conference Sponsors: ASME
  • ISBN: 978-0-7918-4428-1
  • Copyright © 2010 by ASME


3D integration consists of 3D IC packaging, 3D IC integration, and 3D Si integration. They are different and in general the TSV (through-silicon via) separates 3D IC packaging from 3D IC integration and 3D Si integration since the latter two use TSV but 3D IC packaging does not. TSV (with a new concept that every chip could have two surfaces with circuits) is the focus of this investigation. State-of-the-art, key differences, trends of these three technologies, and a 3D integration roadmap are presented.

Copyright © 2010 by ASME
Topics: Silicon



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