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Approximate Analytical Model for a First Level Package With Non-Uniformly Powered Die

[+] Author Affiliations
Abhijit Kaisare, Dereje Agonafer, A. Haji-Sheikh

University of Texas at Arlington

Greg Chrysler, Ravi Mahajan

Intel Corporation

Paper No. IMECE2006-13436, pp. 43-49; 7 pages
  • ASME 2006 International Mechanical Engineering Congress and Exposition
  • Heat Transfer, Volume 3
  • Chicago, Illinois, USA, November 5 – 10, 2006
  • Conference Sponsors: Heat Transfer Division
  • ISBN: 0-7918-4786-1 | eISBN: 0-7918-3790-4
  • Copyright © 2006 by ASME


Microprocessors continue to grow in capabilities, complexity and performance. Microprocessors typically integrate functional components such as logic and level two (L2) cache memory in their architecture. This functional integration of logic and memory results in improved performance of the microprocessor as the clock speed increases and the instruction execution time has decreased. However, the integration also introduces a layer of complexity to the thermal design and management of microprocessors. As a direct result of function integration, the power map on a microprocessor is typically highly non-uniform and the assumption of a uniform heat flux across the chip surface is not valid. The active side of the die is divided into several functional blocks with distinct power assigned to each functional block. Previous work [1,2] has been done to minimize the thermal resistance of the package by optimizing the distribution of the non-uniform powered functional blocks with different power matrices. This study further gives design guideline and key pointers to minimized thermal resistance for any number of functional blocks for a given non-uniformly powered microprocessor. In this paper, initially (Part I) temperature distribution of a typical package consisting of a uniformly powered die, heat spreader, TIM 1 & 2 and the base of the heat sink is calculated using an approximate analytical model. The results are then compared with a detailed numerical model and the agreement is within 5%. This study follows (Part II) with a thermal investigation of non-uniform powered functional blocks with a different power matrices with focus on distribution of power over die surface with an application of maximum, minimum and average uniform junction temperature over a given die area. This will help to predict the trend of the calculated distribution of power that will lead to the least thermal gradient over a given die area. This trend will further help to come up with design correlations for minimizing thermal resistance for any number of functional blocks for a given non-uniformly powered microprocessor numerically as well as analytically. The commercial finite element code ANSYS® is used for this analysis as a numerical tool.

Copyright © 2006 by ASME



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