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High Accuracy Thermal Analysis Methodology for Semiconductor Junction Temperatures Considering Line Patterns of Multilayered Circuit Boards

[+] Author Affiliations
Yutaka Kumano, Tetsuyoshi Ogura, Toru Yamada

Matsushita Electric Industrial Co., Ltd., Kadoma, Osaka, Japan

Paper No. IPACK2007-33372, pp. 631-636; 6 pages
  • ASME 2007 InterPACK Conference collocated with the ASME/JSME 2007 Thermal Engineering Heat Transfer Summer Conference
  • ASME 2007 InterPACK Conference, Volume 2
  • Vancouver, British Columbia, Canada, July 8–12, 2007
  • Conference Sponsors: Electronic and Photonic Packaging Division
  • ISBN: 0-7918-4278-9 | eISBN: 0-7918-3801-3
  • Copyright © 2007 by ASME


As multilayered circuit boards in which semiconductors are embedded have been well reported, thermal management is becoming quite an important issue. In order to predict the junction temperature of an embedded semiconductor precisely, it is necessary that line patterns should be taken into consideration for thermal fluid analysis. However modeling all the patterns correctly is unacceptable because of far too long calculation time. Thus only the ratio of a pattern area to a gross board area was considered, which caused up to 30% calculation error compared to the experimental results. We have developed a novel method to predict semiconductor junction temperatures precisely without modeling patterns themselves. Firstly boards are divided into multiple regions in order to express how much dense or coarse the patterns are. Since the size of each region is much larger than L/S (line and space) specification of the boards, the number of meshes for calculation does not increase explosively and the simulation can be finished within appropriate time. Secondly equivalent anisotropic thermal conductivity of each region is assigned as follows. All the regions are once divided into smaller subregions whose sizes are approximately L/S specification. Then thermal conductivity of each subregion is defined by the property of the material at the centered subregion. After that a thermal network composed of all the subregions is generated and anisotropic thermal conductivities of each divided region are computed by solving this thermal network matrix. This procedure should be executed in an electrical CAD (E-CAD) where line pattern data are stored. A new interface format using which we can transfer board data from E-CAD to thermal fluid simulator was prepared. This format can have not only layouts and sizes but also anisotropic thermal conductivities of all divided regions. There is no need either to prepare model geometries or to input attributes of a great number of divided regions on thermal fluid simulator. By way of this format, analytical models are imported in thermal fluid simulator and semiconductor junction temperatures are computed. It was confirmed that semiconductor junction temperatures calculated by this method were precisely coincident with the experimental results. We can predict semiconductor temperatures without making preproduction samples. This analysis methodology will highly contribute to the reduction of designing time and cost.

Copyright © 2007 by ASME



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